1// Generated by opcode_generator.rb from /home/ubuntu/webkit/Source/JavaScriptCore/b3/air/AirOpcode.opcodes -- do not edit!
2#ifndef AirOpcodeGenerated_h
3#define AirOpcodeGenerated_h
4#include "AirInstInlines.h"
5#include "wtf/PrintStream.h"
6namespace WTF {
7using namespace JSC::B3::Air;
8void printInternal(PrintStream& out, Opcode opcode)
9{
10 switch (opcode) {
11 case Opcode::Nop:
12 out.print("Nop");
13 return;
14 case Opcode::Add32:
15 out.print("Add32");
16 return;
17 case Opcode::Add8:
18 out.print("Add8");
19 return;
20 case Opcode::Add16:
21 out.print("Add16");
22 return;
23 case Opcode::Add64:
24 out.print("Add64");
25 return;
26 case Opcode::AddDouble:
27 out.print("AddDouble");
28 return;
29 case Opcode::AddFloat:
30 out.print("AddFloat");
31 return;
32 case Opcode::Sub32:
33 out.print("Sub32");
34 return;
35 case Opcode::Sub64:
36 out.print("Sub64");
37 return;
38 case Opcode::SubDouble:
39 out.print("SubDouble");
40 return;
41 case Opcode::SubFloat:
42 out.print("SubFloat");
43 return;
44 case Opcode::Neg32:
45 out.print("Neg32");
46 return;
47 case Opcode::Neg64:
48 out.print("Neg64");
49 return;
50 case Opcode::NegateDouble:
51 out.print("NegateDouble");
52 return;
53 case Opcode::NegateFloat:
54 out.print("NegateFloat");
55 return;
56 case Opcode::Mul32:
57 out.print("Mul32");
58 return;
59 case Opcode::Mul64:
60 out.print("Mul64");
61 return;
62 case Opcode::MultiplyAdd32:
63 out.print("MultiplyAdd32");
64 return;
65 case Opcode::MultiplyAdd64:
66 out.print("MultiplyAdd64");
67 return;
68 case Opcode::MultiplySub32:
69 out.print("MultiplySub32");
70 return;
71 case Opcode::MultiplySub64:
72 out.print("MultiplySub64");
73 return;
74 case Opcode::MultiplyNeg32:
75 out.print("MultiplyNeg32");
76 return;
77 case Opcode::MultiplyNeg64:
78 out.print("MultiplyNeg64");
79 return;
80 case Opcode::Div32:
81 out.print("Div32");
82 return;
83 case Opcode::UDiv32:
84 out.print("UDiv32");
85 return;
86 case Opcode::Div64:
87 out.print("Div64");
88 return;
89 case Opcode::UDiv64:
90 out.print("UDiv64");
91 return;
92 case Opcode::MulDouble:
93 out.print("MulDouble");
94 return;
95 case Opcode::MulFloat:
96 out.print("MulFloat");
97 return;
98 case Opcode::DivDouble:
99 out.print("DivDouble");
100 return;
101 case Opcode::DivFloat:
102 out.print("DivFloat");
103 return;
104 case Opcode::X86ConvertToDoubleWord32:
105 out.print("X86ConvertToDoubleWord32");
106 return;
107 case Opcode::X86ConvertToQuadWord64:
108 out.print("X86ConvertToQuadWord64");
109 return;
110 case Opcode::X86Div32:
111 out.print("X86Div32");
112 return;
113 case Opcode::X86UDiv32:
114 out.print("X86UDiv32");
115 return;
116 case Opcode::X86Div64:
117 out.print("X86Div64");
118 return;
119 case Opcode::X86UDiv64:
120 out.print("X86UDiv64");
121 return;
122 case Opcode::Lea32:
123 out.print("Lea32");
124 return;
125 case Opcode::Lea64:
126 out.print("Lea64");
127 return;
128 case Opcode::And32:
129 out.print("And32");
130 return;
131 case Opcode::And64:
132 out.print("And64");
133 return;
134 case Opcode::AndDouble:
135 out.print("AndDouble");
136 return;
137 case Opcode::AndFloat:
138 out.print("AndFloat");
139 return;
140 case Opcode::OrDouble:
141 out.print("OrDouble");
142 return;
143 case Opcode::OrFloat:
144 out.print("OrFloat");
145 return;
146 case Opcode::XorDouble:
147 out.print("XorDouble");
148 return;
149 case Opcode::XorFloat:
150 out.print("XorFloat");
151 return;
152 case Opcode::Lshift32:
153 out.print("Lshift32");
154 return;
155 case Opcode::Lshift64:
156 out.print("Lshift64");
157 return;
158 case Opcode::Rshift32:
159 out.print("Rshift32");
160 return;
161 case Opcode::Rshift64:
162 out.print("Rshift64");
163 return;
164 case Opcode::Urshift32:
165 out.print("Urshift32");
166 return;
167 case Opcode::Urshift64:
168 out.print("Urshift64");
169 return;
170 case Opcode::RotateRight32:
171 out.print("RotateRight32");
172 return;
173 case Opcode::RotateRight64:
174 out.print("RotateRight64");
175 return;
176 case Opcode::RotateLeft32:
177 out.print("RotateLeft32");
178 return;
179 case Opcode::RotateLeft64:
180 out.print("RotateLeft64");
181 return;
182 case Opcode::Or32:
183 out.print("Or32");
184 return;
185 case Opcode::Or64:
186 out.print("Or64");
187 return;
188 case Opcode::Xor32:
189 out.print("Xor32");
190 return;
191 case Opcode::Xor64:
192 out.print("Xor64");
193 return;
194 case Opcode::Not32:
195 out.print("Not32");
196 return;
197 case Opcode::Not64:
198 out.print("Not64");
199 return;
200 case Opcode::AbsDouble:
201 out.print("AbsDouble");
202 return;
203 case Opcode::AbsFloat:
204 out.print("AbsFloat");
205 return;
206 case Opcode::CeilDouble:
207 out.print("CeilDouble");
208 return;
209 case Opcode::CeilFloat:
210 out.print("CeilFloat");
211 return;
212 case Opcode::FloorDouble:
213 out.print("FloorDouble");
214 return;
215 case Opcode::FloorFloat:
216 out.print("FloorFloat");
217 return;
218 case Opcode::SqrtDouble:
219 out.print("SqrtDouble");
220 return;
221 case Opcode::SqrtFloat:
222 out.print("SqrtFloat");
223 return;
224 case Opcode::ConvertInt32ToDouble:
225 out.print("ConvertInt32ToDouble");
226 return;
227 case Opcode::ConvertInt64ToDouble:
228 out.print("ConvertInt64ToDouble");
229 return;
230 case Opcode::ConvertInt32ToFloat:
231 out.print("ConvertInt32ToFloat");
232 return;
233 case Opcode::ConvertInt64ToFloat:
234 out.print("ConvertInt64ToFloat");
235 return;
236 case Opcode::CountLeadingZeros32:
237 out.print("CountLeadingZeros32");
238 return;
239 case Opcode::CountLeadingZeros64:
240 out.print("CountLeadingZeros64");
241 return;
242 case Opcode::ConvertDoubleToFloat:
243 out.print("ConvertDoubleToFloat");
244 return;
245 case Opcode::ConvertFloatToDouble:
246 out.print("ConvertFloatToDouble");
247 return;
248 case Opcode::Move:
249 out.print("Move");
250 return;
251 case Opcode::Swap32:
252 out.print("Swap32");
253 return;
254 case Opcode::Swap64:
255 out.print("Swap64");
256 return;
257 case Opcode::Move32:
258 out.print("Move32");
259 return;
260 case Opcode::StoreZero32:
261 out.print("StoreZero32");
262 return;
263 case Opcode::StoreZero64:
264 out.print("StoreZero64");
265 return;
266 case Opcode::SignExtend32ToPtr:
267 out.print("SignExtend32ToPtr");
268 return;
269 case Opcode::ZeroExtend8To32:
270 out.print("ZeroExtend8To32");
271 return;
272 case Opcode::SignExtend8To32:
273 out.print("SignExtend8To32");
274 return;
275 case Opcode::ZeroExtend16To32:
276 out.print("ZeroExtend16To32");
277 return;
278 case Opcode::SignExtend16To32:
279 out.print("SignExtend16To32");
280 return;
281 case Opcode::MoveFloat:
282 out.print("MoveFloat");
283 return;
284 case Opcode::MoveDouble:
285 out.print("MoveDouble");
286 return;
287 case Opcode::MoveZeroToDouble:
288 out.print("MoveZeroToDouble");
289 return;
290 case Opcode::Move64ToDouble:
291 out.print("Move64ToDouble");
292 return;
293 case Opcode::Move32ToFloat:
294 out.print("Move32ToFloat");
295 return;
296 case Opcode::MoveDoubleTo64:
297 out.print("MoveDoubleTo64");
298 return;
299 case Opcode::MoveFloatTo32:
300 out.print("MoveFloatTo32");
301 return;
302 case Opcode::Load8:
303 out.print("Load8");
304 return;
305 case Opcode::LoadAcq8:
306 out.print("LoadAcq8");
307 return;
308 case Opcode::Store8:
309 out.print("Store8");
310 return;
311 case Opcode::StoreRel8:
312 out.print("StoreRel8");
313 return;
314 case Opcode::Load8SignedExtendTo32:
315 out.print("Load8SignedExtendTo32");
316 return;
317 case Opcode::LoadAcq8SignedExtendTo32:
318 out.print("LoadAcq8SignedExtendTo32");
319 return;
320 case Opcode::Load16:
321 out.print("Load16");
322 return;
323 case Opcode::LoadAcq16:
324 out.print("LoadAcq16");
325 return;
326 case Opcode::Load16SignedExtendTo32:
327 out.print("Load16SignedExtendTo32");
328 return;
329 case Opcode::LoadAcq16SignedExtendTo32:
330 out.print("LoadAcq16SignedExtendTo32");
331 return;
332 case Opcode::Store16:
333 out.print("Store16");
334 return;
335 case Opcode::StoreRel16:
336 out.print("StoreRel16");
337 return;
338 case Opcode::LoadAcq32:
339 out.print("LoadAcq32");
340 return;
341 case Opcode::StoreRel32:
342 out.print("StoreRel32");
343 return;
344 case Opcode::LoadAcq64:
345 out.print("LoadAcq64");
346 return;
347 case Opcode::StoreRel64:
348 out.print("StoreRel64");
349 return;
350 case Opcode::Xchg8:
351 out.print("Xchg8");
352 return;
353 case Opcode::Xchg16:
354 out.print("Xchg16");
355 return;
356 case Opcode::Xchg32:
357 out.print("Xchg32");
358 return;
359 case Opcode::Xchg64:
360 out.print("Xchg64");
361 return;
362 case Opcode::AtomicStrongCAS8:
363 out.print("AtomicStrongCAS8");
364 return;
365 case Opcode::AtomicStrongCAS16:
366 out.print("AtomicStrongCAS16");
367 return;
368 case Opcode::AtomicStrongCAS32:
369 out.print("AtomicStrongCAS32");
370 return;
371 case Opcode::AtomicStrongCAS64:
372 out.print("AtomicStrongCAS64");
373 return;
374 case Opcode::BranchAtomicStrongCAS8:
375 out.print("BranchAtomicStrongCAS8");
376 return;
377 case Opcode::BranchAtomicStrongCAS16:
378 out.print("BranchAtomicStrongCAS16");
379 return;
380 case Opcode::BranchAtomicStrongCAS32:
381 out.print("BranchAtomicStrongCAS32");
382 return;
383 case Opcode::BranchAtomicStrongCAS64:
384 out.print("BranchAtomicStrongCAS64");
385 return;
386 case Opcode::AtomicAdd8:
387 out.print("AtomicAdd8");
388 return;
389 case Opcode::AtomicAdd16:
390 out.print("AtomicAdd16");
391 return;
392 case Opcode::AtomicAdd32:
393 out.print("AtomicAdd32");
394 return;
395 case Opcode::AtomicAdd64:
396 out.print("AtomicAdd64");
397 return;
398 case Opcode::AtomicSub8:
399 out.print("AtomicSub8");
400 return;
401 case Opcode::AtomicSub16:
402 out.print("AtomicSub16");
403 return;
404 case Opcode::AtomicSub32:
405 out.print("AtomicSub32");
406 return;
407 case Opcode::AtomicSub64:
408 out.print("AtomicSub64");
409 return;
410 case Opcode::AtomicAnd8:
411 out.print("AtomicAnd8");
412 return;
413 case Opcode::AtomicAnd16:
414 out.print("AtomicAnd16");
415 return;
416 case Opcode::AtomicAnd32:
417 out.print("AtomicAnd32");
418 return;
419 case Opcode::AtomicAnd64:
420 out.print("AtomicAnd64");
421 return;
422 case Opcode::AtomicOr8:
423 out.print("AtomicOr8");
424 return;
425 case Opcode::AtomicOr16:
426 out.print("AtomicOr16");
427 return;
428 case Opcode::AtomicOr32:
429 out.print("AtomicOr32");
430 return;
431 case Opcode::AtomicOr64:
432 out.print("AtomicOr64");
433 return;
434 case Opcode::AtomicXor8:
435 out.print("AtomicXor8");
436 return;
437 case Opcode::AtomicXor16:
438 out.print("AtomicXor16");
439 return;
440 case Opcode::AtomicXor32:
441 out.print("AtomicXor32");
442 return;
443 case Opcode::AtomicXor64:
444 out.print("AtomicXor64");
445 return;
446 case Opcode::AtomicNeg8:
447 out.print("AtomicNeg8");
448 return;
449 case Opcode::AtomicNeg16:
450 out.print("AtomicNeg16");
451 return;
452 case Opcode::AtomicNeg32:
453 out.print("AtomicNeg32");
454 return;
455 case Opcode::AtomicNeg64:
456 out.print("AtomicNeg64");
457 return;
458 case Opcode::AtomicNot8:
459 out.print("AtomicNot8");
460 return;
461 case Opcode::AtomicNot16:
462 out.print("AtomicNot16");
463 return;
464 case Opcode::AtomicNot32:
465 out.print("AtomicNot32");
466 return;
467 case Opcode::AtomicNot64:
468 out.print("AtomicNot64");
469 return;
470 case Opcode::AtomicXchgAdd8:
471 out.print("AtomicXchgAdd8");
472 return;
473 case Opcode::AtomicXchgAdd16:
474 out.print("AtomicXchgAdd16");
475 return;
476 case Opcode::AtomicXchgAdd32:
477 out.print("AtomicXchgAdd32");
478 return;
479 case Opcode::AtomicXchgAdd64:
480 out.print("AtomicXchgAdd64");
481 return;
482 case Opcode::AtomicXchg8:
483 out.print("AtomicXchg8");
484 return;
485 case Opcode::AtomicXchg16:
486 out.print("AtomicXchg16");
487 return;
488 case Opcode::AtomicXchg32:
489 out.print("AtomicXchg32");
490 return;
491 case Opcode::AtomicXchg64:
492 out.print("AtomicXchg64");
493 return;
494 case Opcode::LoadLink8:
495 out.print("LoadLink8");
496 return;
497 case Opcode::LoadLinkAcq8:
498 out.print("LoadLinkAcq8");
499 return;
500 case Opcode::StoreCond8:
501 out.print("StoreCond8");
502 return;
503 case Opcode::StoreCondRel8:
504 out.print("StoreCondRel8");
505 return;
506 case Opcode::LoadLink16:
507 out.print("LoadLink16");
508 return;
509 case Opcode::LoadLinkAcq16:
510 out.print("LoadLinkAcq16");
511 return;
512 case Opcode::StoreCond16:
513 out.print("StoreCond16");
514 return;
515 case Opcode::StoreCondRel16:
516 out.print("StoreCondRel16");
517 return;
518 case Opcode::LoadLink32:
519 out.print("LoadLink32");
520 return;
521 case Opcode::LoadLinkAcq32:
522 out.print("LoadLinkAcq32");
523 return;
524 case Opcode::StoreCond32:
525 out.print("StoreCond32");
526 return;
527 case Opcode::StoreCondRel32:
528 out.print("StoreCondRel32");
529 return;
530 case Opcode::LoadLink64:
531 out.print("LoadLink64");
532 return;
533 case Opcode::LoadLinkAcq64:
534 out.print("LoadLinkAcq64");
535 return;
536 case Opcode::StoreCond64:
537 out.print("StoreCond64");
538 return;
539 case Opcode::StoreCondRel64:
540 out.print("StoreCondRel64");
541 return;
542 case Opcode::Depend32:
543 out.print("Depend32");
544 return;
545 case Opcode::Depend64:
546 out.print("Depend64");
547 return;
548 case Opcode::Compare32:
549 out.print("Compare32");
550 return;
551 case Opcode::Compare64:
552 out.print("Compare64");
553 return;
554 case Opcode::Test32:
555 out.print("Test32");
556 return;
557 case Opcode::Test64:
558 out.print("Test64");
559 return;
560 case Opcode::CompareDouble:
561 out.print("CompareDouble");
562 return;
563 case Opcode::CompareFloat:
564 out.print("CompareFloat");
565 return;
566 case Opcode::Branch8:
567 out.print("Branch8");
568 return;
569 case Opcode::Branch32:
570 out.print("Branch32");
571 return;
572 case Opcode::Branch64:
573 out.print("Branch64");
574 return;
575 case Opcode::BranchTest8:
576 out.print("BranchTest8");
577 return;
578 case Opcode::BranchTest32:
579 out.print("BranchTest32");
580 return;
581 case Opcode::BranchTest64:
582 out.print("BranchTest64");
583 return;
584 case Opcode::BranchDouble:
585 out.print("BranchDouble");
586 return;
587 case Opcode::BranchFloat:
588 out.print("BranchFloat");
589 return;
590 case Opcode::BranchAdd32:
591 out.print("BranchAdd32");
592 return;
593 case Opcode::BranchAdd64:
594 out.print("BranchAdd64");
595 return;
596 case Opcode::BranchMul32:
597 out.print("BranchMul32");
598 return;
599 case Opcode::BranchMul64:
600 out.print("BranchMul64");
601 return;
602 case Opcode::BranchSub32:
603 out.print("BranchSub32");
604 return;
605 case Opcode::BranchSub64:
606 out.print("BranchSub64");
607 return;
608 case Opcode::BranchNeg32:
609 out.print("BranchNeg32");
610 return;
611 case Opcode::BranchNeg64:
612 out.print("BranchNeg64");
613 return;
614 case Opcode::MoveConditionally32:
615 out.print("MoveConditionally32");
616 return;
617 case Opcode::MoveConditionally64:
618 out.print("MoveConditionally64");
619 return;
620 case Opcode::MoveConditionallyTest32:
621 out.print("MoveConditionallyTest32");
622 return;
623 case Opcode::MoveConditionallyTest64:
624 out.print("MoveConditionallyTest64");
625 return;
626 case Opcode::MoveConditionallyDouble:
627 out.print("MoveConditionallyDouble");
628 return;
629 case Opcode::MoveConditionallyFloat:
630 out.print("MoveConditionallyFloat");
631 return;
632 case Opcode::MoveDoubleConditionally32:
633 out.print("MoveDoubleConditionally32");
634 return;
635 case Opcode::MoveDoubleConditionally64:
636 out.print("MoveDoubleConditionally64");
637 return;
638 case Opcode::MoveDoubleConditionallyTest32:
639 out.print("MoveDoubleConditionallyTest32");
640 return;
641 case Opcode::MoveDoubleConditionallyTest64:
642 out.print("MoveDoubleConditionallyTest64");
643 return;
644 case Opcode::MoveDoubleConditionallyDouble:
645 out.print("MoveDoubleConditionallyDouble");
646 return;
647 case Opcode::MoveDoubleConditionallyFloat:
648 out.print("MoveDoubleConditionallyFloat");
649 return;
650 case Opcode::MemoryFence:
651 out.print("MemoryFence");
652 return;
653 case Opcode::StoreFence:
654 out.print("StoreFence");
655 return;
656 case Opcode::LoadFence:
657 out.print("LoadFence");
658 return;
659 case Opcode::Jump:
660 out.print("Jump");
661 return;
662 case Opcode::RetVoid:
663 out.print("RetVoid");
664 return;
665 case Opcode::Ret32:
666 out.print("Ret32");
667 return;
668 case Opcode::Ret64:
669 out.print("Ret64");
670 return;
671 case Opcode::RetFloat:
672 out.print("RetFloat");
673 return;
674 case Opcode::RetDouble:
675 out.print("RetDouble");
676 return;
677 case Opcode::Oops:
678 out.print("Oops");
679 return;
680 case Opcode::EntrySwitch:
681 out.print("EntrySwitch");
682 return;
683 case Opcode::Shuffle:
684 out.print("Shuffle");
685 return;
686 case Opcode::Patch:
687 out.print("Patch");
688 return;
689 case Opcode::CCall:
690 out.print("CCall");
691 return;
692 case Opcode::ColdCCall:
693 out.print("ColdCCall");
694 return;
695 case Opcode::WasmBoundsCheck:
696 out.print("WasmBoundsCheck");
697 return;
698 }
699 RELEASE_ASSERT_NOT_REACHED();
700}
701} // namespace WTF
702namespace JSC { namespace B3 { namespace Air {
703const uint8_t g_formTable[4809] = {
704// Nop
705
706// Invalid: Nop with numOperands = 1
707INVALID_INST_FORM,
708// Invalid: Nop with numOperands = 2
709INVALID_INST_FORM, INVALID_INST_FORM,
710// Invalid: Nop with numOperands = 3
711INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
712// Invalid: Nop with numOperands = 4
713INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
714// Invalid: Nop with numOperands = 5
715INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
716// Invalid: Nop with numOperands = 6
717INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
718// Invalid: Add32 with numOperands = 0
719
720// Invalid: Add32 with numOperands = 1
721INVALID_INST_FORM,
722// Add32 U:G:32, UZD:G:32
723ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
724// Add32 U:G:32, U:G:32, ZD:G:32
725ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
726// Invalid: Add32 with numOperands = 4
727INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
728// Invalid: Add32 with numOperands = 5
729INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
730// Invalid: Add32 with numOperands = 6
731INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
732// Invalid: Add8 with numOperands = 0
733
734// Invalid: Add8 with numOperands = 1
735INVALID_INST_FORM,
736// Add8 U:G:8, UD:G:8
737ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
738// Invalid: Add8 with numOperands = 3
739INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
740// Invalid: Add8 with numOperands = 4
741INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
742// Invalid: Add8 with numOperands = 5
743INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
744// Invalid: Add8 with numOperands = 6
745INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
746// Invalid: Add16 with numOperands = 0
747
748// Invalid: Add16 with numOperands = 1
749INVALID_INST_FORM,
750// Add16 U:G:16, UD:G:16
751ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
752// Invalid: Add16 with numOperands = 3
753INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
754// Invalid: Add16 with numOperands = 4
755INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
756// Invalid: Add16 with numOperands = 5
757INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
758// Invalid: Add16 with numOperands = 6
759INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
760// Invalid: Add64 with numOperands = 0
761
762// Invalid: Add64 with numOperands = 1
763INVALID_INST_FORM,
764// Add64 U:G:64, UD:G:64
765ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
766// Add64 U:G:64, U:G:64, D:G:64
767ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
768// Invalid: Add64 with numOperands = 4
769INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
770// Invalid: Add64 with numOperands = 5
771INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
772// Invalid: Add64 with numOperands = 6
773INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
774// Invalid: AddDouble with numOperands = 0
775
776// Invalid: AddDouble with numOperands = 1
777INVALID_INST_FORM,
778// AddDouble U:F:64, UD:F:64
779ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
780// AddDouble U:F:64, U:F:64, D:F:64
781ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
782// Invalid: AddDouble with numOperands = 4
783INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
784// Invalid: AddDouble with numOperands = 5
785INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
786// Invalid: AddDouble with numOperands = 6
787INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
788// Invalid: AddFloat with numOperands = 0
789
790// Invalid: AddFloat with numOperands = 1
791INVALID_INST_FORM,
792// AddFloat U:F:32, UD:F:32
793ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
794// AddFloat U:F:32, U:F:32, D:F:32
795ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
796// Invalid: AddFloat with numOperands = 4
797INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
798// Invalid: AddFloat with numOperands = 5
799INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
800// Invalid: AddFloat with numOperands = 6
801INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
802// Invalid: Sub32 with numOperands = 0
803
804// Invalid: Sub32 with numOperands = 1
805INVALID_INST_FORM,
806// Sub32 U:G:32, UZD:G:32
807ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
808// Sub32 U:G:32, U:G:32, D:G:32
809ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32),
810// Invalid: Sub32 with numOperands = 4
811INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
812// Invalid: Sub32 with numOperands = 5
813INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
814// Invalid: Sub32 with numOperands = 6
815INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
816// Invalid: Sub64 with numOperands = 0
817
818// Invalid: Sub64 with numOperands = 1
819INVALID_INST_FORM,
820// Sub64 U:G:64, UD:G:64
821ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
822// Sub64 U:G:64, U:G:64, D:G:64
823ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
824// Invalid: Sub64 with numOperands = 4
825INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
826// Invalid: Sub64 with numOperands = 5
827INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
828// Invalid: Sub64 with numOperands = 6
829INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
830// Invalid: SubDouble with numOperands = 0
831
832// Invalid: SubDouble with numOperands = 1
833INVALID_INST_FORM,
834// SubDouble U:F:64, UD:F:64
835ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
836// SubDouble U:F:64, U:F:64, D:F:64
837ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
838// Invalid: SubDouble with numOperands = 4
839INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
840// Invalid: SubDouble with numOperands = 5
841INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
842// Invalid: SubDouble with numOperands = 6
843INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
844// Invalid: SubFloat with numOperands = 0
845
846// Invalid: SubFloat with numOperands = 1
847INVALID_INST_FORM,
848// SubFloat U:F:32, UD:F:32
849ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
850// SubFloat U:F:32, U:F:32, D:F:32
851ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
852// Invalid: SubFloat with numOperands = 4
853INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
854// Invalid: SubFloat with numOperands = 5
855INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
856// Invalid: SubFloat with numOperands = 6
857INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
858// Invalid: Neg32 with numOperands = 0
859
860// Neg32 UZD:G:32
861ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
862// Invalid: Neg32 with numOperands = 2
863INVALID_INST_FORM, INVALID_INST_FORM,
864// Invalid: Neg32 with numOperands = 3
865INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
866// Invalid: Neg32 with numOperands = 4
867INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
868// Invalid: Neg32 with numOperands = 5
869INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
870// Invalid: Neg32 with numOperands = 6
871INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
872// Invalid: Neg64 with numOperands = 0
873
874// Neg64 UD:G:64
875ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
876// Invalid: Neg64 with numOperands = 2
877INVALID_INST_FORM, INVALID_INST_FORM,
878// Invalid: Neg64 with numOperands = 3
879INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
880// Invalid: Neg64 with numOperands = 4
881INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
882// Invalid: Neg64 with numOperands = 5
883INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
884// Invalid: Neg64 with numOperands = 6
885INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
886// Invalid: NegateDouble with numOperands = 0
887
888// Invalid: NegateDouble with numOperands = 1
889INVALID_INST_FORM,
890// NegateDouble U:F:64, D:F:64
891ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
892// Invalid: NegateDouble with numOperands = 3
893INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
894// Invalid: NegateDouble with numOperands = 4
895INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
896// Invalid: NegateDouble with numOperands = 5
897INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
898// Invalid: NegateDouble with numOperands = 6
899INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
900// Invalid: NegateFloat with numOperands = 0
901
902// Invalid: NegateFloat with numOperands = 1
903INVALID_INST_FORM,
904// NegateFloat U:F:32, D:F:32
905ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
906// Invalid: NegateFloat with numOperands = 3
907INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
908// Invalid: NegateFloat with numOperands = 4
909INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
910// Invalid: NegateFloat with numOperands = 5
911INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
912// Invalid: NegateFloat with numOperands = 6
913INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
914// Invalid: Mul32 with numOperands = 0
915
916// Invalid: Mul32 with numOperands = 1
917INVALID_INST_FORM,
918// Mul32 U:G:32, UZD:G:32
919ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
920// Mul32 U:G:32, U:G:32, ZD:G:32
921ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
922// Invalid: Mul32 with numOperands = 4
923INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
924// Invalid: Mul32 with numOperands = 5
925INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
926// Invalid: Mul32 with numOperands = 6
927INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
928// Invalid: Mul64 with numOperands = 0
929
930// Invalid: Mul64 with numOperands = 1
931INVALID_INST_FORM,
932// Mul64 U:G:64, UD:G:64
933ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
934// Mul64 U:G:64, U:G:64, D:G:64
935ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
936// Invalid: Mul64 with numOperands = 4
937INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
938// Invalid: Mul64 with numOperands = 5
939INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
940// Invalid: Mul64 with numOperands = 6
941INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
942// Invalid: MultiplyAdd32 with numOperands = 0
943
944// Invalid: MultiplyAdd32 with numOperands = 1
945INVALID_INST_FORM,
946// Invalid: MultiplyAdd32 with numOperands = 2
947INVALID_INST_FORM, INVALID_INST_FORM,
948// Invalid: MultiplyAdd32 with numOperands = 3
949INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
950// MultiplyAdd32 U:G:32, U:G:32, U:G:32, ZD:G:32
951ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
952// Invalid: MultiplyAdd32 with numOperands = 5
953INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
954// Invalid: MultiplyAdd32 with numOperands = 6
955INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
956// Invalid: MultiplyAdd64 with numOperands = 0
957
958// Invalid: MultiplyAdd64 with numOperands = 1
959INVALID_INST_FORM,
960// Invalid: MultiplyAdd64 with numOperands = 2
961INVALID_INST_FORM, INVALID_INST_FORM,
962// Invalid: MultiplyAdd64 with numOperands = 3
963INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
964// MultiplyAdd64 U:G:64, U:G:64, U:G:64, D:G:64
965ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
966// Invalid: MultiplyAdd64 with numOperands = 5
967INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
968// Invalid: MultiplyAdd64 with numOperands = 6
969INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
970// Invalid: MultiplySub32 with numOperands = 0
971
972// Invalid: MultiplySub32 with numOperands = 1
973INVALID_INST_FORM,
974// Invalid: MultiplySub32 with numOperands = 2
975INVALID_INST_FORM, INVALID_INST_FORM,
976// Invalid: MultiplySub32 with numOperands = 3
977INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
978// MultiplySub32 U:G:32, U:G:32, U:G:32, ZD:G:32
979ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
980// Invalid: MultiplySub32 with numOperands = 5
981INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
982// Invalid: MultiplySub32 with numOperands = 6
983INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
984// Invalid: MultiplySub64 with numOperands = 0
985
986// Invalid: MultiplySub64 with numOperands = 1
987INVALID_INST_FORM,
988// Invalid: MultiplySub64 with numOperands = 2
989INVALID_INST_FORM, INVALID_INST_FORM,
990// Invalid: MultiplySub64 with numOperands = 3
991INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
992// MultiplySub64 U:G:64, U:G:64, U:G:64, D:G:64
993ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
994// Invalid: MultiplySub64 with numOperands = 5
995INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
996// Invalid: MultiplySub64 with numOperands = 6
997INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
998// Invalid: MultiplyNeg32 with numOperands = 0
999
1000// Invalid: MultiplyNeg32 with numOperands = 1
1001INVALID_INST_FORM,
1002// Invalid: MultiplyNeg32 with numOperands = 2
1003INVALID_INST_FORM, INVALID_INST_FORM,
1004// MultiplyNeg32 U:G:32, U:G:32, ZD:G:32
1005ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1006// Invalid: MultiplyNeg32 with numOperands = 4
1007INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1008// Invalid: MultiplyNeg32 with numOperands = 5
1009INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1010// Invalid: MultiplyNeg32 with numOperands = 6
1011INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1012// Invalid: MultiplyNeg64 with numOperands = 0
1013
1014// Invalid: MultiplyNeg64 with numOperands = 1
1015INVALID_INST_FORM,
1016// Invalid: MultiplyNeg64 with numOperands = 2
1017INVALID_INST_FORM, INVALID_INST_FORM,
1018// MultiplyNeg64 U:G:64, U:G:64, ZD:G:64
1019ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
1020// Invalid: MultiplyNeg64 with numOperands = 4
1021INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1022// Invalid: MultiplyNeg64 with numOperands = 5
1023INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1024// Invalid: MultiplyNeg64 with numOperands = 6
1025INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1026// Invalid: Div32 with numOperands = 0
1027
1028// Invalid: Div32 with numOperands = 1
1029INVALID_INST_FORM,
1030// Invalid: Div32 with numOperands = 2
1031INVALID_INST_FORM, INVALID_INST_FORM,
1032// Div32 U:G:32, U:G:32, ZD:G:32
1033ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1034// Invalid: Div32 with numOperands = 4
1035INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1036// Invalid: Div32 with numOperands = 5
1037INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1038// Invalid: Div32 with numOperands = 6
1039INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1040// Invalid: UDiv32 with numOperands = 0
1041
1042// Invalid: UDiv32 with numOperands = 1
1043INVALID_INST_FORM,
1044// Invalid: UDiv32 with numOperands = 2
1045INVALID_INST_FORM, INVALID_INST_FORM,
1046// UDiv32 U:G:32, U:G:32, ZD:G:32
1047ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1048// Invalid: UDiv32 with numOperands = 4
1049INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1050// Invalid: UDiv32 with numOperands = 5
1051INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1052// Invalid: UDiv32 with numOperands = 6
1053INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1054// Invalid: Div64 with numOperands = 0
1055
1056// Invalid: Div64 with numOperands = 1
1057INVALID_INST_FORM,
1058// Invalid: Div64 with numOperands = 2
1059INVALID_INST_FORM, INVALID_INST_FORM,
1060// Div64 U:G:64, U:G:64, D:G:64
1061ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1062// Invalid: Div64 with numOperands = 4
1063INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1064// Invalid: Div64 with numOperands = 5
1065INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1066// Invalid: Div64 with numOperands = 6
1067INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1068// Invalid: UDiv64 with numOperands = 0
1069
1070// Invalid: UDiv64 with numOperands = 1
1071INVALID_INST_FORM,
1072// Invalid: UDiv64 with numOperands = 2
1073INVALID_INST_FORM, INVALID_INST_FORM,
1074// UDiv64 U:G:64, U:G:64, D:G:64
1075ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1076// Invalid: UDiv64 with numOperands = 4
1077INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1078// Invalid: UDiv64 with numOperands = 5
1079INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1080// Invalid: UDiv64 with numOperands = 6
1081INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1082// Invalid: MulDouble with numOperands = 0
1083
1084// Invalid: MulDouble with numOperands = 1
1085INVALID_INST_FORM,
1086// MulDouble U:F:64, UD:F:64
1087ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1088// MulDouble U:F:64, U:F:64, D:F:64
1089ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1090// Invalid: MulDouble with numOperands = 4
1091INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1092// Invalid: MulDouble with numOperands = 5
1093INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1094// Invalid: MulDouble with numOperands = 6
1095INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1096// Invalid: MulFloat with numOperands = 0
1097
1098// Invalid: MulFloat with numOperands = 1
1099INVALID_INST_FORM,
1100// MulFloat U:F:32, UD:F:32
1101ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1102// MulFloat U:F:32, U:F:32, D:F:32
1103ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1104// Invalid: MulFloat with numOperands = 4
1105INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1106// Invalid: MulFloat with numOperands = 5
1107INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1108// Invalid: MulFloat with numOperands = 6
1109INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1110// Invalid: DivDouble with numOperands = 0
1111
1112// Invalid: DivDouble with numOperands = 1
1113INVALID_INST_FORM,
1114// DivDouble U:F:64, UD:F:64
1115ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1116// DivDouble U:F:64, U:F:32, D:F:64
1117ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1118// Invalid: DivDouble with numOperands = 4
1119INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1120// Invalid: DivDouble with numOperands = 5
1121INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1122// Invalid: DivDouble with numOperands = 6
1123INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1124// Invalid: DivFloat with numOperands = 0
1125
1126// Invalid: DivFloat with numOperands = 1
1127INVALID_INST_FORM,
1128// DivFloat U:F:32, UD:F:32
1129ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1130// DivFloat U:F:32, U:F:32, D:F:32
1131ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1132// Invalid: DivFloat with numOperands = 4
1133INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1134// Invalid: DivFloat with numOperands = 5
1135INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1136// Invalid: DivFloat with numOperands = 6
1137INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1138// Invalid: X86ConvertToDoubleWord32 with numOperands = 0
1139
1140// Invalid: X86ConvertToDoubleWord32 with numOperands = 1
1141INVALID_INST_FORM,
1142// X86ConvertToDoubleWord32 U:G:32, ZD:G:32
1143ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1144// Invalid: X86ConvertToDoubleWord32 with numOperands = 3
1145INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1146// Invalid: X86ConvertToDoubleWord32 with numOperands = 4
1147INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1148// Invalid: X86ConvertToDoubleWord32 with numOperands = 5
1149INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1150// Invalid: X86ConvertToDoubleWord32 with numOperands = 6
1151INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1152// Invalid: X86ConvertToQuadWord64 with numOperands = 0
1153
1154// Invalid: X86ConvertToQuadWord64 with numOperands = 1
1155INVALID_INST_FORM,
1156// X86ConvertToQuadWord64 U:G:64, D:G:64
1157ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1158// Invalid: X86ConvertToQuadWord64 with numOperands = 3
1159INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1160// Invalid: X86ConvertToQuadWord64 with numOperands = 4
1161INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1162// Invalid: X86ConvertToQuadWord64 with numOperands = 5
1163INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1164// Invalid: X86ConvertToQuadWord64 with numOperands = 6
1165INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1166// Invalid: X86Div32 with numOperands = 0
1167
1168// Invalid: X86Div32 with numOperands = 1
1169INVALID_INST_FORM,
1170// Invalid: X86Div32 with numOperands = 2
1171INVALID_INST_FORM, INVALID_INST_FORM,
1172// X86Div32 UZD:G:32, UZD:G:32, U:G:32
1173ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
1174// Invalid: X86Div32 with numOperands = 4
1175INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1176// Invalid: X86Div32 with numOperands = 5
1177INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1178// Invalid: X86Div32 with numOperands = 6
1179INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1180// Invalid: X86UDiv32 with numOperands = 0
1181
1182// Invalid: X86UDiv32 with numOperands = 1
1183INVALID_INST_FORM,
1184// Invalid: X86UDiv32 with numOperands = 2
1185INVALID_INST_FORM, INVALID_INST_FORM,
1186// X86UDiv32 UZD:G:32, UZD:G:32, U:G:32
1187ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
1188// Invalid: X86UDiv32 with numOperands = 4
1189INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1190// Invalid: X86UDiv32 with numOperands = 5
1191INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1192// Invalid: X86UDiv32 with numOperands = 6
1193INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1194// Invalid: X86Div64 with numOperands = 0
1195
1196// Invalid: X86Div64 with numOperands = 1
1197INVALID_INST_FORM,
1198// Invalid: X86Div64 with numOperands = 2
1199INVALID_INST_FORM, INVALID_INST_FORM,
1200// X86Div64 UZD:G:64, UZD:G:64, U:G:64
1201ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
1202// Invalid: X86Div64 with numOperands = 4
1203INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1204// Invalid: X86Div64 with numOperands = 5
1205INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1206// Invalid: X86Div64 with numOperands = 6
1207INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1208// Invalid: X86UDiv64 with numOperands = 0
1209
1210// Invalid: X86UDiv64 with numOperands = 1
1211INVALID_INST_FORM,
1212// Invalid: X86UDiv64 with numOperands = 2
1213INVALID_INST_FORM, INVALID_INST_FORM,
1214// X86UDiv64 UZD:G:64, UZD:G:64, U:G:64
1215ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
1216// Invalid: X86UDiv64 with numOperands = 4
1217INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1218// Invalid: X86UDiv64 with numOperands = 5
1219INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1220// Invalid: X86UDiv64 with numOperands = 6
1221INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1222// Invalid: Lea32 with numOperands = 0
1223
1224// Invalid: Lea32 with numOperands = 1
1225INVALID_INST_FORM,
1226// Lea32 UA:G:32, D:G:32
1227ENCODE_INST_FORM(Arg::UseAddr, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32),
1228// Invalid: Lea32 with numOperands = 3
1229INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1230// Invalid: Lea32 with numOperands = 4
1231INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1232// Invalid: Lea32 with numOperands = 5
1233INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1234// Invalid: Lea32 with numOperands = 6
1235INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1236// Invalid: Lea64 with numOperands = 0
1237
1238// Invalid: Lea64 with numOperands = 1
1239INVALID_INST_FORM,
1240// Lea64 UA:G:64, D:G:64
1241ENCODE_INST_FORM(Arg::UseAddr, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1242// Invalid: Lea64 with numOperands = 3
1243INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1244// Invalid: Lea64 with numOperands = 4
1245INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1246// Invalid: Lea64 with numOperands = 5
1247INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1248// Invalid: Lea64 with numOperands = 6
1249INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1250// Invalid: And32 with numOperands = 0
1251
1252// Invalid: And32 with numOperands = 1
1253INVALID_INST_FORM,
1254// And32 U:G:32, UZD:G:32
1255ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1256// And32 U:G:32, U:G:32, ZD:G:32
1257ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1258// Invalid: And32 with numOperands = 4
1259INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1260// Invalid: And32 with numOperands = 5
1261INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1262// Invalid: And32 with numOperands = 6
1263INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1264// Invalid: And64 with numOperands = 0
1265
1266// Invalid: And64 with numOperands = 1
1267INVALID_INST_FORM,
1268// And64 U:G:64, UD:G:64
1269ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1270// And64 U:G:64, U:G:64, D:G:64
1271ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1272// Invalid: And64 with numOperands = 4
1273INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1274// Invalid: And64 with numOperands = 5
1275INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1276// Invalid: And64 with numOperands = 6
1277INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1278// Invalid: AndDouble with numOperands = 0
1279
1280// Invalid: AndDouble with numOperands = 1
1281INVALID_INST_FORM,
1282// AndDouble U:F:64, UD:F:64
1283ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1284// AndDouble U:F:64, U:F:64, D:F:64
1285ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1286// Invalid: AndDouble with numOperands = 4
1287INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1288// Invalid: AndDouble with numOperands = 5
1289INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1290// Invalid: AndDouble with numOperands = 6
1291INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1292// Invalid: AndFloat with numOperands = 0
1293
1294// Invalid: AndFloat with numOperands = 1
1295INVALID_INST_FORM,
1296// AndFloat U:F:32, UD:F:32
1297ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1298// AndFloat U:F:32, U:F:32, D:F:32
1299ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1300// Invalid: AndFloat with numOperands = 4
1301INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1302// Invalid: AndFloat with numOperands = 5
1303INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1304// Invalid: AndFloat with numOperands = 6
1305INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1306// Invalid: OrDouble with numOperands = 0
1307
1308// Invalid: OrDouble with numOperands = 1
1309INVALID_INST_FORM,
1310// OrDouble U:F:64, UD:F:64
1311ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1312// OrDouble U:F:64, U:F:64, D:F:64
1313ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1314// Invalid: OrDouble with numOperands = 4
1315INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1316// Invalid: OrDouble with numOperands = 5
1317INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1318// Invalid: OrDouble with numOperands = 6
1319INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1320// Invalid: OrFloat with numOperands = 0
1321
1322// Invalid: OrFloat with numOperands = 1
1323INVALID_INST_FORM,
1324// OrFloat U:F:32, UD:F:32
1325ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1326// OrFloat U:F:32, U:F:32, D:F:32
1327ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1328// Invalid: OrFloat with numOperands = 4
1329INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1330// Invalid: OrFloat with numOperands = 5
1331INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1332// Invalid: OrFloat with numOperands = 6
1333INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1334// Invalid: XorDouble with numOperands = 0
1335
1336// Invalid: XorDouble with numOperands = 1
1337INVALID_INST_FORM,
1338// XorDouble U:F:64, UD:F:64
1339ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::UseDef, FP, Width64),
1340// XorDouble U:F:64, U:F:64, D:F:64
1341ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1342// Invalid: XorDouble with numOperands = 4
1343INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1344// Invalid: XorDouble with numOperands = 5
1345INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1346// Invalid: XorDouble with numOperands = 6
1347INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1348// Invalid: XorFloat with numOperands = 0
1349
1350// Invalid: XorFloat with numOperands = 1
1351INVALID_INST_FORM,
1352// XorFloat U:F:32, UD:F:32
1353ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::UseDef, FP, Width32),
1354// XorFloat U:F:32, U:F:32, D:F:32
1355ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1356// Invalid: XorFloat with numOperands = 4
1357INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1358// Invalid: XorFloat with numOperands = 5
1359INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1360// Invalid: XorFloat with numOperands = 6
1361INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1362// Invalid: Lshift32 with numOperands = 0
1363
1364// Invalid: Lshift32 with numOperands = 1
1365INVALID_INST_FORM,
1366// Lshift32 U:G:32, UZD:G:32
1367ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1368// Lshift32 U:G:32, U:G:32, ZD:G:32
1369ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1370// Invalid: Lshift32 with numOperands = 4
1371INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1372// Invalid: Lshift32 with numOperands = 5
1373INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1374// Invalid: Lshift32 with numOperands = 6
1375INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1376// Invalid: Lshift64 with numOperands = 0
1377
1378// Invalid: Lshift64 with numOperands = 1
1379INVALID_INST_FORM,
1380// Lshift64 U:G:64, UD:G:64
1381ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1382// Lshift64 U:G:64, U:G:64, D:G:64
1383ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1384// Invalid: Lshift64 with numOperands = 4
1385INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1386// Invalid: Lshift64 with numOperands = 5
1387INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1388// Invalid: Lshift64 with numOperands = 6
1389INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1390// Invalid: Rshift32 with numOperands = 0
1391
1392// Invalid: Rshift32 with numOperands = 1
1393INVALID_INST_FORM,
1394// Rshift32 U:G:32, UZD:G:32
1395ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1396// Rshift32 U:G:32, U:G:32, ZD:G:32
1397ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1398// Invalid: Rshift32 with numOperands = 4
1399INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1400// Invalid: Rshift32 with numOperands = 5
1401INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1402// Invalid: Rshift32 with numOperands = 6
1403INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1404// Invalid: Rshift64 with numOperands = 0
1405
1406// Invalid: Rshift64 with numOperands = 1
1407INVALID_INST_FORM,
1408// Rshift64 U:G:64, UD:G:64
1409ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1410// Rshift64 U:G:64, U:G:64, D:G:64
1411ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1412// Invalid: Rshift64 with numOperands = 4
1413INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1414// Invalid: Rshift64 with numOperands = 5
1415INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1416// Invalid: Rshift64 with numOperands = 6
1417INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1418// Invalid: Urshift32 with numOperands = 0
1419
1420// Invalid: Urshift32 with numOperands = 1
1421INVALID_INST_FORM,
1422// Urshift32 U:G:32, UZD:G:32
1423ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1424// Urshift32 U:G:32, U:G:32, ZD:G:32
1425ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1426// Invalid: Urshift32 with numOperands = 4
1427INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1428// Invalid: Urshift32 with numOperands = 5
1429INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1430// Invalid: Urshift32 with numOperands = 6
1431INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1432// Invalid: Urshift64 with numOperands = 0
1433
1434// Invalid: Urshift64 with numOperands = 1
1435INVALID_INST_FORM,
1436// Urshift64 U:G:64, UD:G:64
1437ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1438// Urshift64 U:G:64, U:G:64, D:G:64
1439ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1440// Invalid: Urshift64 with numOperands = 4
1441INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1442// Invalid: Urshift64 with numOperands = 5
1443INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1444// Invalid: Urshift64 with numOperands = 6
1445INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1446// Invalid: RotateRight32 with numOperands = 0
1447
1448// Invalid: RotateRight32 with numOperands = 1
1449INVALID_INST_FORM,
1450// RotateRight32 U:G:32, UZD:G:32
1451ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1452// RotateRight32 U:G:32, U:G:32, ZD:G:32
1453ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1454// Invalid: RotateRight32 with numOperands = 4
1455INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1456// Invalid: RotateRight32 with numOperands = 5
1457INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1458// Invalid: RotateRight32 with numOperands = 6
1459INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1460// Invalid: RotateRight64 with numOperands = 0
1461
1462// Invalid: RotateRight64 with numOperands = 1
1463INVALID_INST_FORM,
1464// RotateRight64 U:G:64, UD:G:64
1465ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1466// RotateRight64 U:G:64, U:G:64, D:G:64
1467ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1468// Invalid: RotateRight64 with numOperands = 4
1469INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1470// Invalid: RotateRight64 with numOperands = 5
1471INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1472// Invalid: RotateRight64 with numOperands = 6
1473INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1474// Invalid: RotateLeft32 with numOperands = 0
1475
1476// Invalid: RotateLeft32 with numOperands = 1
1477INVALID_INST_FORM,
1478// RotateLeft32 U:G:32, UZD:G:32
1479ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1480// Invalid: RotateLeft32 with numOperands = 3
1481INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1482// Invalid: RotateLeft32 with numOperands = 4
1483INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1484// Invalid: RotateLeft32 with numOperands = 5
1485INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1486// Invalid: RotateLeft32 with numOperands = 6
1487INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1488// Invalid: RotateLeft64 with numOperands = 0
1489
1490// Invalid: RotateLeft64 with numOperands = 1
1491INVALID_INST_FORM,
1492// RotateLeft64 U:G:64, UD:G:64
1493ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1494// Invalid: RotateLeft64 with numOperands = 3
1495INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1496// Invalid: RotateLeft64 with numOperands = 4
1497INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1498// Invalid: RotateLeft64 with numOperands = 5
1499INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1500// Invalid: RotateLeft64 with numOperands = 6
1501INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1502// Invalid: Or32 with numOperands = 0
1503
1504// Invalid: Or32 with numOperands = 1
1505INVALID_INST_FORM,
1506// Or32 U:G:32, UZD:G:32
1507ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1508// Or32 U:G:32, U:G:32, ZD:G:32
1509ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1510// Invalid: Or32 with numOperands = 4
1511INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1512// Invalid: Or32 with numOperands = 5
1513INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1514// Invalid: Or32 with numOperands = 6
1515INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1516// Invalid: Or64 with numOperands = 0
1517
1518// Invalid: Or64 with numOperands = 1
1519INVALID_INST_FORM,
1520// Or64 U:G:64, UD:G:64
1521ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1522// Or64 U:G:64, U:G:64, D:G:64
1523ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1524// Invalid: Or64 with numOperands = 4
1525INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1526// Invalid: Or64 with numOperands = 5
1527INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1528// Invalid: Or64 with numOperands = 6
1529INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1530// Invalid: Xor32 with numOperands = 0
1531
1532// Invalid: Xor32 with numOperands = 1
1533INVALID_INST_FORM,
1534// Xor32 U:G:32, UZD:G:32
1535ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1536// Xor32 U:G:32, U:G:32, ZD:G:32
1537ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1538// Invalid: Xor32 with numOperands = 4
1539INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1540// Invalid: Xor32 with numOperands = 5
1541INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1542// Invalid: Xor32 with numOperands = 6
1543INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1544// Invalid: Xor64 with numOperands = 0
1545
1546// Invalid: Xor64 with numOperands = 1
1547INVALID_INST_FORM,
1548// Xor64 U:G:64, UD:G:64
1549ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1550// Xor64 U:G:64, U:G:64, D:G:64
1551ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1552// Invalid: Xor64 with numOperands = 4
1553INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1554// Invalid: Xor64 with numOperands = 5
1555INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1556// Invalid: Xor64 with numOperands = 6
1557INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1558// Invalid: Not32 with numOperands = 0
1559
1560// Not32 UZD:G:32
1561ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
1562// Not32 U:G:32, ZD:G:32
1563ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1564// Invalid: Not32 with numOperands = 3
1565INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1566// Invalid: Not32 with numOperands = 4
1567INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1568// Invalid: Not32 with numOperands = 5
1569INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1570// Invalid: Not32 with numOperands = 6
1571INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1572// Invalid: Not64 with numOperands = 0
1573
1574// Not64 UD:G:64
1575ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1576// Not64 U:G:64, D:G:64
1577ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1578// Invalid: Not64 with numOperands = 3
1579INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1580// Invalid: Not64 with numOperands = 4
1581INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1582// Invalid: Not64 with numOperands = 5
1583INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1584// Invalid: Not64 with numOperands = 6
1585INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1586// Invalid: AbsDouble with numOperands = 0
1587
1588// Invalid: AbsDouble with numOperands = 1
1589INVALID_INST_FORM,
1590// AbsDouble U:F:64, D:F:64
1591ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1592// Invalid: AbsDouble with numOperands = 3
1593INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1594// Invalid: AbsDouble with numOperands = 4
1595INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1596// Invalid: AbsDouble with numOperands = 5
1597INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1598// Invalid: AbsDouble with numOperands = 6
1599INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1600// Invalid: AbsFloat with numOperands = 0
1601
1602// Invalid: AbsFloat with numOperands = 1
1603INVALID_INST_FORM,
1604// AbsFloat U:F:32, D:F:32
1605ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1606// Invalid: AbsFloat with numOperands = 3
1607INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1608// Invalid: AbsFloat with numOperands = 4
1609INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1610// Invalid: AbsFloat with numOperands = 5
1611INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1612// Invalid: AbsFloat with numOperands = 6
1613INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1614// Invalid: CeilDouble with numOperands = 0
1615
1616// Invalid: CeilDouble with numOperands = 1
1617INVALID_INST_FORM,
1618// CeilDouble U:F:64, D:F:64
1619ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1620// Invalid: CeilDouble with numOperands = 3
1621INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1622// Invalid: CeilDouble with numOperands = 4
1623INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1624// Invalid: CeilDouble with numOperands = 5
1625INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1626// Invalid: CeilDouble with numOperands = 6
1627INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1628// Invalid: CeilFloat with numOperands = 0
1629
1630// Invalid: CeilFloat with numOperands = 1
1631INVALID_INST_FORM,
1632// CeilFloat U:F:32, D:F:32
1633ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1634// Invalid: CeilFloat with numOperands = 3
1635INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1636// Invalid: CeilFloat with numOperands = 4
1637INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1638// Invalid: CeilFloat with numOperands = 5
1639INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1640// Invalid: CeilFloat with numOperands = 6
1641INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1642// Invalid: FloorDouble with numOperands = 0
1643
1644// Invalid: FloorDouble with numOperands = 1
1645INVALID_INST_FORM,
1646// FloorDouble U:F:64, D:F:64
1647ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1648// Invalid: FloorDouble with numOperands = 3
1649INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1650// Invalid: FloorDouble with numOperands = 4
1651INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1652// Invalid: FloorDouble with numOperands = 5
1653INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1654// Invalid: FloorDouble with numOperands = 6
1655INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1656// Invalid: FloorFloat with numOperands = 0
1657
1658// Invalid: FloorFloat with numOperands = 1
1659INVALID_INST_FORM,
1660// FloorFloat U:F:32, D:F:32
1661ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1662// Invalid: FloorFloat with numOperands = 3
1663INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1664// Invalid: FloorFloat with numOperands = 4
1665INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1666// Invalid: FloorFloat with numOperands = 5
1667INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1668// Invalid: FloorFloat with numOperands = 6
1669INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1670// Invalid: SqrtDouble with numOperands = 0
1671
1672// Invalid: SqrtDouble with numOperands = 1
1673INVALID_INST_FORM,
1674// SqrtDouble U:F:64, D:F:64
1675ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1676// Invalid: SqrtDouble with numOperands = 3
1677INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1678// Invalid: SqrtDouble with numOperands = 4
1679INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1680// Invalid: SqrtDouble with numOperands = 5
1681INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1682// Invalid: SqrtDouble with numOperands = 6
1683INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1684// Invalid: SqrtFloat with numOperands = 0
1685
1686// Invalid: SqrtFloat with numOperands = 1
1687INVALID_INST_FORM,
1688// SqrtFloat U:F:32, D:F:32
1689ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1690// Invalid: SqrtFloat with numOperands = 3
1691INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1692// Invalid: SqrtFloat with numOperands = 4
1693INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1694// Invalid: SqrtFloat with numOperands = 5
1695INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1696// Invalid: SqrtFloat with numOperands = 6
1697INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1698// Invalid: ConvertInt32ToDouble with numOperands = 0
1699
1700// Invalid: ConvertInt32ToDouble with numOperands = 1
1701INVALID_INST_FORM,
1702// ConvertInt32ToDouble U:G:32, D:F:64
1703ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1704// Invalid: ConvertInt32ToDouble with numOperands = 3
1705INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1706// Invalid: ConvertInt32ToDouble with numOperands = 4
1707INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1708// Invalid: ConvertInt32ToDouble with numOperands = 5
1709INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1710// Invalid: ConvertInt32ToDouble with numOperands = 6
1711INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1712// Invalid: ConvertInt64ToDouble with numOperands = 0
1713
1714// Invalid: ConvertInt64ToDouble with numOperands = 1
1715INVALID_INST_FORM,
1716// ConvertInt64ToDouble U:G:64, D:F:64
1717ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1718// Invalid: ConvertInt64ToDouble with numOperands = 3
1719INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1720// Invalid: ConvertInt64ToDouble with numOperands = 4
1721INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1722// Invalid: ConvertInt64ToDouble with numOperands = 5
1723INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1724// Invalid: ConvertInt64ToDouble with numOperands = 6
1725INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1726// Invalid: ConvertInt32ToFloat with numOperands = 0
1727
1728// Invalid: ConvertInt32ToFloat with numOperands = 1
1729INVALID_INST_FORM,
1730// ConvertInt32ToFloat U:G:32, D:F:32
1731ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1732// Invalid: ConvertInt32ToFloat with numOperands = 3
1733INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1734// Invalid: ConvertInt32ToFloat with numOperands = 4
1735INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1736// Invalid: ConvertInt32ToFloat with numOperands = 5
1737INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1738// Invalid: ConvertInt32ToFloat with numOperands = 6
1739INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1740// Invalid: ConvertInt64ToFloat with numOperands = 0
1741
1742// Invalid: ConvertInt64ToFloat with numOperands = 1
1743INVALID_INST_FORM,
1744// ConvertInt64ToFloat U:G:64, D:F:32
1745ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1746// Invalid: ConvertInt64ToFloat with numOperands = 3
1747INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1748// Invalid: ConvertInt64ToFloat with numOperands = 4
1749INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1750// Invalid: ConvertInt64ToFloat with numOperands = 5
1751INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1752// Invalid: ConvertInt64ToFloat with numOperands = 6
1753INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1754// Invalid: CountLeadingZeros32 with numOperands = 0
1755
1756// Invalid: CountLeadingZeros32 with numOperands = 1
1757INVALID_INST_FORM,
1758// CountLeadingZeros32 U:G:32, ZD:G:32
1759ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1760// Invalid: CountLeadingZeros32 with numOperands = 3
1761INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1762// Invalid: CountLeadingZeros32 with numOperands = 4
1763INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1764// Invalid: CountLeadingZeros32 with numOperands = 5
1765INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1766// Invalid: CountLeadingZeros32 with numOperands = 6
1767INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1768// Invalid: CountLeadingZeros64 with numOperands = 0
1769
1770// Invalid: CountLeadingZeros64 with numOperands = 1
1771INVALID_INST_FORM,
1772// CountLeadingZeros64 U:G:64, D:G:64
1773ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
1774// Invalid: CountLeadingZeros64 with numOperands = 3
1775INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1776// Invalid: CountLeadingZeros64 with numOperands = 4
1777INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1778// Invalid: CountLeadingZeros64 with numOperands = 5
1779INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1780// Invalid: CountLeadingZeros64 with numOperands = 6
1781INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1782// Invalid: ConvertDoubleToFloat with numOperands = 0
1783
1784// Invalid: ConvertDoubleToFloat with numOperands = 1
1785INVALID_INST_FORM,
1786// ConvertDoubleToFloat U:F:64, D:F:32
1787ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1788// Invalid: ConvertDoubleToFloat with numOperands = 3
1789INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1790// Invalid: ConvertDoubleToFloat with numOperands = 4
1791INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1792// Invalid: ConvertDoubleToFloat with numOperands = 5
1793INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1794// Invalid: ConvertDoubleToFloat with numOperands = 6
1795INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1796// Invalid: ConvertFloatToDouble with numOperands = 0
1797
1798// Invalid: ConvertFloatToDouble with numOperands = 1
1799INVALID_INST_FORM,
1800// ConvertFloatToDouble U:F:32, D:F:64
1801ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1802// Invalid: ConvertFloatToDouble with numOperands = 3
1803INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1804// Invalid: ConvertFloatToDouble with numOperands = 4
1805INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1806// Invalid: ConvertFloatToDouble with numOperands = 5
1807INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1808// Invalid: ConvertFloatToDouble with numOperands = 6
1809INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1810// Invalid: Move with numOperands = 0
1811
1812// Invalid: Move with numOperands = 1
1813INVALID_INST_FORM,
1814// Move U:G:Ptr, D:G:Ptr
1815ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
1816// Move U:G:Ptr, D:G:Ptr, S:G:Ptr
1817ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Scratch, GP, POINTER_WIDTH),
1818// Invalid: Move with numOperands = 4
1819INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1820// Invalid: Move with numOperands = 5
1821INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1822// Invalid: Move with numOperands = 6
1823INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1824// Invalid: Swap32 with numOperands = 0
1825
1826// Invalid: Swap32 with numOperands = 1
1827INVALID_INST_FORM,
1828// Swap32 UD:G:32, UD:G:32
1829ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
1830// Invalid: Swap32 with numOperands = 3
1831INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1832// Invalid: Swap32 with numOperands = 4
1833INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1834// Invalid: Swap32 with numOperands = 5
1835INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1836// Invalid: Swap32 with numOperands = 6
1837INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1838// Invalid: Swap64 with numOperands = 0
1839
1840// Invalid: Swap64 with numOperands = 1
1841INVALID_INST_FORM,
1842// Swap64 UD:G:64, UD:G:64
1843ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
1844// Invalid: Swap64 with numOperands = 3
1845INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1846// Invalid: Swap64 with numOperands = 4
1847INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1848// Invalid: Swap64 with numOperands = 5
1849INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1850// Invalid: Swap64 with numOperands = 6
1851INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1852// Invalid: Move32 with numOperands = 0
1853
1854// Invalid: Move32 with numOperands = 1
1855INVALID_INST_FORM,
1856// Move32 U:G:32, ZD:G:32
1857ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1858// Move32 U:G:32, ZD:G:32, S:G:32
1859ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32), ENCODE_INST_FORM(Arg::Scratch, GP, Width32),
1860// Invalid: Move32 with numOperands = 4
1861INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1862// Invalid: Move32 with numOperands = 5
1863INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1864// Invalid: Move32 with numOperands = 6
1865INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1866// Invalid: StoreZero32 with numOperands = 0
1867
1868// StoreZero32 D:G:32
1869ENCODE_INST_FORM(Arg::Def, GP, Width32),
1870// Invalid: StoreZero32 with numOperands = 2
1871INVALID_INST_FORM, INVALID_INST_FORM,
1872// Invalid: StoreZero32 with numOperands = 3
1873INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1874// Invalid: StoreZero32 with numOperands = 4
1875INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1876// Invalid: StoreZero32 with numOperands = 5
1877INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1878// Invalid: StoreZero32 with numOperands = 6
1879INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1880// Invalid: StoreZero64 with numOperands = 0
1881
1882// StoreZero64 D:G:64
1883ENCODE_INST_FORM(Arg::Def, GP, Width64),
1884// Invalid: StoreZero64 with numOperands = 2
1885INVALID_INST_FORM, INVALID_INST_FORM,
1886// Invalid: StoreZero64 with numOperands = 3
1887INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1888// Invalid: StoreZero64 with numOperands = 4
1889INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1890// Invalid: StoreZero64 with numOperands = 5
1891INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1892// Invalid: StoreZero64 with numOperands = 6
1893INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1894// Invalid: SignExtend32ToPtr with numOperands = 0
1895
1896// Invalid: SignExtend32ToPtr with numOperands = 1
1897INVALID_INST_FORM,
1898// SignExtend32ToPtr U:G:32, D:G:Ptr
1899ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
1900// Invalid: SignExtend32ToPtr with numOperands = 3
1901INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1902// Invalid: SignExtend32ToPtr with numOperands = 4
1903INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1904// Invalid: SignExtend32ToPtr with numOperands = 5
1905INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1906// Invalid: SignExtend32ToPtr with numOperands = 6
1907INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1908// Invalid: ZeroExtend8To32 with numOperands = 0
1909
1910// Invalid: ZeroExtend8To32 with numOperands = 1
1911INVALID_INST_FORM,
1912// ZeroExtend8To32 U:G:8, ZD:G:32
1913ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1914// Invalid: ZeroExtend8To32 with numOperands = 3
1915INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1916// Invalid: ZeroExtend8To32 with numOperands = 4
1917INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1918// Invalid: ZeroExtend8To32 with numOperands = 5
1919INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1920// Invalid: ZeroExtend8To32 with numOperands = 6
1921INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1922// Invalid: SignExtend8To32 with numOperands = 0
1923
1924// Invalid: SignExtend8To32 with numOperands = 1
1925INVALID_INST_FORM,
1926// SignExtend8To32 U:G:8, ZD:G:32
1927ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1928// Invalid: SignExtend8To32 with numOperands = 3
1929INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1930// Invalid: SignExtend8To32 with numOperands = 4
1931INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1932// Invalid: SignExtend8To32 with numOperands = 5
1933INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1934// Invalid: SignExtend8To32 with numOperands = 6
1935INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1936// Invalid: ZeroExtend16To32 with numOperands = 0
1937
1938// Invalid: ZeroExtend16To32 with numOperands = 1
1939INVALID_INST_FORM,
1940// ZeroExtend16To32 U:G:16, ZD:G:32
1941ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1942// Invalid: ZeroExtend16To32 with numOperands = 3
1943INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1944// Invalid: ZeroExtend16To32 with numOperands = 4
1945INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1946// Invalid: ZeroExtend16To32 with numOperands = 5
1947INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1948// Invalid: ZeroExtend16To32 with numOperands = 6
1949INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1950// Invalid: SignExtend16To32 with numOperands = 0
1951
1952// Invalid: SignExtend16To32 with numOperands = 1
1953INVALID_INST_FORM,
1954// SignExtend16To32 U:G:16, ZD:G:32
1955ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
1956// Invalid: SignExtend16To32 with numOperands = 3
1957INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1958// Invalid: SignExtend16To32 with numOperands = 4
1959INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1960// Invalid: SignExtend16To32 with numOperands = 5
1961INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1962// Invalid: SignExtend16To32 with numOperands = 6
1963INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1964// Invalid: MoveFloat with numOperands = 0
1965
1966// Invalid: MoveFloat with numOperands = 1
1967INVALID_INST_FORM,
1968// MoveFloat U:F:32, D:F:32
1969ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
1970// MoveFloat U:F:32, D:F:32, S:F:32
1971ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32), ENCODE_INST_FORM(Arg::Scratch, FP, Width32),
1972// Invalid: MoveFloat with numOperands = 4
1973INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1974// Invalid: MoveFloat with numOperands = 5
1975INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1976// Invalid: MoveFloat with numOperands = 6
1977INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1978// Invalid: MoveDouble with numOperands = 0
1979
1980// Invalid: MoveDouble with numOperands = 1
1981INVALID_INST_FORM,
1982// MoveDouble U:F:64, D:F:64
1983ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
1984// MoveDouble U:F:64, D:F:64, S:F:64
1985ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64), ENCODE_INST_FORM(Arg::Scratch, FP, Width64),
1986// Invalid: MoveDouble with numOperands = 4
1987INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1988// Invalid: MoveDouble with numOperands = 5
1989INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1990// Invalid: MoveDouble with numOperands = 6
1991INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
1992// Invalid: MoveZeroToDouble with numOperands = 0
1993
1994// MoveZeroToDouble D:F:64
1995ENCODE_INST_FORM(Arg::Def, FP, Width64),
1996// Invalid: MoveZeroToDouble with numOperands = 2
1997INVALID_INST_FORM, INVALID_INST_FORM,
1998// Invalid: MoveZeroToDouble with numOperands = 3
1999INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2000// Invalid: MoveZeroToDouble with numOperands = 4
2001INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2002// Invalid: MoveZeroToDouble with numOperands = 5
2003INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2004// Invalid: MoveZeroToDouble with numOperands = 6
2005INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2006// Invalid: Move64ToDouble with numOperands = 0
2007
2008// Invalid: Move64ToDouble with numOperands = 1
2009INVALID_INST_FORM,
2010// Move64ToDouble U:G:64, D:F:64
2011ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
2012// Invalid: Move64ToDouble with numOperands = 3
2013INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2014// Invalid: Move64ToDouble with numOperands = 4
2015INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2016// Invalid: Move64ToDouble with numOperands = 5
2017INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2018// Invalid: Move64ToDouble with numOperands = 6
2019INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2020// Invalid: Move32ToFloat with numOperands = 0
2021
2022// Invalid: Move32ToFloat with numOperands = 1
2023INVALID_INST_FORM,
2024// Move32ToFloat U:G:32, D:F:32
2025ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, FP, Width32),
2026// Invalid: Move32ToFloat with numOperands = 3
2027INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2028// Invalid: Move32ToFloat with numOperands = 4
2029INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2030// Invalid: Move32ToFloat with numOperands = 5
2031INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2032// Invalid: Move32ToFloat with numOperands = 6
2033INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2034// Invalid: MoveDoubleTo64 with numOperands = 0
2035
2036// Invalid: MoveDoubleTo64 with numOperands = 1
2037INVALID_INST_FORM,
2038// MoveDoubleTo64 U:F:64, D:G:64
2039ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64),
2040// Invalid: MoveDoubleTo64 with numOperands = 3
2041INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2042// Invalid: MoveDoubleTo64 with numOperands = 4
2043INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2044// Invalid: MoveDoubleTo64 with numOperands = 5
2045INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2046// Invalid: MoveDoubleTo64 with numOperands = 6
2047INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2048// Invalid: MoveFloatTo32 with numOperands = 0
2049
2050// Invalid: MoveFloatTo32 with numOperands = 1
2051INVALID_INST_FORM,
2052// MoveFloatTo32 U:F:32, D:G:32
2053ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32),
2054// Invalid: MoveFloatTo32 with numOperands = 3
2055INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2056// Invalid: MoveFloatTo32 with numOperands = 4
2057INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2058// Invalid: MoveFloatTo32 with numOperands = 5
2059INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2060// Invalid: MoveFloatTo32 with numOperands = 6
2061INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2062// Invalid: Load8 with numOperands = 0
2063
2064// Invalid: Load8 with numOperands = 1
2065INVALID_INST_FORM,
2066// Load8 U:G:8, ZD:G:32
2067ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2068// Invalid: Load8 with numOperands = 3
2069INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2070// Invalid: Load8 with numOperands = 4
2071INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2072// Invalid: Load8 with numOperands = 5
2073INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2074// Invalid: Load8 with numOperands = 6
2075INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2076// Invalid: LoadAcq8 with numOperands = 0
2077
2078// Invalid: LoadAcq8 with numOperands = 1
2079INVALID_INST_FORM,
2080// LoadAcq8 U:G:8, ZD:G:32
2081ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2082// Invalid: LoadAcq8 with numOperands = 3
2083INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2084// Invalid: LoadAcq8 with numOperands = 4
2085INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2086// Invalid: LoadAcq8 with numOperands = 5
2087INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2088// Invalid: LoadAcq8 with numOperands = 6
2089INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2090// Invalid: Store8 with numOperands = 0
2091
2092// Invalid: Store8 with numOperands = 1
2093INVALID_INST_FORM,
2094// Store8 U:G:8, D:G:8
2095ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8),
2096// Invalid: Store8 with numOperands = 3
2097INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2098// Invalid: Store8 with numOperands = 4
2099INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2100// Invalid: Store8 with numOperands = 5
2101INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2102// Invalid: Store8 with numOperands = 6
2103INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2104// Invalid: StoreRel8 with numOperands = 0
2105
2106// Invalid: StoreRel8 with numOperands = 1
2107INVALID_INST_FORM,
2108// StoreRel8 U:G:8, D:G:8
2109ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8),
2110// Invalid: StoreRel8 with numOperands = 3
2111INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2112// Invalid: StoreRel8 with numOperands = 4
2113INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2114// Invalid: StoreRel8 with numOperands = 5
2115INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2116// Invalid: StoreRel8 with numOperands = 6
2117INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2118// Invalid: Load8SignedExtendTo32 with numOperands = 0
2119
2120// Invalid: Load8SignedExtendTo32 with numOperands = 1
2121INVALID_INST_FORM,
2122// Load8SignedExtendTo32 U:G:8, ZD:G:32
2123ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2124// Invalid: Load8SignedExtendTo32 with numOperands = 3
2125INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2126// Invalid: Load8SignedExtendTo32 with numOperands = 4
2127INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2128// Invalid: Load8SignedExtendTo32 with numOperands = 5
2129INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2130// Invalid: Load8SignedExtendTo32 with numOperands = 6
2131INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2132// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 0
2133
2134// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 1
2135INVALID_INST_FORM,
2136// LoadAcq8SignedExtendTo32 U:G:8, ZD:G:32
2137ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2138// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 3
2139INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2140// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 4
2141INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2142// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 5
2143INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2144// Invalid: LoadAcq8SignedExtendTo32 with numOperands = 6
2145INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2146// Invalid: Load16 with numOperands = 0
2147
2148// Invalid: Load16 with numOperands = 1
2149INVALID_INST_FORM,
2150// Load16 U:G:16, ZD:G:32
2151ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2152// Invalid: Load16 with numOperands = 3
2153INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2154// Invalid: Load16 with numOperands = 4
2155INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2156// Invalid: Load16 with numOperands = 5
2157INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2158// Invalid: Load16 with numOperands = 6
2159INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2160// Invalid: LoadAcq16 with numOperands = 0
2161
2162// Invalid: LoadAcq16 with numOperands = 1
2163INVALID_INST_FORM,
2164// LoadAcq16 U:G:16, ZD:G:32
2165ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2166// Invalid: LoadAcq16 with numOperands = 3
2167INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2168// Invalid: LoadAcq16 with numOperands = 4
2169INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2170// Invalid: LoadAcq16 with numOperands = 5
2171INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2172// Invalid: LoadAcq16 with numOperands = 6
2173INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2174// Invalid: Load16SignedExtendTo32 with numOperands = 0
2175
2176// Invalid: Load16SignedExtendTo32 with numOperands = 1
2177INVALID_INST_FORM,
2178// Load16SignedExtendTo32 U:G:16, ZD:G:32
2179ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2180// Invalid: Load16SignedExtendTo32 with numOperands = 3
2181INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2182// Invalid: Load16SignedExtendTo32 with numOperands = 4
2183INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2184// Invalid: Load16SignedExtendTo32 with numOperands = 5
2185INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2186// Invalid: Load16SignedExtendTo32 with numOperands = 6
2187INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2188// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 0
2189
2190// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 1
2191INVALID_INST_FORM,
2192// LoadAcq16SignedExtendTo32 U:G:16, ZD:G:32
2193ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2194// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 3
2195INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2196// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 4
2197INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2198// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 5
2199INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2200// Invalid: LoadAcq16SignedExtendTo32 with numOperands = 6
2201INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2202// Invalid: Store16 with numOperands = 0
2203
2204// Invalid: Store16 with numOperands = 1
2205INVALID_INST_FORM,
2206// Store16 U:G:16, D:G:16
2207ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16),
2208// Invalid: Store16 with numOperands = 3
2209INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2210// Invalid: Store16 with numOperands = 4
2211INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2212// Invalid: Store16 with numOperands = 5
2213INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2214// Invalid: Store16 with numOperands = 6
2215INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2216// Invalid: StoreRel16 with numOperands = 0
2217
2218// Invalid: StoreRel16 with numOperands = 1
2219INVALID_INST_FORM,
2220// StoreRel16 U:G:16, D:G:16
2221ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16),
2222// Invalid: StoreRel16 with numOperands = 3
2223INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2224// Invalid: StoreRel16 with numOperands = 4
2225INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2226// Invalid: StoreRel16 with numOperands = 5
2227INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2228// Invalid: StoreRel16 with numOperands = 6
2229INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2230// Invalid: LoadAcq32 with numOperands = 0
2231
2232// Invalid: LoadAcq32 with numOperands = 1
2233INVALID_INST_FORM,
2234// LoadAcq32 U:G:32, ZD:G:32
2235ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2236// Invalid: LoadAcq32 with numOperands = 3
2237INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2238// Invalid: LoadAcq32 with numOperands = 4
2239INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2240// Invalid: LoadAcq32 with numOperands = 5
2241INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2242// Invalid: LoadAcq32 with numOperands = 6
2243INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2244// Invalid: StoreRel32 with numOperands = 0
2245
2246// Invalid: StoreRel32 with numOperands = 1
2247INVALID_INST_FORM,
2248// StoreRel32 U:G:32, ZD:G:32
2249ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
2250// Invalid: StoreRel32 with numOperands = 3
2251INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2252// Invalid: StoreRel32 with numOperands = 4
2253INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2254// Invalid: StoreRel32 with numOperands = 5
2255INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2256// Invalid: StoreRel32 with numOperands = 6
2257INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2258// Invalid: LoadAcq64 with numOperands = 0
2259
2260// Invalid: LoadAcq64 with numOperands = 1
2261INVALID_INST_FORM,
2262// LoadAcq64 U:G:64, ZD:G:64
2263ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
2264// Invalid: LoadAcq64 with numOperands = 3
2265INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2266// Invalid: LoadAcq64 with numOperands = 4
2267INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2268// Invalid: LoadAcq64 with numOperands = 5
2269INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2270// Invalid: LoadAcq64 with numOperands = 6
2271INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2272// Invalid: StoreRel64 with numOperands = 0
2273
2274// Invalid: StoreRel64 with numOperands = 1
2275INVALID_INST_FORM,
2276// StoreRel64 U:G:64, ZD:G:64
2277ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
2278// Invalid: StoreRel64 with numOperands = 3
2279INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2280// Invalid: StoreRel64 with numOperands = 4
2281INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2282// Invalid: StoreRel64 with numOperands = 5
2283INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2284// Invalid: StoreRel64 with numOperands = 6
2285INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2286// Invalid: Xchg8 with numOperands = 0
2287
2288// Invalid: Xchg8 with numOperands = 1
2289INVALID_INST_FORM,
2290// Xchg8 UD:G:8, UD:G:8
2291ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2292// Invalid: Xchg8 with numOperands = 3
2293INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2294// Invalid: Xchg8 with numOperands = 4
2295INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2296// Invalid: Xchg8 with numOperands = 5
2297INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2298// Invalid: Xchg8 with numOperands = 6
2299INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2300// Invalid: Xchg16 with numOperands = 0
2301
2302// Invalid: Xchg16 with numOperands = 1
2303INVALID_INST_FORM,
2304// Xchg16 UD:G:16, UD:G:16
2305ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2306// Invalid: Xchg16 with numOperands = 3
2307INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2308// Invalid: Xchg16 with numOperands = 4
2309INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2310// Invalid: Xchg16 with numOperands = 5
2311INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2312// Invalid: Xchg16 with numOperands = 6
2313INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2314// Invalid: Xchg32 with numOperands = 0
2315
2316// Invalid: Xchg32 with numOperands = 1
2317INVALID_INST_FORM,
2318// Xchg32 UD:G:32, UD:G:32
2319ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2320// Invalid: Xchg32 with numOperands = 3
2321INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2322// Invalid: Xchg32 with numOperands = 4
2323INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2324// Invalid: Xchg32 with numOperands = 5
2325INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2326// Invalid: Xchg32 with numOperands = 6
2327INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2328// Invalid: Xchg64 with numOperands = 0
2329
2330// Invalid: Xchg64 with numOperands = 1
2331INVALID_INST_FORM,
2332// Xchg64 UD:G:64, UD:G:64
2333ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2334// Invalid: Xchg64 with numOperands = 3
2335INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2336// Invalid: Xchg64 with numOperands = 4
2337INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2338// Invalid: Xchg64 with numOperands = 5
2339INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2340// Invalid: Xchg64 with numOperands = 6
2341INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2342// Invalid: AtomicStrongCAS8 with numOperands = 0
2343
2344// Invalid: AtomicStrongCAS8 with numOperands = 1
2345INVALID_INST_FORM,
2346// Invalid: AtomicStrongCAS8 with numOperands = 2
2347INVALID_INST_FORM, INVALID_INST_FORM,
2348// AtomicStrongCAS8 UD:G:8, U:G:8, UD:G:8
2349ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2350// Invalid: AtomicStrongCAS8 with numOperands = 4
2351INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2352// AtomicStrongCAS8 U:G:32, UD:G:8, U:G:8, UD:G:8, ZD:G:8
2353ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2354// Invalid: AtomicStrongCAS8 with numOperands = 6
2355INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2356// Invalid: AtomicStrongCAS16 with numOperands = 0
2357
2358// Invalid: AtomicStrongCAS16 with numOperands = 1
2359INVALID_INST_FORM,
2360// Invalid: AtomicStrongCAS16 with numOperands = 2
2361INVALID_INST_FORM, INVALID_INST_FORM,
2362// AtomicStrongCAS16 UD:G:16, U:G:32, UD:G:16
2363ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2364// Invalid: AtomicStrongCAS16 with numOperands = 4
2365INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2366// AtomicStrongCAS16 U:G:32, UD:G:16, U:G:32, UD:G:16, ZD:G:8
2367ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2368// Invalid: AtomicStrongCAS16 with numOperands = 6
2369INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2370// Invalid: AtomicStrongCAS32 with numOperands = 0
2371
2372// Invalid: AtomicStrongCAS32 with numOperands = 1
2373INVALID_INST_FORM,
2374// Invalid: AtomicStrongCAS32 with numOperands = 2
2375INVALID_INST_FORM, INVALID_INST_FORM,
2376// AtomicStrongCAS32 UD:G:32, U:G:32, UD:G:32
2377ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2378// Invalid: AtomicStrongCAS32 with numOperands = 4
2379INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2380// AtomicStrongCAS32 U:G:32, UD:G:32, U:G:32, UD:G:32, ZD:G:8
2381ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2382// Invalid: AtomicStrongCAS32 with numOperands = 6
2383INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2384// Invalid: AtomicStrongCAS64 with numOperands = 0
2385
2386// Invalid: AtomicStrongCAS64 with numOperands = 1
2387INVALID_INST_FORM,
2388// Invalid: AtomicStrongCAS64 with numOperands = 2
2389INVALID_INST_FORM, INVALID_INST_FORM,
2390// AtomicStrongCAS64 UD:G:64, U:G:64, UD:G:64
2391ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2392// Invalid: AtomicStrongCAS64 with numOperands = 4
2393INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2394// AtomicStrongCAS64 U:G:32, UD:G:64, U:G:64, UD:G:64, ZD:G:8
2395ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2396// Invalid: AtomicStrongCAS64 with numOperands = 6
2397INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2398// Invalid: BranchAtomicStrongCAS8 with numOperands = 0
2399
2400// Invalid: BranchAtomicStrongCAS8 with numOperands = 1
2401INVALID_INST_FORM,
2402// Invalid: BranchAtomicStrongCAS8 with numOperands = 2
2403INVALID_INST_FORM, INVALID_INST_FORM,
2404// Invalid: BranchAtomicStrongCAS8 with numOperands = 3
2405INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2406// BranchAtomicStrongCAS8 U:G:32, UD:G:8, U:G:8, UD:G:8
2407ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2408// Invalid: BranchAtomicStrongCAS8 with numOperands = 5
2409INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2410// Invalid: BranchAtomicStrongCAS8 with numOperands = 6
2411INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2412// Invalid: BranchAtomicStrongCAS16 with numOperands = 0
2413
2414// Invalid: BranchAtomicStrongCAS16 with numOperands = 1
2415INVALID_INST_FORM,
2416// Invalid: BranchAtomicStrongCAS16 with numOperands = 2
2417INVALID_INST_FORM, INVALID_INST_FORM,
2418// Invalid: BranchAtomicStrongCAS16 with numOperands = 3
2419INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2420// BranchAtomicStrongCAS16 U:G:32, UD:G:16, U:G:32, UD:G:16
2421ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2422// Invalid: BranchAtomicStrongCAS16 with numOperands = 5
2423INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2424// Invalid: BranchAtomicStrongCAS16 with numOperands = 6
2425INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2426// Invalid: BranchAtomicStrongCAS32 with numOperands = 0
2427
2428// Invalid: BranchAtomicStrongCAS32 with numOperands = 1
2429INVALID_INST_FORM,
2430// Invalid: BranchAtomicStrongCAS32 with numOperands = 2
2431INVALID_INST_FORM, INVALID_INST_FORM,
2432// Invalid: BranchAtomicStrongCAS32 with numOperands = 3
2433INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2434// BranchAtomicStrongCAS32 U:G:32, UD:G:32, U:G:32, UD:G:32
2435ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2436// Invalid: BranchAtomicStrongCAS32 with numOperands = 5
2437INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2438// Invalid: BranchAtomicStrongCAS32 with numOperands = 6
2439INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2440// Invalid: BranchAtomicStrongCAS64 with numOperands = 0
2441
2442// Invalid: BranchAtomicStrongCAS64 with numOperands = 1
2443INVALID_INST_FORM,
2444// Invalid: BranchAtomicStrongCAS64 with numOperands = 2
2445INVALID_INST_FORM, INVALID_INST_FORM,
2446// Invalid: BranchAtomicStrongCAS64 with numOperands = 3
2447INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2448// BranchAtomicStrongCAS64 U:G:32, UD:G:64, U:G:64, UD:G:64
2449ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2450// Invalid: BranchAtomicStrongCAS64 with numOperands = 5
2451INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2452// Invalid: BranchAtomicStrongCAS64 with numOperands = 6
2453INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2454// Invalid: AtomicAdd8 with numOperands = 0
2455
2456// Invalid: AtomicAdd8 with numOperands = 1
2457INVALID_INST_FORM,
2458// AtomicAdd8 U:G:8, UD:G:8
2459ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2460// Invalid: AtomicAdd8 with numOperands = 3
2461INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2462// Invalid: AtomicAdd8 with numOperands = 4
2463INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2464// Invalid: AtomicAdd8 with numOperands = 5
2465INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2466// Invalid: AtomicAdd8 with numOperands = 6
2467INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2468// Invalid: AtomicAdd16 with numOperands = 0
2469
2470// Invalid: AtomicAdd16 with numOperands = 1
2471INVALID_INST_FORM,
2472// AtomicAdd16 U:G:16, UD:G:16
2473ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2474// Invalid: AtomicAdd16 with numOperands = 3
2475INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2476// Invalid: AtomicAdd16 with numOperands = 4
2477INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2478// Invalid: AtomicAdd16 with numOperands = 5
2479INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2480// Invalid: AtomicAdd16 with numOperands = 6
2481INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2482// Invalid: AtomicAdd32 with numOperands = 0
2483
2484// Invalid: AtomicAdd32 with numOperands = 1
2485INVALID_INST_FORM,
2486// AtomicAdd32 U:G:32, UD:G:32
2487ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2488// Invalid: AtomicAdd32 with numOperands = 3
2489INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2490// Invalid: AtomicAdd32 with numOperands = 4
2491INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2492// Invalid: AtomicAdd32 with numOperands = 5
2493INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2494// Invalid: AtomicAdd32 with numOperands = 6
2495INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2496// Invalid: AtomicAdd64 with numOperands = 0
2497
2498// Invalid: AtomicAdd64 with numOperands = 1
2499INVALID_INST_FORM,
2500// AtomicAdd64 U:G:64, UD:G:64
2501ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2502// Invalid: AtomicAdd64 with numOperands = 3
2503INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2504// Invalid: AtomicAdd64 with numOperands = 4
2505INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2506// Invalid: AtomicAdd64 with numOperands = 5
2507INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2508// Invalid: AtomicAdd64 with numOperands = 6
2509INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2510// Invalid: AtomicSub8 with numOperands = 0
2511
2512// Invalid: AtomicSub8 with numOperands = 1
2513INVALID_INST_FORM,
2514// AtomicSub8 U:G:8, UD:G:8
2515ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2516// Invalid: AtomicSub8 with numOperands = 3
2517INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2518// Invalid: AtomicSub8 with numOperands = 4
2519INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2520// Invalid: AtomicSub8 with numOperands = 5
2521INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2522// Invalid: AtomicSub8 with numOperands = 6
2523INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2524// Invalid: AtomicSub16 with numOperands = 0
2525
2526// Invalid: AtomicSub16 with numOperands = 1
2527INVALID_INST_FORM,
2528// AtomicSub16 U:G:16, UD:G:16
2529ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2530// Invalid: AtomicSub16 with numOperands = 3
2531INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2532// Invalid: AtomicSub16 with numOperands = 4
2533INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2534// Invalid: AtomicSub16 with numOperands = 5
2535INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2536// Invalid: AtomicSub16 with numOperands = 6
2537INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2538// Invalid: AtomicSub32 with numOperands = 0
2539
2540// Invalid: AtomicSub32 with numOperands = 1
2541INVALID_INST_FORM,
2542// AtomicSub32 U:G:32, UD:G:32
2543ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2544// Invalid: AtomicSub32 with numOperands = 3
2545INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2546// Invalid: AtomicSub32 with numOperands = 4
2547INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2548// Invalid: AtomicSub32 with numOperands = 5
2549INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2550// Invalid: AtomicSub32 with numOperands = 6
2551INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2552// Invalid: AtomicSub64 with numOperands = 0
2553
2554// Invalid: AtomicSub64 with numOperands = 1
2555INVALID_INST_FORM,
2556// AtomicSub64 U:G:64, UD:G:64
2557ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2558// Invalid: AtomicSub64 with numOperands = 3
2559INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2560// Invalid: AtomicSub64 with numOperands = 4
2561INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2562// Invalid: AtomicSub64 with numOperands = 5
2563INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2564// Invalid: AtomicSub64 with numOperands = 6
2565INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2566// Invalid: AtomicAnd8 with numOperands = 0
2567
2568// Invalid: AtomicAnd8 with numOperands = 1
2569INVALID_INST_FORM,
2570// AtomicAnd8 U:G:8, UD:G:8
2571ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2572// Invalid: AtomicAnd8 with numOperands = 3
2573INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2574// Invalid: AtomicAnd8 with numOperands = 4
2575INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2576// Invalid: AtomicAnd8 with numOperands = 5
2577INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2578// Invalid: AtomicAnd8 with numOperands = 6
2579INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2580// Invalid: AtomicAnd16 with numOperands = 0
2581
2582// Invalid: AtomicAnd16 with numOperands = 1
2583INVALID_INST_FORM,
2584// AtomicAnd16 U:G:16, UD:G:16
2585ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2586// Invalid: AtomicAnd16 with numOperands = 3
2587INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2588// Invalid: AtomicAnd16 with numOperands = 4
2589INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2590// Invalid: AtomicAnd16 with numOperands = 5
2591INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2592// Invalid: AtomicAnd16 with numOperands = 6
2593INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2594// Invalid: AtomicAnd32 with numOperands = 0
2595
2596// Invalid: AtomicAnd32 with numOperands = 1
2597INVALID_INST_FORM,
2598// AtomicAnd32 U:G:32, UD:G:32
2599ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2600// Invalid: AtomicAnd32 with numOperands = 3
2601INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2602// Invalid: AtomicAnd32 with numOperands = 4
2603INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2604// Invalid: AtomicAnd32 with numOperands = 5
2605INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2606// Invalid: AtomicAnd32 with numOperands = 6
2607INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2608// Invalid: AtomicAnd64 with numOperands = 0
2609
2610// Invalid: AtomicAnd64 with numOperands = 1
2611INVALID_INST_FORM,
2612// AtomicAnd64 U:G:64, UD:G:64
2613ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2614// Invalid: AtomicAnd64 with numOperands = 3
2615INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2616// Invalid: AtomicAnd64 with numOperands = 4
2617INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2618// Invalid: AtomicAnd64 with numOperands = 5
2619INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2620// Invalid: AtomicAnd64 with numOperands = 6
2621INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2622// Invalid: AtomicOr8 with numOperands = 0
2623
2624// Invalid: AtomicOr8 with numOperands = 1
2625INVALID_INST_FORM,
2626// AtomicOr8 U:G:8, UD:G:8
2627ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2628// Invalid: AtomicOr8 with numOperands = 3
2629INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2630// Invalid: AtomicOr8 with numOperands = 4
2631INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2632// Invalid: AtomicOr8 with numOperands = 5
2633INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2634// Invalid: AtomicOr8 with numOperands = 6
2635INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2636// Invalid: AtomicOr16 with numOperands = 0
2637
2638// Invalid: AtomicOr16 with numOperands = 1
2639INVALID_INST_FORM,
2640// AtomicOr16 U:G:16, UD:G:16
2641ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2642// Invalid: AtomicOr16 with numOperands = 3
2643INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2644// Invalid: AtomicOr16 with numOperands = 4
2645INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2646// Invalid: AtomicOr16 with numOperands = 5
2647INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2648// Invalid: AtomicOr16 with numOperands = 6
2649INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2650// Invalid: AtomicOr32 with numOperands = 0
2651
2652// Invalid: AtomicOr32 with numOperands = 1
2653INVALID_INST_FORM,
2654// AtomicOr32 U:G:32, UD:G:32
2655ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2656// Invalid: AtomicOr32 with numOperands = 3
2657INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2658// Invalid: AtomicOr32 with numOperands = 4
2659INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2660// Invalid: AtomicOr32 with numOperands = 5
2661INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2662// Invalid: AtomicOr32 with numOperands = 6
2663INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2664// Invalid: AtomicOr64 with numOperands = 0
2665
2666// Invalid: AtomicOr64 with numOperands = 1
2667INVALID_INST_FORM,
2668// AtomicOr64 U:G:64, UD:G:64
2669ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2670// Invalid: AtomicOr64 with numOperands = 3
2671INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2672// Invalid: AtomicOr64 with numOperands = 4
2673INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2674// Invalid: AtomicOr64 with numOperands = 5
2675INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2676// Invalid: AtomicOr64 with numOperands = 6
2677INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2678// Invalid: AtomicXor8 with numOperands = 0
2679
2680// Invalid: AtomicXor8 with numOperands = 1
2681INVALID_INST_FORM,
2682// AtomicXor8 U:G:8, UD:G:8
2683ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2684// Invalid: AtomicXor8 with numOperands = 3
2685INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2686// Invalid: AtomicXor8 with numOperands = 4
2687INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2688// Invalid: AtomicXor8 with numOperands = 5
2689INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2690// Invalid: AtomicXor8 with numOperands = 6
2691INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2692// Invalid: AtomicXor16 with numOperands = 0
2693
2694// Invalid: AtomicXor16 with numOperands = 1
2695INVALID_INST_FORM,
2696// AtomicXor16 U:G:16, UD:G:16
2697ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2698// Invalid: AtomicXor16 with numOperands = 3
2699INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2700// Invalid: AtomicXor16 with numOperands = 4
2701INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2702// Invalid: AtomicXor16 with numOperands = 5
2703INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2704// Invalid: AtomicXor16 with numOperands = 6
2705INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2706// Invalid: AtomicXor32 with numOperands = 0
2707
2708// Invalid: AtomicXor32 with numOperands = 1
2709INVALID_INST_FORM,
2710// AtomicXor32 U:G:32, UD:G:32
2711ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2712// Invalid: AtomicXor32 with numOperands = 3
2713INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2714// Invalid: AtomicXor32 with numOperands = 4
2715INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2716// Invalid: AtomicXor32 with numOperands = 5
2717INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2718// Invalid: AtomicXor32 with numOperands = 6
2719INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2720// Invalid: AtomicXor64 with numOperands = 0
2721
2722// Invalid: AtomicXor64 with numOperands = 1
2723INVALID_INST_FORM,
2724// AtomicXor64 U:G:64, UD:G:64
2725ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2726// Invalid: AtomicXor64 with numOperands = 3
2727INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2728// Invalid: AtomicXor64 with numOperands = 4
2729INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2730// Invalid: AtomicXor64 with numOperands = 5
2731INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2732// Invalid: AtomicXor64 with numOperands = 6
2733INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2734// Invalid: AtomicNeg8 with numOperands = 0
2735
2736// AtomicNeg8 UD:G:8
2737ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2738// Invalid: AtomicNeg8 with numOperands = 2
2739INVALID_INST_FORM, INVALID_INST_FORM,
2740// Invalid: AtomicNeg8 with numOperands = 3
2741INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2742// Invalid: AtomicNeg8 with numOperands = 4
2743INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2744// Invalid: AtomicNeg8 with numOperands = 5
2745INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2746// Invalid: AtomicNeg8 with numOperands = 6
2747INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2748// Invalid: AtomicNeg16 with numOperands = 0
2749
2750// AtomicNeg16 UD:G:16
2751ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2752// Invalid: AtomicNeg16 with numOperands = 2
2753INVALID_INST_FORM, INVALID_INST_FORM,
2754// Invalid: AtomicNeg16 with numOperands = 3
2755INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2756// Invalid: AtomicNeg16 with numOperands = 4
2757INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2758// Invalid: AtomicNeg16 with numOperands = 5
2759INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2760// Invalid: AtomicNeg16 with numOperands = 6
2761INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2762// Invalid: AtomicNeg32 with numOperands = 0
2763
2764// AtomicNeg32 UD:G:32
2765ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2766// Invalid: AtomicNeg32 with numOperands = 2
2767INVALID_INST_FORM, INVALID_INST_FORM,
2768// Invalid: AtomicNeg32 with numOperands = 3
2769INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2770// Invalid: AtomicNeg32 with numOperands = 4
2771INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2772// Invalid: AtomicNeg32 with numOperands = 5
2773INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2774// Invalid: AtomicNeg32 with numOperands = 6
2775INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2776// Invalid: AtomicNeg64 with numOperands = 0
2777
2778// AtomicNeg64 UD:G:64
2779ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2780// Invalid: AtomicNeg64 with numOperands = 2
2781INVALID_INST_FORM, INVALID_INST_FORM,
2782// Invalid: AtomicNeg64 with numOperands = 3
2783INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2784// Invalid: AtomicNeg64 with numOperands = 4
2785INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2786// Invalid: AtomicNeg64 with numOperands = 5
2787INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2788// Invalid: AtomicNeg64 with numOperands = 6
2789INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2790// Invalid: AtomicNot8 with numOperands = 0
2791
2792// AtomicNot8 UD:G:8
2793ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2794// Invalid: AtomicNot8 with numOperands = 2
2795INVALID_INST_FORM, INVALID_INST_FORM,
2796// Invalid: AtomicNot8 with numOperands = 3
2797INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2798// Invalid: AtomicNot8 with numOperands = 4
2799INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2800// Invalid: AtomicNot8 with numOperands = 5
2801INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2802// Invalid: AtomicNot8 with numOperands = 6
2803INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2804// Invalid: AtomicNot16 with numOperands = 0
2805
2806// AtomicNot16 UD:G:16
2807ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2808// Invalid: AtomicNot16 with numOperands = 2
2809INVALID_INST_FORM, INVALID_INST_FORM,
2810// Invalid: AtomicNot16 with numOperands = 3
2811INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2812// Invalid: AtomicNot16 with numOperands = 4
2813INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2814// Invalid: AtomicNot16 with numOperands = 5
2815INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2816// Invalid: AtomicNot16 with numOperands = 6
2817INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2818// Invalid: AtomicNot32 with numOperands = 0
2819
2820// AtomicNot32 UD:G:32
2821ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2822// Invalid: AtomicNot32 with numOperands = 2
2823INVALID_INST_FORM, INVALID_INST_FORM,
2824// Invalid: AtomicNot32 with numOperands = 3
2825INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2826// Invalid: AtomicNot32 with numOperands = 4
2827INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2828// Invalid: AtomicNot32 with numOperands = 5
2829INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2830// Invalid: AtomicNot32 with numOperands = 6
2831INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2832// Invalid: AtomicNot64 with numOperands = 0
2833
2834// AtomicNot64 UD:G:64
2835ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2836// Invalid: AtomicNot64 with numOperands = 2
2837INVALID_INST_FORM, INVALID_INST_FORM,
2838// Invalid: AtomicNot64 with numOperands = 3
2839INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2840// Invalid: AtomicNot64 with numOperands = 4
2841INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2842// Invalid: AtomicNot64 with numOperands = 5
2843INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2844// Invalid: AtomicNot64 with numOperands = 6
2845INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2846// Invalid: AtomicXchgAdd8 with numOperands = 0
2847
2848// Invalid: AtomicXchgAdd8 with numOperands = 1
2849INVALID_INST_FORM,
2850// AtomicXchgAdd8 UD:G:8, UD:G:8
2851ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2852// Invalid: AtomicXchgAdd8 with numOperands = 3
2853INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2854// Invalid: AtomicXchgAdd8 with numOperands = 4
2855INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2856// Invalid: AtomicXchgAdd8 with numOperands = 5
2857INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2858// Invalid: AtomicXchgAdd8 with numOperands = 6
2859INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2860// Invalid: AtomicXchgAdd16 with numOperands = 0
2861
2862// Invalid: AtomicXchgAdd16 with numOperands = 1
2863INVALID_INST_FORM,
2864// AtomicXchgAdd16 UD:G:16, UD:G:16
2865ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2866// Invalid: AtomicXchgAdd16 with numOperands = 3
2867INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2868// Invalid: AtomicXchgAdd16 with numOperands = 4
2869INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2870// Invalid: AtomicXchgAdd16 with numOperands = 5
2871INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2872// Invalid: AtomicXchgAdd16 with numOperands = 6
2873INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2874// Invalid: AtomicXchgAdd32 with numOperands = 0
2875
2876// Invalid: AtomicXchgAdd32 with numOperands = 1
2877INVALID_INST_FORM,
2878// AtomicXchgAdd32 UD:G:32, UD:G:32
2879ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2880// Invalid: AtomicXchgAdd32 with numOperands = 3
2881INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2882// Invalid: AtomicXchgAdd32 with numOperands = 4
2883INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2884// Invalid: AtomicXchgAdd32 with numOperands = 5
2885INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2886// Invalid: AtomicXchgAdd32 with numOperands = 6
2887INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2888// Invalid: AtomicXchgAdd64 with numOperands = 0
2889
2890// Invalid: AtomicXchgAdd64 with numOperands = 1
2891INVALID_INST_FORM,
2892// AtomicXchgAdd64 UD:G:64, UD:G:64
2893ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2894// Invalid: AtomicXchgAdd64 with numOperands = 3
2895INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2896// Invalid: AtomicXchgAdd64 with numOperands = 4
2897INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2898// Invalid: AtomicXchgAdd64 with numOperands = 5
2899INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2900// Invalid: AtomicXchgAdd64 with numOperands = 6
2901INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2902// Invalid: AtomicXchg8 with numOperands = 0
2903
2904// Invalid: AtomicXchg8 with numOperands = 1
2905INVALID_INST_FORM,
2906// AtomicXchg8 UD:G:8, UD:G:8
2907ENCODE_INST_FORM(Arg::UseDef, GP, Width8), ENCODE_INST_FORM(Arg::UseDef, GP, Width8),
2908// Invalid: AtomicXchg8 with numOperands = 3
2909INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2910// Invalid: AtomicXchg8 with numOperands = 4
2911INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2912// Invalid: AtomicXchg8 with numOperands = 5
2913INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2914// Invalid: AtomicXchg8 with numOperands = 6
2915INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2916// Invalid: AtomicXchg16 with numOperands = 0
2917
2918// Invalid: AtomicXchg16 with numOperands = 1
2919INVALID_INST_FORM,
2920// AtomicXchg16 UD:G:16, UD:G:16
2921ENCODE_INST_FORM(Arg::UseDef, GP, Width16), ENCODE_INST_FORM(Arg::UseDef, GP, Width16),
2922// Invalid: AtomicXchg16 with numOperands = 3
2923INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2924// Invalid: AtomicXchg16 with numOperands = 4
2925INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2926// Invalid: AtomicXchg16 with numOperands = 5
2927INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2928// Invalid: AtomicXchg16 with numOperands = 6
2929INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2930// Invalid: AtomicXchg32 with numOperands = 0
2931
2932// Invalid: AtomicXchg32 with numOperands = 1
2933INVALID_INST_FORM,
2934// AtomicXchg32 UD:G:32, UD:G:32
2935ENCODE_INST_FORM(Arg::UseDef, GP, Width32), ENCODE_INST_FORM(Arg::UseDef, GP, Width32),
2936// Invalid: AtomicXchg32 with numOperands = 3
2937INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2938// Invalid: AtomicXchg32 with numOperands = 4
2939INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2940// Invalid: AtomicXchg32 with numOperands = 5
2941INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2942// Invalid: AtomicXchg32 with numOperands = 6
2943INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2944// Invalid: AtomicXchg64 with numOperands = 0
2945
2946// Invalid: AtomicXchg64 with numOperands = 1
2947INVALID_INST_FORM,
2948// AtomicXchg64 UD:G:64, UD:G:64
2949ENCODE_INST_FORM(Arg::UseDef, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
2950// Invalid: AtomicXchg64 with numOperands = 3
2951INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2952// Invalid: AtomicXchg64 with numOperands = 4
2953INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2954// Invalid: AtomicXchg64 with numOperands = 5
2955INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2956// Invalid: AtomicXchg64 with numOperands = 6
2957INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2958// Invalid: LoadLink8 with numOperands = 0
2959
2960// Invalid: LoadLink8 with numOperands = 1
2961INVALID_INST_FORM,
2962// LoadLink8 U:G:8, ZD:G:8
2963ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2964// Invalid: LoadLink8 with numOperands = 3
2965INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2966// Invalid: LoadLink8 with numOperands = 4
2967INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2968// Invalid: LoadLink8 with numOperands = 5
2969INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2970// Invalid: LoadLink8 with numOperands = 6
2971INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2972// Invalid: LoadLinkAcq8 with numOperands = 0
2973
2974// Invalid: LoadLinkAcq8 with numOperands = 1
2975INVALID_INST_FORM,
2976// LoadLinkAcq8 U:G:8, ZD:G:8
2977ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::ZDef, GP, Width8),
2978// Invalid: LoadLinkAcq8 with numOperands = 3
2979INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2980// Invalid: LoadLinkAcq8 with numOperands = 4
2981INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2982// Invalid: LoadLinkAcq8 with numOperands = 5
2983INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2984// Invalid: LoadLinkAcq8 with numOperands = 6
2985INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2986// Invalid: StoreCond8 with numOperands = 0
2987
2988// Invalid: StoreCond8 with numOperands = 1
2989INVALID_INST_FORM,
2990// Invalid: StoreCond8 with numOperands = 2
2991INVALID_INST_FORM, INVALID_INST_FORM,
2992// StoreCond8 U:G:8, D:G:8, EZD:G:8
2993ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
2994// Invalid: StoreCond8 with numOperands = 4
2995INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2996// Invalid: StoreCond8 with numOperands = 5
2997INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
2998// Invalid: StoreCond8 with numOperands = 6
2999INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3000// Invalid: StoreCondRel8 with numOperands = 0
3001
3002// Invalid: StoreCondRel8 with numOperands = 1
3003INVALID_INST_FORM,
3004// Invalid: StoreCondRel8 with numOperands = 2
3005INVALID_INST_FORM, INVALID_INST_FORM,
3006// StoreCondRel8 U:G:8, D:G:8, EZD:G:8
3007ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Def, GP, Width8), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3008// Invalid: StoreCondRel8 with numOperands = 4
3009INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3010// Invalid: StoreCondRel8 with numOperands = 5
3011INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3012// Invalid: StoreCondRel8 with numOperands = 6
3013INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3014// Invalid: LoadLink16 with numOperands = 0
3015
3016// Invalid: LoadLink16 with numOperands = 1
3017INVALID_INST_FORM,
3018// LoadLink16 U:G:16, ZD:G:16
3019ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width16),
3020// Invalid: LoadLink16 with numOperands = 3
3021INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3022// Invalid: LoadLink16 with numOperands = 4
3023INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3024// Invalid: LoadLink16 with numOperands = 5
3025INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3026// Invalid: LoadLink16 with numOperands = 6
3027INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3028// Invalid: LoadLinkAcq16 with numOperands = 0
3029
3030// Invalid: LoadLinkAcq16 with numOperands = 1
3031INVALID_INST_FORM,
3032// LoadLinkAcq16 U:G:16, ZD:G:16
3033ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::ZDef, GP, Width16),
3034// Invalid: LoadLinkAcq16 with numOperands = 3
3035INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3036// Invalid: LoadLinkAcq16 with numOperands = 4
3037INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3038// Invalid: LoadLinkAcq16 with numOperands = 5
3039INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3040// Invalid: LoadLinkAcq16 with numOperands = 6
3041INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3042// Invalid: StoreCond16 with numOperands = 0
3043
3044// Invalid: StoreCond16 with numOperands = 1
3045INVALID_INST_FORM,
3046// Invalid: StoreCond16 with numOperands = 2
3047INVALID_INST_FORM, INVALID_INST_FORM,
3048// StoreCond16 U:G:16, D:G:16, EZD:G:8
3049ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3050// Invalid: StoreCond16 with numOperands = 4
3051INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3052// Invalid: StoreCond16 with numOperands = 5
3053INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3054// Invalid: StoreCond16 with numOperands = 6
3055INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3056// Invalid: StoreCondRel16 with numOperands = 0
3057
3058// Invalid: StoreCondRel16 with numOperands = 1
3059INVALID_INST_FORM,
3060// Invalid: StoreCondRel16 with numOperands = 2
3061INVALID_INST_FORM, INVALID_INST_FORM,
3062// StoreCondRel16 U:G:16, D:G:16, EZD:G:8
3063ENCODE_INST_FORM(Arg::Use, GP, Width16), ENCODE_INST_FORM(Arg::Def, GP, Width16), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3064// Invalid: StoreCondRel16 with numOperands = 4
3065INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3066// Invalid: StoreCondRel16 with numOperands = 5
3067INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3068// Invalid: StoreCondRel16 with numOperands = 6
3069INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3070// Invalid: LoadLink32 with numOperands = 0
3071
3072// Invalid: LoadLink32 with numOperands = 1
3073INVALID_INST_FORM,
3074// LoadLink32 U:G:32, ZD:G:32
3075ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3076// Invalid: LoadLink32 with numOperands = 3
3077INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3078// Invalid: LoadLink32 with numOperands = 4
3079INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3080// Invalid: LoadLink32 with numOperands = 5
3081INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3082// Invalid: LoadLink32 with numOperands = 6
3083INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3084// Invalid: LoadLinkAcq32 with numOperands = 0
3085
3086// Invalid: LoadLinkAcq32 with numOperands = 1
3087INVALID_INST_FORM,
3088// LoadLinkAcq32 U:G:32, ZD:G:32
3089ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3090// Invalid: LoadLinkAcq32 with numOperands = 3
3091INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3092// Invalid: LoadLinkAcq32 with numOperands = 4
3093INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3094// Invalid: LoadLinkAcq32 with numOperands = 5
3095INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3096// Invalid: LoadLinkAcq32 with numOperands = 6
3097INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3098// Invalid: StoreCond32 with numOperands = 0
3099
3100// Invalid: StoreCond32 with numOperands = 1
3101INVALID_INST_FORM,
3102// Invalid: StoreCond32 with numOperands = 2
3103INVALID_INST_FORM, INVALID_INST_FORM,
3104// StoreCond32 U:G:32, D:G:32, EZD:G:8
3105ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3106// Invalid: StoreCond32 with numOperands = 4
3107INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3108// Invalid: StoreCond32 with numOperands = 5
3109INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3110// Invalid: StoreCond32 with numOperands = 6
3111INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3112// Invalid: StoreCondRel32 with numOperands = 0
3113
3114// Invalid: StoreCondRel32 with numOperands = 1
3115INVALID_INST_FORM,
3116// Invalid: StoreCondRel32 with numOperands = 2
3117INVALID_INST_FORM, INVALID_INST_FORM,
3118// StoreCondRel32 U:G:32, D:G:32, EZD:G:8
3119ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Def, GP, Width32), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3120// Invalid: StoreCondRel32 with numOperands = 4
3121INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3122// Invalid: StoreCondRel32 with numOperands = 5
3123INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3124// Invalid: StoreCondRel32 with numOperands = 6
3125INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3126// Invalid: LoadLink64 with numOperands = 0
3127
3128// Invalid: LoadLink64 with numOperands = 1
3129INVALID_INST_FORM,
3130// LoadLink64 U:G:64, ZD:G:64
3131ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3132// Invalid: LoadLink64 with numOperands = 3
3133INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3134// Invalid: LoadLink64 with numOperands = 4
3135INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3136// Invalid: LoadLink64 with numOperands = 5
3137INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3138// Invalid: LoadLink64 with numOperands = 6
3139INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3140// Invalid: LoadLinkAcq64 with numOperands = 0
3141
3142// Invalid: LoadLinkAcq64 with numOperands = 1
3143INVALID_INST_FORM,
3144// LoadLinkAcq64 U:G:64, ZD:G:64
3145ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3146// Invalid: LoadLinkAcq64 with numOperands = 3
3147INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3148// Invalid: LoadLinkAcq64 with numOperands = 4
3149INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3150// Invalid: LoadLinkAcq64 with numOperands = 5
3151INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3152// Invalid: LoadLinkAcq64 with numOperands = 6
3153INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3154// Invalid: StoreCond64 with numOperands = 0
3155
3156// Invalid: StoreCond64 with numOperands = 1
3157INVALID_INST_FORM,
3158// Invalid: StoreCond64 with numOperands = 2
3159INVALID_INST_FORM, INVALID_INST_FORM,
3160// StoreCond64 U:G:64, D:G:64, EZD:G:8
3161ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3162// Invalid: StoreCond64 with numOperands = 4
3163INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3164// Invalid: StoreCond64 with numOperands = 5
3165INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3166// Invalid: StoreCond64 with numOperands = 6
3167INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3168// Invalid: StoreCondRel64 with numOperands = 0
3169
3170// Invalid: StoreCondRel64 with numOperands = 1
3171INVALID_INST_FORM,
3172// Invalid: StoreCondRel64 with numOperands = 2
3173INVALID_INST_FORM, INVALID_INST_FORM,
3174// StoreCondRel64 U:G:64, D:G:64, EZD:G:8
3175ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Def, GP, Width64), ENCODE_INST_FORM(Arg::EarlyZDef, GP, Width8),
3176// Invalid: StoreCondRel64 with numOperands = 4
3177INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3178// Invalid: StoreCondRel64 with numOperands = 5
3179INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3180// Invalid: StoreCondRel64 with numOperands = 6
3181INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3182// Invalid: Depend32 with numOperands = 0
3183
3184// Invalid: Depend32 with numOperands = 1
3185INVALID_INST_FORM,
3186// Depend32 U:G:32, ZD:G:32
3187ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3188// Invalid: Depend32 with numOperands = 3
3189INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3190// Invalid: Depend32 with numOperands = 4
3191INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3192// Invalid: Depend32 with numOperands = 5
3193INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3194// Invalid: Depend32 with numOperands = 6
3195INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3196// Invalid: Depend64 with numOperands = 0
3197
3198// Invalid: Depend64 with numOperands = 1
3199INVALID_INST_FORM,
3200// Depend64 U:G:64, ZD:G:64
3201ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3202// Invalid: Depend64 with numOperands = 3
3203INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3204// Invalid: Depend64 with numOperands = 4
3205INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3206// Invalid: Depend64 with numOperands = 5
3207INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3208// Invalid: Depend64 with numOperands = 6
3209INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3210// Invalid: Compare32 with numOperands = 0
3211
3212// Invalid: Compare32 with numOperands = 1
3213INVALID_INST_FORM,
3214// Invalid: Compare32 with numOperands = 2
3215INVALID_INST_FORM, INVALID_INST_FORM,
3216// Invalid: Compare32 with numOperands = 3
3217INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3218// Compare32 U:G:32, U:G:32, U:G:32, ZD:G:32
3219ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3220// Invalid: Compare32 with numOperands = 5
3221INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3222// Invalid: Compare32 with numOperands = 6
3223INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3224// Invalid: Compare64 with numOperands = 0
3225
3226// Invalid: Compare64 with numOperands = 1
3227INVALID_INST_FORM,
3228// Invalid: Compare64 with numOperands = 2
3229INVALID_INST_FORM, INVALID_INST_FORM,
3230// Invalid: Compare64 with numOperands = 3
3231INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3232// Compare64 U:G:32, U:G:64, U:G:64, ZD:G:32
3233ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3234// Invalid: Compare64 with numOperands = 5
3235INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3236// Invalid: Compare64 with numOperands = 6
3237INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3238// Invalid: Test32 with numOperands = 0
3239
3240// Invalid: Test32 with numOperands = 1
3241INVALID_INST_FORM,
3242// Invalid: Test32 with numOperands = 2
3243INVALID_INST_FORM, INVALID_INST_FORM,
3244// Invalid: Test32 with numOperands = 3
3245INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3246// Test32 U:G:32, U:G:32, U:G:32, ZD:G:32
3247ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3248// Invalid: Test32 with numOperands = 5
3249INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3250// Invalid: Test32 with numOperands = 6
3251INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3252// Invalid: Test64 with numOperands = 0
3253
3254// Invalid: Test64 with numOperands = 1
3255INVALID_INST_FORM,
3256// Invalid: Test64 with numOperands = 2
3257INVALID_INST_FORM, INVALID_INST_FORM,
3258// Invalid: Test64 with numOperands = 3
3259INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3260// Test64 U:G:32, U:G:64, U:G:64, ZD:G:32
3261ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3262// Invalid: Test64 with numOperands = 5
3263INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3264// Invalid: Test64 with numOperands = 6
3265INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3266// Invalid: CompareDouble with numOperands = 0
3267
3268// Invalid: CompareDouble with numOperands = 1
3269INVALID_INST_FORM,
3270// Invalid: CompareDouble with numOperands = 2
3271INVALID_INST_FORM, INVALID_INST_FORM,
3272// Invalid: CompareDouble with numOperands = 3
3273INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3274// CompareDouble U:G:32, U:F:64, U:F:64, ZD:G:32
3275ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3276// Invalid: CompareDouble with numOperands = 5
3277INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3278// Invalid: CompareDouble with numOperands = 6
3279INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3280// Invalid: CompareFloat with numOperands = 0
3281
3282// Invalid: CompareFloat with numOperands = 1
3283INVALID_INST_FORM,
3284// Invalid: CompareFloat with numOperands = 2
3285INVALID_INST_FORM, INVALID_INST_FORM,
3286// Invalid: CompareFloat with numOperands = 3
3287INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3288// CompareFloat U:G:32, U:F:32, U:F:32, ZD:G:32
3289ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3290// Invalid: CompareFloat with numOperands = 5
3291INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3292// Invalid: CompareFloat with numOperands = 6
3293INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3294// Invalid: Branch8 with numOperands = 0
3295
3296// Invalid: Branch8 with numOperands = 1
3297INVALID_INST_FORM,
3298// Invalid: Branch8 with numOperands = 2
3299INVALID_INST_FORM, INVALID_INST_FORM,
3300// Branch8 U:G:32, U:G:8, U:G:8
3301ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8),
3302// Invalid: Branch8 with numOperands = 4
3303INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3304// Invalid: Branch8 with numOperands = 5
3305INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3306// Invalid: Branch8 with numOperands = 6
3307INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3308// Invalid: Branch32 with numOperands = 0
3309
3310// Invalid: Branch32 with numOperands = 1
3311INVALID_INST_FORM,
3312// Invalid: Branch32 with numOperands = 2
3313INVALID_INST_FORM, INVALID_INST_FORM,
3314// Branch32 U:G:32, U:G:32, U:G:32
3315ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
3316// Invalid: Branch32 with numOperands = 4
3317INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3318// Invalid: Branch32 with numOperands = 5
3319INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3320// Invalid: Branch32 with numOperands = 6
3321INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3322// Invalid: Branch64 with numOperands = 0
3323
3324// Invalid: Branch64 with numOperands = 1
3325INVALID_INST_FORM,
3326// Invalid: Branch64 with numOperands = 2
3327INVALID_INST_FORM, INVALID_INST_FORM,
3328// Branch64 U:G:32, U:G:64, U:G:64
3329ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
3330// Invalid: Branch64 with numOperands = 4
3331INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3332// Invalid: Branch64 with numOperands = 5
3333INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3334// Invalid: Branch64 with numOperands = 6
3335INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3336// Invalid: BranchTest8 with numOperands = 0
3337
3338// Invalid: BranchTest8 with numOperands = 1
3339INVALID_INST_FORM,
3340// Invalid: BranchTest8 with numOperands = 2
3341INVALID_INST_FORM, INVALID_INST_FORM,
3342// BranchTest8 U:G:32, U:G:8, U:G:8
3343ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width8), ENCODE_INST_FORM(Arg::Use, GP, Width8),
3344// Invalid: BranchTest8 with numOperands = 4
3345INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3346// Invalid: BranchTest8 with numOperands = 5
3347INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3348// Invalid: BranchTest8 with numOperands = 6
3349INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3350// Invalid: BranchTest32 with numOperands = 0
3351
3352// Invalid: BranchTest32 with numOperands = 1
3353INVALID_INST_FORM,
3354// Invalid: BranchTest32 with numOperands = 2
3355INVALID_INST_FORM, INVALID_INST_FORM,
3356// BranchTest32 U:G:32, U:G:32, U:G:32
3357ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32),
3358// Invalid: BranchTest32 with numOperands = 4
3359INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3360// Invalid: BranchTest32 with numOperands = 5
3361INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3362// Invalid: BranchTest32 with numOperands = 6
3363INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3364// Invalid: BranchTest64 with numOperands = 0
3365
3366// Invalid: BranchTest64 with numOperands = 1
3367INVALID_INST_FORM,
3368// Invalid: BranchTest64 with numOperands = 2
3369INVALID_INST_FORM, INVALID_INST_FORM,
3370// BranchTest64 U:G:32, U:G:64, U:G:64
3371ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64),
3372// Invalid: BranchTest64 with numOperands = 4
3373INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3374// Invalid: BranchTest64 with numOperands = 5
3375INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3376// Invalid: BranchTest64 with numOperands = 6
3377INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3378// Invalid: BranchDouble with numOperands = 0
3379
3380// Invalid: BranchDouble with numOperands = 1
3381INVALID_INST_FORM,
3382// Invalid: BranchDouble with numOperands = 2
3383INVALID_INST_FORM, INVALID_INST_FORM,
3384// BranchDouble U:G:32, U:F:64, U:F:64
3385ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64),
3386// Invalid: BranchDouble with numOperands = 4
3387INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3388// Invalid: BranchDouble with numOperands = 5
3389INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3390// Invalid: BranchDouble with numOperands = 6
3391INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3392// Invalid: BranchFloat with numOperands = 0
3393
3394// Invalid: BranchFloat with numOperands = 1
3395INVALID_INST_FORM,
3396// Invalid: BranchFloat with numOperands = 2
3397INVALID_INST_FORM, INVALID_INST_FORM,
3398// BranchFloat U:G:32, U:F:32, U:F:32
3399ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32),
3400// Invalid: BranchFloat with numOperands = 4
3401INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3402// Invalid: BranchFloat with numOperands = 5
3403INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3404// Invalid: BranchFloat with numOperands = 6
3405INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3406// Invalid: BranchAdd32 with numOperands = 0
3407
3408// Invalid: BranchAdd32 with numOperands = 1
3409INVALID_INST_FORM,
3410// Invalid: BranchAdd32 with numOperands = 2
3411INVALID_INST_FORM, INVALID_INST_FORM,
3412// BranchAdd32 U:G:32, U:G:32, UZD:G:32
3413ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3414// BranchAdd32 U:G:32, U:G:32, U:G:32, ZD:G:32
3415ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3416// Invalid: BranchAdd32 with numOperands = 5
3417INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3418// Invalid: BranchAdd32 with numOperands = 6
3419INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3420// Invalid: BranchAdd64 with numOperands = 0
3421
3422// Invalid: BranchAdd64 with numOperands = 1
3423INVALID_INST_FORM,
3424// Invalid: BranchAdd64 with numOperands = 2
3425INVALID_INST_FORM, INVALID_INST_FORM,
3426// BranchAdd64 U:G:32, U:G:64, UD:G:64
3427ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
3428// BranchAdd64 U:G:32, U:G:64, U:G:64, ZD:G:64
3429ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3430// Invalid: BranchAdd64 with numOperands = 5
3431INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3432// Invalid: BranchAdd64 with numOperands = 6
3433INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3434// Invalid: BranchMul32 with numOperands = 0
3435
3436// Invalid: BranchMul32 with numOperands = 1
3437INVALID_INST_FORM,
3438// Invalid: BranchMul32 with numOperands = 2
3439INVALID_INST_FORM, INVALID_INST_FORM,
3440// BranchMul32 U:G:32, U:G:32, UZD:G:32
3441ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3442// BranchMul32 U:G:32, U:G:32, U:G:32, ZD:G:32
3443ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3444// Invalid: BranchMul32 with numOperands = 5
3445INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3446// BranchMul32 U:G:32, U:G:32, U:G:32, S:G:32, S:G:32, ZD:G:32
3447ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Scratch, GP, Width32), ENCODE_INST_FORM(Arg::Scratch, GP, Width32), ENCODE_INST_FORM(Arg::ZDef, GP, Width32),
3448// Invalid: BranchMul64 with numOperands = 0
3449
3450// Invalid: BranchMul64 with numOperands = 1
3451INVALID_INST_FORM,
3452// Invalid: BranchMul64 with numOperands = 2
3453INVALID_INST_FORM, INVALID_INST_FORM,
3454// BranchMul64 U:G:32, U:G:64, UZD:G:64
3455ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64),
3456// Invalid: BranchMul64 with numOperands = 4
3457INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3458// Invalid: BranchMul64 with numOperands = 5
3459INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3460// BranchMul64 U:G:32, U:G:64, U:G:64, S:G:64, S:G:64, ZD:G:64
3461ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Scratch, GP, Width64), ENCODE_INST_FORM(Arg::Scratch, GP, Width64), ENCODE_INST_FORM(Arg::ZDef, GP, Width64),
3462// Invalid: BranchSub32 with numOperands = 0
3463
3464// Invalid: BranchSub32 with numOperands = 1
3465INVALID_INST_FORM,
3466// Invalid: BranchSub32 with numOperands = 2
3467INVALID_INST_FORM, INVALID_INST_FORM,
3468// BranchSub32 U:G:32, U:G:32, UZD:G:32
3469ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3470// Invalid: BranchSub32 with numOperands = 4
3471INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3472// Invalid: BranchSub32 with numOperands = 5
3473INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3474// Invalid: BranchSub32 with numOperands = 6
3475INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3476// Invalid: BranchSub64 with numOperands = 0
3477
3478// Invalid: BranchSub64 with numOperands = 1
3479INVALID_INST_FORM,
3480// Invalid: BranchSub64 with numOperands = 2
3481INVALID_INST_FORM, INVALID_INST_FORM,
3482// BranchSub64 U:G:32, U:G:64, UD:G:64
3483ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::UseDef, GP, Width64),
3484// Invalid: BranchSub64 with numOperands = 4
3485INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3486// Invalid: BranchSub64 with numOperands = 5
3487INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3488// Invalid: BranchSub64 with numOperands = 6
3489INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3490// Invalid: BranchNeg32 with numOperands = 0
3491
3492// Invalid: BranchNeg32 with numOperands = 1
3493INVALID_INST_FORM,
3494// BranchNeg32 U:G:32, UZD:G:32
3495ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width32),
3496// Invalid: BranchNeg32 with numOperands = 3
3497INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3498// Invalid: BranchNeg32 with numOperands = 4
3499INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3500// Invalid: BranchNeg32 with numOperands = 5
3501INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3502// Invalid: BranchNeg32 with numOperands = 6
3503INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3504// Invalid: BranchNeg64 with numOperands = 0
3505
3506// Invalid: BranchNeg64 with numOperands = 1
3507INVALID_INST_FORM,
3508// BranchNeg64 U:G:32, UZD:G:64
3509ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::UseZDef, GP, Width64),
3510// Invalid: BranchNeg64 with numOperands = 3
3511INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3512// Invalid: BranchNeg64 with numOperands = 4
3513INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3514// Invalid: BranchNeg64 with numOperands = 5
3515INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3516// Invalid: BranchNeg64 with numOperands = 6
3517INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3518// Invalid: MoveConditionally32 with numOperands = 0
3519
3520// Invalid: MoveConditionally32 with numOperands = 1
3521INVALID_INST_FORM,
3522// Invalid: MoveConditionally32 with numOperands = 2
3523INVALID_INST_FORM, INVALID_INST_FORM,
3524// Invalid: MoveConditionally32 with numOperands = 3
3525INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3526// Invalid: MoveConditionally32 with numOperands = 4
3527INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3528// MoveConditionally32 U:G:32, U:G:32, U:G:32, U:G:Ptr, UD:G:Ptr
3529ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3530// MoveConditionally32 U:G:32, U:G:32, U:G:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3531ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3532// Invalid: MoveConditionally64 with numOperands = 0
3533
3534// Invalid: MoveConditionally64 with numOperands = 1
3535INVALID_INST_FORM,
3536// Invalid: MoveConditionally64 with numOperands = 2
3537INVALID_INST_FORM, INVALID_INST_FORM,
3538// Invalid: MoveConditionally64 with numOperands = 3
3539INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3540// Invalid: MoveConditionally64 with numOperands = 4
3541INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3542// MoveConditionally64 U:G:32, U:G:64, U:G:64, U:G:Ptr, UD:G:Ptr
3543ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3544// MoveConditionally64 U:G:32, U:G:64, U:G:64, U:G:Ptr, U:G:Ptr, D:G:Ptr
3545ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3546// Invalid: MoveConditionallyTest32 with numOperands = 0
3547
3548// Invalid: MoveConditionallyTest32 with numOperands = 1
3549INVALID_INST_FORM,
3550// Invalid: MoveConditionallyTest32 with numOperands = 2
3551INVALID_INST_FORM, INVALID_INST_FORM,
3552// Invalid: MoveConditionallyTest32 with numOperands = 3
3553INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3554// Invalid: MoveConditionallyTest32 with numOperands = 4
3555INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3556// MoveConditionallyTest32 U:G:32, U:G:32, U:G:32, U:G:Ptr, UD:G:Ptr
3557ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3558// MoveConditionallyTest32 U:G:32, U:G:32, U:G:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3559ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3560// Invalid: MoveConditionallyTest64 with numOperands = 0
3561
3562// Invalid: MoveConditionallyTest64 with numOperands = 1
3563INVALID_INST_FORM,
3564// Invalid: MoveConditionallyTest64 with numOperands = 2
3565INVALID_INST_FORM, INVALID_INST_FORM,
3566// Invalid: MoveConditionallyTest64 with numOperands = 3
3567INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3568// Invalid: MoveConditionallyTest64 with numOperands = 4
3569INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3570// MoveConditionallyTest64 U:G:32, U:G:64, U:G:64, U:G:Ptr, UD:G:Ptr
3571ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3572// MoveConditionallyTest64 U:G:32, U:G:32, U:G:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3573ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3574// Invalid: MoveConditionallyDouble with numOperands = 0
3575
3576// Invalid: MoveConditionallyDouble with numOperands = 1
3577INVALID_INST_FORM,
3578// Invalid: MoveConditionallyDouble with numOperands = 2
3579INVALID_INST_FORM, INVALID_INST_FORM,
3580// Invalid: MoveConditionallyDouble with numOperands = 3
3581INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3582// Invalid: MoveConditionallyDouble with numOperands = 4
3583INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3584// MoveConditionallyDouble U:G:32, U:F:64, U:F:64, U:G:Ptr, UD:G:Ptr
3585ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3586// MoveConditionallyDouble U:G:32, U:F:64, U:F:64, U:G:Ptr, U:G:Ptr, D:G:Ptr
3587ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3588// Invalid: MoveConditionallyFloat with numOperands = 0
3589
3590// Invalid: MoveConditionallyFloat with numOperands = 1
3591INVALID_INST_FORM,
3592// Invalid: MoveConditionallyFloat with numOperands = 2
3593INVALID_INST_FORM, INVALID_INST_FORM,
3594// Invalid: MoveConditionallyFloat with numOperands = 3
3595INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3596// Invalid: MoveConditionallyFloat with numOperands = 4
3597INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3598// MoveConditionallyFloat U:G:32, U:F:32, U:F:32, U:G:Ptr, UD:G:Ptr
3599ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::UseDef, GP, POINTER_WIDTH),
3600// MoveConditionallyFloat U:G:32, U:F:32, U:F:32, U:G:Ptr, U:G:Ptr, D:G:Ptr
3601ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Use, GP, POINTER_WIDTH), ENCODE_INST_FORM(Arg::Def, GP, POINTER_WIDTH),
3602// Invalid: MoveDoubleConditionally32 with numOperands = 0
3603
3604// Invalid: MoveDoubleConditionally32 with numOperands = 1
3605INVALID_INST_FORM,
3606// Invalid: MoveDoubleConditionally32 with numOperands = 2
3607INVALID_INST_FORM, INVALID_INST_FORM,
3608// Invalid: MoveDoubleConditionally32 with numOperands = 3
3609INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3610// Invalid: MoveDoubleConditionally32 with numOperands = 4
3611INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3612// Invalid: MoveDoubleConditionally32 with numOperands = 5
3613INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3614// MoveDoubleConditionally32 U:G:32, U:G:32, U:G:32, U:F:64, U:F:64, D:F:64
3615ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3616// Invalid: MoveDoubleConditionally64 with numOperands = 0
3617
3618// Invalid: MoveDoubleConditionally64 with numOperands = 1
3619INVALID_INST_FORM,
3620// Invalid: MoveDoubleConditionally64 with numOperands = 2
3621INVALID_INST_FORM, INVALID_INST_FORM,
3622// Invalid: MoveDoubleConditionally64 with numOperands = 3
3623INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3624// Invalid: MoveDoubleConditionally64 with numOperands = 4
3625INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3626// Invalid: MoveDoubleConditionally64 with numOperands = 5
3627INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3628// MoveDoubleConditionally64 U:G:32, U:G:64, U:G:64, U:F:64, U:F:64, D:F:64
3629ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3630// Invalid: MoveDoubleConditionallyTest32 with numOperands = 0
3631
3632// Invalid: MoveDoubleConditionallyTest32 with numOperands = 1
3633INVALID_INST_FORM,
3634// Invalid: MoveDoubleConditionallyTest32 with numOperands = 2
3635INVALID_INST_FORM, INVALID_INST_FORM,
3636// Invalid: MoveDoubleConditionallyTest32 with numOperands = 3
3637INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3638// Invalid: MoveDoubleConditionallyTest32 with numOperands = 4
3639INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3640// Invalid: MoveDoubleConditionallyTest32 with numOperands = 5
3641INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3642// MoveDoubleConditionallyTest32 U:G:32, U:G:32, U:G:32, U:F:64, U:F:64, D:F:64
3643ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3644// Invalid: MoveDoubleConditionallyTest64 with numOperands = 0
3645
3646// Invalid: MoveDoubleConditionallyTest64 with numOperands = 1
3647INVALID_INST_FORM,
3648// Invalid: MoveDoubleConditionallyTest64 with numOperands = 2
3649INVALID_INST_FORM, INVALID_INST_FORM,
3650// Invalid: MoveDoubleConditionallyTest64 with numOperands = 3
3651INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3652// Invalid: MoveDoubleConditionallyTest64 with numOperands = 4
3653INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3654// Invalid: MoveDoubleConditionallyTest64 with numOperands = 5
3655INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3656// MoveDoubleConditionallyTest64 U:G:32, U:G:64, U:G:64, U:F:64, U:F:64, D:F:64
3657ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, GP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3658// Invalid: MoveDoubleConditionallyDouble with numOperands = 0
3659
3660// Invalid: MoveDoubleConditionallyDouble with numOperands = 1
3661INVALID_INST_FORM,
3662// Invalid: MoveDoubleConditionallyDouble with numOperands = 2
3663INVALID_INST_FORM, INVALID_INST_FORM,
3664// Invalid: MoveDoubleConditionallyDouble with numOperands = 3
3665INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3666// Invalid: MoveDoubleConditionallyDouble with numOperands = 4
3667INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3668// Invalid: MoveDoubleConditionallyDouble with numOperands = 5
3669INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3670// MoveDoubleConditionallyDouble U:G:32, U:F:64, U:F:64, U:F:64, U:F:64, D:F:64
3671ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3672// Invalid: MoveDoubleConditionallyFloat with numOperands = 0
3673
3674// Invalid: MoveDoubleConditionallyFloat with numOperands = 1
3675INVALID_INST_FORM,
3676// Invalid: MoveDoubleConditionallyFloat with numOperands = 2
3677INVALID_INST_FORM, INVALID_INST_FORM,
3678// Invalid: MoveDoubleConditionallyFloat with numOperands = 3
3679INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3680// Invalid: MoveDoubleConditionallyFloat with numOperands = 4
3681INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3682// Invalid: MoveDoubleConditionallyFloat with numOperands = 5
3683INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3684// MoveDoubleConditionallyFloat U:G:32, U:F:32, U:F:32, U:F:64, U:F:64, D:F:64
3685ENCODE_INST_FORM(Arg::Use, GP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width32), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Use, FP, Width64), ENCODE_INST_FORM(Arg::Def, FP, Width64),
3686// MemoryFence
3687
3688// Invalid: MemoryFence with numOperands = 1
3689INVALID_INST_FORM,
3690// Invalid: MemoryFence with numOperands = 2
3691INVALID_INST_FORM, INVALID_INST_FORM,
3692// Invalid: MemoryFence with numOperands = 3
3693INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3694// Invalid: MemoryFence with numOperands = 4
3695INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3696// Invalid: MemoryFence with numOperands = 5
3697INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3698// Invalid: MemoryFence with numOperands = 6
3699INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3700// StoreFence
3701
3702// Invalid: StoreFence with numOperands = 1
3703INVALID_INST_FORM,
3704// Invalid: StoreFence with numOperands = 2
3705INVALID_INST_FORM, INVALID_INST_FORM,
3706// Invalid: StoreFence with numOperands = 3
3707INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3708// Invalid: StoreFence with numOperands = 4
3709INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3710// Invalid: StoreFence with numOperands = 5
3711INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3712// Invalid: StoreFence with numOperands = 6
3713INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3714// LoadFence
3715
3716// Invalid: LoadFence with numOperands = 1
3717INVALID_INST_FORM,
3718// Invalid: LoadFence with numOperands = 2
3719INVALID_INST_FORM, INVALID_INST_FORM,
3720// Invalid: LoadFence with numOperands = 3
3721INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3722// Invalid: LoadFence with numOperands = 4
3723INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3724// Invalid: LoadFence with numOperands = 5
3725INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3726// Invalid: LoadFence with numOperands = 6
3727INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3728// Jump
3729
3730// Invalid: Jump with numOperands = 1
3731INVALID_INST_FORM,
3732// Invalid: Jump with numOperands = 2
3733INVALID_INST_FORM, INVALID_INST_FORM,
3734// Invalid: Jump with numOperands = 3
3735INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3736// Invalid: Jump with numOperands = 4
3737INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3738// Invalid: Jump with numOperands = 5
3739INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3740// Invalid: Jump with numOperands = 6
3741INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3742// RetVoid
3743
3744// Invalid: RetVoid with numOperands = 1
3745INVALID_INST_FORM,
3746// Invalid: RetVoid with numOperands = 2
3747INVALID_INST_FORM, INVALID_INST_FORM,
3748// Invalid: RetVoid with numOperands = 3
3749INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3750// Invalid: RetVoid with numOperands = 4
3751INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3752// Invalid: RetVoid with numOperands = 5
3753INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3754// Invalid: RetVoid with numOperands = 6
3755INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3756// Invalid: Ret32 with numOperands = 0
3757
3758// Ret32 U:G:32
3759ENCODE_INST_FORM(Arg::Use, GP, Width32),
3760// Invalid: Ret32 with numOperands = 2
3761INVALID_INST_FORM, INVALID_INST_FORM,
3762// Invalid: Ret32 with numOperands = 3
3763INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3764// Invalid: Ret32 with numOperands = 4
3765INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3766// Invalid: Ret32 with numOperands = 5
3767INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3768// Invalid: Ret32 with numOperands = 6
3769INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3770// Invalid: Ret64 with numOperands = 0
3771
3772// Ret64 U:G:64
3773ENCODE_INST_FORM(Arg::Use, GP, Width64),
3774// Invalid: Ret64 with numOperands = 2
3775INVALID_INST_FORM, INVALID_INST_FORM,
3776// Invalid: Ret64 with numOperands = 3
3777INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3778// Invalid: Ret64 with numOperands = 4
3779INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3780// Invalid: Ret64 with numOperands = 5
3781INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3782// Invalid: Ret64 with numOperands = 6
3783INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3784// Invalid: RetFloat with numOperands = 0
3785
3786// RetFloat U:F:32
3787ENCODE_INST_FORM(Arg::Use, FP, Width32),
3788// Invalid: RetFloat with numOperands = 2
3789INVALID_INST_FORM, INVALID_INST_FORM,
3790// Invalid: RetFloat with numOperands = 3
3791INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3792// Invalid: RetFloat with numOperands = 4
3793INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3794// Invalid: RetFloat with numOperands = 5
3795INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3796// Invalid: RetFloat with numOperands = 6
3797INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3798// Invalid: RetDouble with numOperands = 0
3799
3800// RetDouble U:F:64
3801ENCODE_INST_FORM(Arg::Use, FP, Width64),
3802// Invalid: RetDouble with numOperands = 2
3803INVALID_INST_FORM, INVALID_INST_FORM,
3804// Invalid: RetDouble with numOperands = 3
3805INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3806// Invalid: RetDouble with numOperands = 4
3807INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3808// Invalid: RetDouble with numOperands = 5
3809INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3810// Invalid: RetDouble with numOperands = 6
3811INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3812// Oops
3813
3814// Invalid: Oops with numOperands = 1
3815INVALID_INST_FORM,
3816// Invalid: Oops with numOperands = 2
3817INVALID_INST_FORM, INVALID_INST_FORM,
3818// Invalid: Oops with numOperands = 3
3819INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3820// Invalid: Oops with numOperands = 4
3821INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3822// Invalid: Oops with numOperands = 5
3823INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3824// Invalid: Oops with numOperands = 6
3825INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3826// Invalid: EntrySwitch with numOperands = 0
3827
3828// Invalid: EntrySwitch with numOperands = 1
3829INVALID_INST_FORM,
3830// Invalid: EntrySwitch with numOperands = 2
3831INVALID_INST_FORM, INVALID_INST_FORM,
3832// Invalid: EntrySwitch with numOperands = 3
3833INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3834// Invalid: EntrySwitch with numOperands = 4
3835INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3836// Invalid: EntrySwitch with numOperands = 5
3837INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3838// Invalid: EntrySwitch with numOperands = 6
3839INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3840// Invalid: Shuffle with numOperands = 0
3841
3842// Invalid: Shuffle with numOperands = 1
3843INVALID_INST_FORM,
3844// Invalid: Shuffle with numOperands = 2
3845INVALID_INST_FORM, INVALID_INST_FORM,
3846// Invalid: Shuffle with numOperands = 3
3847INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3848// Invalid: Shuffle with numOperands = 4
3849INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3850// Invalid: Shuffle with numOperands = 5
3851INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3852// Invalid: Shuffle with numOperands = 6
3853INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3854// Invalid: Patch with numOperands = 0
3855
3856// Invalid: Patch with numOperands = 1
3857INVALID_INST_FORM,
3858// Invalid: Patch with numOperands = 2
3859INVALID_INST_FORM, INVALID_INST_FORM,
3860// Invalid: Patch with numOperands = 3
3861INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3862// Invalid: Patch with numOperands = 4
3863INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3864// Invalid: Patch with numOperands = 5
3865INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3866// Invalid: Patch with numOperands = 6
3867INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3868// Invalid: CCall with numOperands = 0
3869
3870// Invalid: CCall with numOperands = 1
3871INVALID_INST_FORM,
3872// Invalid: CCall with numOperands = 2
3873INVALID_INST_FORM, INVALID_INST_FORM,
3874// Invalid: CCall with numOperands = 3
3875INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3876// Invalid: CCall with numOperands = 4
3877INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3878// Invalid: CCall with numOperands = 5
3879INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3880// Invalid: CCall with numOperands = 6
3881INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3882// Invalid: ColdCCall with numOperands = 0
3883
3884// Invalid: ColdCCall with numOperands = 1
3885INVALID_INST_FORM,
3886// Invalid: ColdCCall with numOperands = 2
3887INVALID_INST_FORM, INVALID_INST_FORM,
3888// Invalid: ColdCCall with numOperands = 3
3889INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3890// Invalid: ColdCCall with numOperands = 4
3891INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3892// Invalid: ColdCCall with numOperands = 5
3893INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3894// Invalid: ColdCCall with numOperands = 6
3895INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3896// Invalid: WasmBoundsCheck with numOperands = 0
3897
3898// Invalid: WasmBoundsCheck with numOperands = 1
3899INVALID_INST_FORM,
3900// Invalid: WasmBoundsCheck with numOperands = 2
3901INVALID_INST_FORM, INVALID_INST_FORM,
3902// Invalid: WasmBoundsCheck with numOperands = 3
3903INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3904// Invalid: WasmBoundsCheck with numOperands = 4
3905INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3906// Invalid: WasmBoundsCheck with numOperands = 5
3907INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3908// Invalid: WasmBoundsCheck with numOperands = 6
3909INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM, INVALID_INST_FORM,
3910};
3911void Inst::forEachArgCustom(ScopedLambda<EachArgCallback> lambda)
3912{
3913switch (kind.opcode) {
3914case Opcode::EntrySwitch:
3915EntrySwitchCustom::forEachArg(*this, lambda);
3916break;
3917case Opcode::Shuffle:
3918ShuffleCustom::forEachArg(*this, lambda);
3919break;
3920case Opcode::Patch:
3921PatchCustom::forEachArg(*this, lambda);
3922break;
3923case Opcode::CCall:
3924CCallCustom::forEachArg(*this, lambda);
3925break;
3926case Opcode::ColdCCall:
3927ColdCCallCustom::forEachArg(*this, lambda);
3928break;
3929case Opcode::WasmBoundsCheck:
3930WasmBoundsCheckCustom::forEachArg(*this, lambda);
3931break;
3932default:
3933dataLog("Bad call to forEachArgCustom, not custom opcode: ", kind, "\n");
3934RELEASE_ASSERT_NOT_REACHED();
3935}
3936}
3937bool Inst::isValidForm()
3938{
3939switch (this->kind.opcode) {
3940case Opcode::Nop:
3941switch (this->args.size()) {
3942case 0:
3943OPGEN_RETURN(true);
3944break;
3945break;
3946default:
3947break;
3948}
3949break;
3950case Opcode::Add32:
3951switch (this->args.size()) {
3952case 3:
3953switch (this->args[0].kind()) {
3954case Arg::Imm:
3955switch (this->args[1].kind()) {
3956case Arg::Tmp:
3957switch (this->args[2].kind()) {
3958case Arg::Tmp:
3959if (!Arg::isValidImmForm(args[0].value()))
3960OPGEN_RETURN(false);
3961if (!args[1].tmp().isGP())
3962OPGEN_RETURN(false);
3963if (!args[2].tmp().isGP())
3964OPGEN_RETURN(false);
3965OPGEN_RETURN(true);
3966break;
3967break;
3968default:
3969break;
3970}
3971break;
3972default:
3973break;
3974}
3975break;
3976case Arg::Tmp:
3977switch (this->args[1].kind()) {
3978case Arg::Tmp:
3979switch (this->args[2].kind()) {
3980case Arg::Tmp:
3981if (!args[0].tmp().isGP())
3982OPGEN_RETURN(false);
3983if (!args[1].tmp().isGP())
3984OPGEN_RETURN(false);
3985if (!args[2].tmp().isGP())
3986OPGEN_RETURN(false);
3987OPGEN_RETURN(true);
3988break;
3989break;
3990default:
3991break;
3992}
3993break;
3994default:
3995break;
3996}
3997break;
3998default:
3999break;
4000}
4001break;
4002case 2:
4003switch (this->args[0].kind()) {
4004case Arg::Tmp:
4005switch (this->args[1].kind()) {
4006case Arg::Tmp:
4007if (!args[0].tmp().isGP())
4008OPGEN_RETURN(false);
4009if (!args[1].tmp().isGP())
4010OPGEN_RETURN(false);
4011OPGEN_RETURN(true);
4012break;
4013break;
4014case Arg::Addr:
4015case Arg::Stack:
4016case Arg::CallArg:
4017#if CPU(X86) || CPU(X86_64)
4018if (!args[0].tmp().isGP())
4019OPGEN_RETURN(false);
4020if (!Arg::isValidAddrForm(args[1].offset()))
4021OPGEN_RETURN(false);
4022OPGEN_RETURN(true);
4023#endif
4024break;
4025break;
4026case Arg::Index:
4027#if CPU(X86) || CPU(X86_64)
4028if (!args[0].tmp().isGP())
4029OPGEN_RETURN(false);
4030if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4031OPGEN_RETURN(false);
4032OPGEN_RETURN(true);
4033#endif
4034break;
4035break;
4036default:
4037break;
4038}
4039break;
4040case Arg::Imm:
4041switch (this->args[1].kind()) {
4042case Arg::Addr:
4043case Arg::Stack:
4044case Arg::CallArg:
4045#if CPU(X86) || CPU(X86_64)
4046if (!Arg::isValidImmForm(args[0].value()))
4047OPGEN_RETURN(false);
4048if (!Arg::isValidAddrForm(args[1].offset()))
4049OPGEN_RETURN(false);
4050OPGEN_RETURN(true);
4051#endif
4052break;
4053break;
4054case Arg::Index:
4055#if CPU(X86) || CPU(X86_64)
4056if (!Arg::isValidImmForm(args[0].value()))
4057OPGEN_RETURN(false);
4058if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4059OPGEN_RETURN(false);
4060OPGEN_RETURN(true);
4061#endif
4062break;
4063break;
4064case Arg::Tmp:
4065if (!Arg::isValidImmForm(args[0].value()))
4066OPGEN_RETURN(false);
4067if (!args[1].tmp().isGP())
4068OPGEN_RETURN(false);
4069OPGEN_RETURN(true);
4070break;
4071break;
4072default:
4073break;
4074}
4075break;
4076case Arg::Addr:
4077case Arg::Stack:
4078case Arg::CallArg:
4079switch (this->args[1].kind()) {
4080case Arg::Tmp:
4081#if CPU(X86) || CPU(X86_64)
4082if (!Arg::isValidAddrForm(args[0].offset()))
4083OPGEN_RETURN(false);
4084if (!args[1].tmp().isGP())
4085OPGEN_RETURN(false);
4086OPGEN_RETURN(true);
4087#endif
4088break;
4089break;
4090default:
4091break;
4092}
4093break;
4094case Arg::Index:
4095switch (this->args[1].kind()) {
4096case Arg::Tmp:
4097#if CPU(X86) || CPU(X86_64)
4098if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
4099OPGEN_RETURN(false);
4100if (!args[1].tmp().isGP())
4101OPGEN_RETURN(false);
4102OPGEN_RETURN(true);
4103#endif
4104break;
4105break;
4106default:
4107break;
4108}
4109break;
4110default:
4111break;
4112}
4113break;
4114default:
4115break;
4116}
4117break;
4118case Opcode::Add8:
4119switch (this->args.size()) {
4120case 2:
4121switch (this->args[0].kind()) {
4122case Arg::Imm:
4123switch (this->args[1].kind()) {
4124case Arg::Addr:
4125case Arg::Stack:
4126case Arg::CallArg:
4127#if CPU(X86) || CPU(X86_64)
4128if (!Arg::isValidImmForm(args[0].value()))
4129OPGEN_RETURN(false);
4130if (!Arg::isValidAddrForm(args[1].offset()))
4131OPGEN_RETURN(false);
4132OPGEN_RETURN(true);
4133#endif
4134break;
4135break;
4136case Arg::Index:
4137#if CPU(X86) || CPU(X86_64)
4138if (!Arg::isValidImmForm(args[0].value()))
4139OPGEN_RETURN(false);
4140if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
4141OPGEN_RETURN(false);
4142OPGEN_RETURN(true);
4143#endif
4144break;
4145break;
4146default:
4147break;
4148}
4149break;
4150case Arg::Tmp:
4151switch (this->args[1].kind()) {
4152case Arg::Addr:
4153case Arg::Stack:
4154case Arg::CallArg:
4155#if CPU(X86) || CPU(X86_64)
4156if (!args[0].tmp().isGP())
4157OPGEN_RETURN(false);
4158if (!Arg::isValidAddrForm(args[1].offset()))
4159OPGEN_RETURN(false);
4160OPGEN_RETURN(true);
4161#endif
4162break;
4163break;
4164case Arg::Index:
4165#if CPU(X86) || CPU(X86_64)
4166if (!args[0].tmp().isGP())
4167OPGEN_RETURN(false);
4168if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
4169OPGEN_RETURN(false);
4170OPGEN_RETURN(true);
4171#endif
4172break;
4173break;
4174default:
4175break;
4176}
4177break;
4178default:
4179break;
4180}
4181break;
4182default:
4183break;
4184}
4185break;
4186case Opcode::Add16:
4187switch (this->args.size()) {
4188case 2:
4189switch (this->args[0].kind()) {
4190case Arg::Imm:
4191switch (this->args[1].kind()) {
4192case Arg::Addr:
4193case Arg::Stack:
4194case Arg::CallArg:
4195#if CPU(X86) || CPU(X86_64)
4196if (!Arg::isValidImmForm(args[0].value()))
4197OPGEN_RETURN(false);
4198if (!Arg::isValidAddrForm(args[1].offset()))
4199OPGEN_RETURN(false);
4200OPGEN_RETURN(true);
4201#endif
4202break;
4203break;
4204case Arg::Index:
4205#if CPU(X86) || CPU(X86_64)
4206if (!Arg::isValidImmForm(args[0].value()))
4207OPGEN_RETURN(false);
4208if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
4209OPGEN_RETURN(false);
4210OPGEN_RETURN(true);
4211#endif
4212break;
4213break;
4214default:
4215break;
4216}
4217break;
4218case Arg::Tmp:
4219switch (this->args[1].kind()) {
4220case Arg::Addr:
4221case Arg::Stack:
4222case Arg::CallArg:
4223#if CPU(X86) || CPU(X86_64)
4224if (!args[0].tmp().isGP())
4225OPGEN_RETURN(false);
4226if (!Arg::isValidAddrForm(args[1].offset()))
4227OPGEN_RETURN(false);
4228OPGEN_RETURN(true);
4229#endif
4230break;
4231break;
4232case Arg::Index:
4233#if CPU(X86) || CPU(X86_64)
4234if (!args[0].tmp().isGP())
4235OPGEN_RETURN(false);
4236if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
4237OPGEN_RETURN(false);
4238OPGEN_RETURN(true);
4239#endif
4240break;
4241break;
4242default:
4243break;
4244}
4245break;
4246default:
4247break;
4248}
4249break;
4250default:
4251break;
4252}
4253break;
4254case Opcode::Add64:
4255switch (this->args.size()) {
4256case 2:
4257switch (this->args[0].kind()) {
4258case Arg::Tmp:
4259switch (this->args[1].kind()) {
4260case Arg::Tmp:
4261#if CPU(X86_64) || CPU(ARM64)
4262if (!args[0].tmp().isGP())
4263OPGEN_RETURN(false);
4264if (!args[1].tmp().isGP())
4265OPGEN_RETURN(false);
4266OPGEN_RETURN(true);
4267#endif
4268break;
4269break;
4270case Arg::Addr:
4271case Arg::Stack:
4272case Arg::CallArg:
4273#if CPU(X86_64)
4274if (!args[0].tmp().isGP())
4275OPGEN_RETURN(false);
4276if (!Arg::isValidAddrForm(args[1].offset()))
4277OPGEN_RETURN(false);
4278OPGEN_RETURN(true);
4279#endif
4280break;
4281break;
4282case Arg::Index:
4283#if CPU(X86_64)
4284if (!args[0].tmp().isGP())
4285OPGEN_RETURN(false);
4286if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4287OPGEN_RETURN(false);
4288OPGEN_RETURN(true);
4289#endif
4290break;
4291break;
4292default:
4293break;
4294}
4295break;
4296case Arg::Imm:
4297switch (this->args[1].kind()) {
4298case Arg::Addr:
4299case Arg::Stack:
4300case Arg::CallArg:
4301#if CPU(X86_64)
4302if (!Arg::isValidImmForm(args[0].value()))
4303OPGEN_RETURN(false);
4304if (!Arg::isValidAddrForm(args[1].offset()))
4305OPGEN_RETURN(false);
4306OPGEN_RETURN(true);
4307#endif
4308break;
4309break;
4310case Arg::Index:
4311#if CPU(X86_64)
4312if (!Arg::isValidImmForm(args[0].value()))
4313OPGEN_RETURN(false);
4314if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4315OPGEN_RETURN(false);
4316OPGEN_RETURN(true);
4317#endif
4318break;
4319break;
4320case Arg::Tmp:
4321#if CPU(X86_64) || CPU(ARM64)
4322if (!Arg::isValidImmForm(args[0].value()))
4323OPGEN_RETURN(false);
4324if (!args[1].tmp().isGP())
4325OPGEN_RETURN(false);
4326OPGEN_RETURN(true);
4327#endif
4328break;
4329break;
4330default:
4331break;
4332}
4333break;
4334case Arg::Addr:
4335case Arg::Stack:
4336case Arg::CallArg:
4337switch (this->args[1].kind()) {
4338case Arg::Tmp:
4339#if CPU(X86_64)
4340if (!Arg::isValidAddrForm(args[0].offset()))
4341OPGEN_RETURN(false);
4342if (!args[1].tmp().isGP())
4343OPGEN_RETURN(false);
4344OPGEN_RETURN(true);
4345#endif
4346break;
4347break;
4348default:
4349break;
4350}
4351break;
4352case Arg::Index:
4353switch (this->args[1].kind()) {
4354case Arg::Tmp:
4355#if CPU(X86_64)
4356if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
4357OPGEN_RETURN(false);
4358if (!args[1].tmp().isGP())
4359OPGEN_RETURN(false);
4360OPGEN_RETURN(true);
4361#endif
4362break;
4363break;
4364default:
4365break;
4366}
4367break;
4368default:
4369break;
4370}
4371break;
4372case 3:
4373switch (this->args[0].kind()) {
4374case Arg::Imm:
4375switch (this->args[1].kind()) {
4376case Arg::Tmp:
4377switch (this->args[2].kind()) {
4378case Arg::Tmp:
4379#if CPU(X86_64) || CPU(ARM64)
4380if (!Arg::isValidImmForm(args[0].value()))
4381OPGEN_RETURN(false);
4382if (!args[1].tmp().isGP())
4383OPGEN_RETURN(false);
4384if (!args[2].tmp().isGP())
4385OPGEN_RETURN(false);
4386OPGEN_RETURN(true);
4387#endif
4388break;
4389break;
4390default:
4391break;
4392}
4393break;
4394default:
4395break;
4396}
4397break;
4398case Arg::Tmp:
4399switch (this->args[1].kind()) {
4400case Arg::Tmp:
4401switch (this->args[2].kind()) {
4402case Arg::Tmp:
4403#if CPU(X86_64) || CPU(ARM64)
4404if (!args[0].tmp().isGP())
4405OPGEN_RETURN(false);
4406if (!args[1].tmp().isGP())
4407OPGEN_RETURN(false);
4408if (!args[2].tmp().isGP())
4409OPGEN_RETURN(false);
4410OPGEN_RETURN(true);
4411#endif
4412break;
4413break;
4414default:
4415break;
4416}
4417break;
4418default:
4419break;
4420}
4421break;
4422default:
4423break;
4424}
4425break;
4426default:
4427break;
4428}
4429break;
4430case Opcode::AddDouble:
4431switch (this->args.size()) {
4432case 3:
4433switch (this->args[0].kind()) {
4434case Arg::Tmp:
4435switch (this->args[1].kind()) {
4436case Arg::Tmp:
4437switch (this->args[2].kind()) {
4438case Arg::Tmp:
4439if (!args[0].tmp().isFP())
4440OPGEN_RETURN(false);
4441if (!args[1].tmp().isFP())
4442OPGEN_RETURN(false);
4443if (!args[2].tmp().isFP())
4444OPGEN_RETURN(false);
4445OPGEN_RETURN(true);
4446break;
4447break;
4448default:
4449break;
4450}
4451break;
4452case Arg::Addr:
4453case Arg::Stack:
4454case Arg::CallArg:
4455switch (this->args[2].kind()) {
4456case Arg::Tmp:
4457#if CPU(X86) || CPU(X86_64)
4458if (!args[0].tmp().isFP())
4459OPGEN_RETURN(false);
4460if (!Arg::isValidAddrForm(args[1].offset()))
4461OPGEN_RETURN(false);
4462if (!args[2].tmp().isFP())
4463OPGEN_RETURN(false);
4464OPGEN_RETURN(true);
4465#endif
4466break;
4467break;
4468default:
4469break;
4470}
4471break;
4472default:
4473break;
4474}
4475break;
4476case Arg::Addr:
4477case Arg::Stack:
4478case Arg::CallArg:
4479switch (this->args[1].kind()) {
4480case Arg::Tmp:
4481switch (this->args[2].kind()) {
4482case Arg::Tmp:
4483#if CPU(X86) || CPU(X86_64)
4484if (!Arg::isValidAddrForm(args[0].offset()))
4485OPGEN_RETURN(false);
4486if (!args[1].tmp().isFP())
4487OPGEN_RETURN(false);
4488if (!args[2].tmp().isFP())
4489OPGEN_RETURN(false);
4490OPGEN_RETURN(true);
4491#endif
4492break;
4493break;
4494default:
4495break;
4496}
4497break;
4498default:
4499break;
4500}
4501break;
4502case Arg::Index:
4503switch (this->args[1].kind()) {
4504case Arg::Tmp:
4505switch (this->args[2].kind()) {
4506case Arg::Tmp:
4507#if CPU(X86) || CPU(X86_64)
4508if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
4509OPGEN_RETURN(false);
4510if (!args[1].tmp().isFP())
4511OPGEN_RETURN(false);
4512if (!args[2].tmp().isFP())
4513OPGEN_RETURN(false);
4514OPGEN_RETURN(true);
4515#endif
4516break;
4517break;
4518default:
4519break;
4520}
4521break;
4522default:
4523break;
4524}
4525break;
4526default:
4527break;
4528}
4529break;
4530case 2:
4531switch (this->args[0].kind()) {
4532case Arg::Tmp:
4533switch (this->args[1].kind()) {
4534case Arg::Tmp:
4535#if CPU(X86) || CPU(X86_64)
4536if (!args[0].tmp().isFP())
4537OPGEN_RETURN(false);
4538if (!args[1].tmp().isFP())
4539OPGEN_RETURN(false);
4540OPGEN_RETURN(true);
4541#endif
4542break;
4543break;
4544default:
4545break;
4546}
4547break;
4548case Arg::Addr:
4549case Arg::Stack:
4550case Arg::CallArg:
4551switch (this->args[1].kind()) {
4552case Arg::Tmp:
4553#if CPU(X86) || CPU(X86_64)
4554if (!Arg::isValidAddrForm(args[0].offset()))
4555OPGEN_RETURN(false);
4556if (!args[1].tmp().isFP())
4557OPGEN_RETURN(false);
4558OPGEN_RETURN(true);
4559#endif
4560break;
4561break;
4562default:
4563break;
4564}
4565break;
4566default:
4567break;
4568}
4569break;
4570default:
4571break;
4572}
4573break;
4574case Opcode::AddFloat:
4575switch (this->args.size()) {
4576case 3:
4577switch (this->args[0].kind()) {
4578case Arg::Tmp:
4579switch (this->args[1].kind()) {
4580case Arg::Tmp:
4581switch (this->args[2].kind()) {
4582case Arg::Tmp:
4583if (!args[0].tmp().isFP())
4584OPGEN_RETURN(false);
4585if (!args[1].tmp().isFP())
4586OPGEN_RETURN(false);
4587if (!args[2].tmp().isFP())
4588OPGEN_RETURN(false);
4589OPGEN_RETURN(true);
4590break;
4591break;
4592default:
4593break;
4594}
4595break;
4596case Arg::Addr:
4597case Arg::Stack:
4598case Arg::CallArg:
4599switch (this->args[2].kind()) {
4600case Arg::Tmp:
4601#if CPU(X86) || CPU(X86_64)
4602if (!args[0].tmp().isFP())
4603OPGEN_RETURN(false);
4604if (!Arg::isValidAddrForm(args[1].offset()))
4605OPGEN_RETURN(false);
4606if (!args[2].tmp().isFP())
4607OPGEN_RETURN(false);
4608OPGEN_RETURN(true);
4609#endif
4610break;
4611break;
4612default:
4613break;
4614}
4615break;
4616default:
4617break;
4618}
4619break;
4620case Arg::Addr:
4621case Arg::Stack:
4622case Arg::CallArg:
4623switch (this->args[1].kind()) {
4624case Arg::Tmp:
4625switch (this->args[2].kind()) {
4626case Arg::Tmp:
4627#if CPU(X86) || CPU(X86_64)
4628if (!Arg::isValidAddrForm(args[0].offset()))
4629OPGEN_RETURN(false);
4630if (!args[1].tmp().isFP())
4631OPGEN_RETURN(false);
4632if (!args[2].tmp().isFP())
4633OPGEN_RETURN(false);
4634OPGEN_RETURN(true);
4635#endif
4636break;
4637break;
4638default:
4639break;
4640}
4641break;
4642default:
4643break;
4644}
4645break;
4646case Arg::Index:
4647switch (this->args[1].kind()) {
4648case Arg::Tmp:
4649switch (this->args[2].kind()) {
4650case Arg::Tmp:
4651#if CPU(X86) || CPU(X86_64)
4652if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
4653OPGEN_RETURN(false);
4654if (!args[1].tmp().isFP())
4655OPGEN_RETURN(false);
4656if (!args[2].tmp().isFP())
4657OPGEN_RETURN(false);
4658OPGEN_RETURN(true);
4659#endif
4660break;
4661break;
4662default:
4663break;
4664}
4665break;
4666default:
4667break;
4668}
4669break;
4670default:
4671break;
4672}
4673break;
4674case 2:
4675switch (this->args[0].kind()) {
4676case Arg::Tmp:
4677switch (this->args[1].kind()) {
4678case Arg::Tmp:
4679#if CPU(X86) || CPU(X86_64)
4680if (!args[0].tmp().isFP())
4681OPGEN_RETURN(false);
4682if (!args[1].tmp().isFP())
4683OPGEN_RETURN(false);
4684OPGEN_RETURN(true);
4685#endif
4686break;
4687break;
4688default:
4689break;
4690}
4691break;
4692case Arg::Addr:
4693case Arg::Stack:
4694case Arg::CallArg:
4695switch (this->args[1].kind()) {
4696case Arg::Tmp:
4697#if CPU(X86) || CPU(X86_64)
4698if (!Arg::isValidAddrForm(args[0].offset()))
4699OPGEN_RETURN(false);
4700if (!args[1].tmp().isFP())
4701OPGEN_RETURN(false);
4702OPGEN_RETURN(true);
4703#endif
4704break;
4705break;
4706default:
4707break;
4708}
4709break;
4710default:
4711break;
4712}
4713break;
4714default:
4715break;
4716}
4717break;
4718case Opcode::Sub32:
4719switch (this->args.size()) {
4720case 2:
4721switch (this->args[0].kind()) {
4722case Arg::Tmp:
4723switch (this->args[1].kind()) {
4724case Arg::Tmp:
4725if (!args[0].tmp().isGP())
4726OPGEN_RETURN(false);
4727if (!args[1].tmp().isGP())
4728OPGEN_RETURN(false);
4729OPGEN_RETURN(true);
4730break;
4731break;
4732case Arg::Addr:
4733case Arg::Stack:
4734case Arg::CallArg:
4735#if CPU(X86) || CPU(X86_64)
4736if (!args[0].tmp().isGP())
4737OPGEN_RETURN(false);
4738if (!Arg::isValidAddrForm(args[1].offset()))
4739OPGEN_RETURN(false);
4740OPGEN_RETURN(true);
4741#endif
4742break;
4743break;
4744case Arg::Index:
4745#if CPU(X86) || CPU(X86_64)
4746if (!args[0].tmp().isGP())
4747OPGEN_RETURN(false);
4748if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4749OPGEN_RETURN(false);
4750OPGEN_RETURN(true);
4751#endif
4752break;
4753break;
4754default:
4755break;
4756}
4757break;
4758case Arg::Imm:
4759switch (this->args[1].kind()) {
4760case Arg::Addr:
4761case Arg::Stack:
4762case Arg::CallArg:
4763#if CPU(X86) || CPU(X86_64)
4764if (!Arg::isValidImmForm(args[0].value()))
4765OPGEN_RETURN(false);
4766if (!Arg::isValidAddrForm(args[1].offset()))
4767OPGEN_RETURN(false);
4768OPGEN_RETURN(true);
4769#endif
4770break;
4771break;
4772case Arg::Index:
4773#if CPU(X86) || CPU(X86_64)
4774if (!Arg::isValidImmForm(args[0].value()))
4775OPGEN_RETURN(false);
4776if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
4777OPGEN_RETURN(false);
4778OPGEN_RETURN(true);
4779#endif
4780break;
4781break;
4782case Arg::Tmp:
4783if (!Arg::isValidImmForm(args[0].value()))
4784OPGEN_RETURN(false);
4785if (!args[1].tmp().isGP())
4786OPGEN_RETURN(false);
4787OPGEN_RETURN(true);
4788break;
4789break;
4790default:
4791break;
4792}
4793break;
4794case Arg::Addr:
4795case Arg::Stack:
4796case Arg::CallArg:
4797switch (this->args[1].kind()) {
4798case Arg::Tmp:
4799#if CPU(X86) || CPU(X86_64)
4800if (!Arg::isValidAddrForm(args[0].offset()))
4801OPGEN_RETURN(false);
4802if (!args[1].tmp().isGP())
4803OPGEN_RETURN(false);
4804OPGEN_RETURN(true);
4805#endif
4806break;
4807break;
4808default:
4809break;
4810}
4811break;
4812case Arg::Index:
4813switch (this->args[1].kind()) {
4814case Arg::Tmp:
4815#if CPU(X86) || CPU(X86_64)
4816if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
4817OPGEN_RETURN(false);
4818if (!args[1].tmp().isGP())
4819OPGEN_RETURN(false);
4820OPGEN_RETURN(true);
4821#endif
4822break;
4823break;
4824default:
4825break;
4826}
4827break;
4828default:
4829break;
4830}
4831break;
4832case 3:
4833switch (this->args[0].kind()) {
4834case Arg::Tmp:
4835switch (this->args[1].kind()) {
4836case Arg::Tmp:
4837switch (this->args[2].kind()) {
4838case Arg::Tmp:
4839#if CPU(ARM64)
4840if (!args[0].tmp().isGP())
4841OPGEN_RETURN(false);
4842if (!args[1].tmp().isGP())
4843OPGEN_RETURN(false);
4844if (!args[2].tmp().isGP())
4845OPGEN_RETURN(false);
4846OPGEN_RETURN(true);
4847#endif
4848break;
4849break;
4850default:
4851break;
4852}
4853break;
4854default:
4855break;
4856}
4857break;
4858default:
4859break;
4860}
4861break;
4862default:
4863break;
4864}
4865break;
4866case Opcode::Sub64:
4867switch (this->args.size()) {
4868case 2:
4869switch (this->args[0].kind()) {
4870case Arg::Tmp:
4871switch (this->args[1].kind()) {
4872case Arg::Tmp:
4873#if CPU(X86_64) || CPU(ARM64)
4874if (!args[0].tmp().isGP())
4875OPGEN_RETURN(false);
4876if (!args[1].tmp().isGP())
4877OPGEN_RETURN(false);
4878OPGEN_RETURN(true);
4879#endif
4880break;
4881break;
4882case Arg::Addr:
4883case Arg::Stack:
4884case Arg::CallArg:
4885#if CPU(X86_64)
4886if (!args[0].tmp().isGP())
4887OPGEN_RETURN(false);
4888if (!Arg::isValidAddrForm(args[1].offset()))
4889OPGEN_RETURN(false);
4890OPGEN_RETURN(true);
4891#endif
4892break;
4893break;
4894case Arg::Index:
4895#if CPU(X86_64)
4896if (!args[0].tmp().isGP())
4897OPGEN_RETURN(false);
4898if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4899OPGEN_RETURN(false);
4900OPGEN_RETURN(true);
4901#endif
4902break;
4903break;
4904default:
4905break;
4906}
4907break;
4908case Arg::Imm:
4909switch (this->args[1].kind()) {
4910case Arg::Addr:
4911case Arg::Stack:
4912case Arg::CallArg:
4913#if CPU(X86_64)
4914if (!Arg::isValidImmForm(args[0].value()))
4915OPGEN_RETURN(false);
4916if (!Arg::isValidAddrForm(args[1].offset()))
4917OPGEN_RETURN(false);
4918OPGEN_RETURN(true);
4919#endif
4920break;
4921break;
4922case Arg::Index:
4923#if CPU(X86_64)
4924if (!Arg::isValidImmForm(args[0].value()))
4925OPGEN_RETURN(false);
4926if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
4927OPGEN_RETURN(false);
4928OPGEN_RETURN(true);
4929#endif
4930break;
4931break;
4932case Arg::Tmp:
4933#if CPU(X86_64) || CPU(ARM64)
4934if (!Arg::isValidImmForm(args[0].value()))
4935OPGEN_RETURN(false);
4936if (!args[1].tmp().isGP())
4937OPGEN_RETURN(false);
4938OPGEN_RETURN(true);
4939#endif
4940break;
4941break;
4942default:
4943break;
4944}
4945break;
4946case Arg::Addr:
4947case Arg::Stack:
4948case Arg::CallArg:
4949switch (this->args[1].kind()) {
4950case Arg::Tmp:
4951#if CPU(X86_64)
4952if (!Arg::isValidAddrForm(args[0].offset()))
4953OPGEN_RETURN(false);
4954if (!args[1].tmp().isGP())
4955OPGEN_RETURN(false);
4956OPGEN_RETURN(true);
4957#endif
4958break;
4959break;
4960default:
4961break;
4962}
4963break;
4964case Arg::Index:
4965switch (this->args[1].kind()) {
4966case Arg::Tmp:
4967#if CPU(X86_64)
4968if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
4969OPGEN_RETURN(false);
4970if (!args[1].tmp().isGP())
4971OPGEN_RETURN(false);
4972OPGEN_RETURN(true);
4973#endif
4974break;
4975break;
4976default:
4977break;
4978}
4979break;
4980default:
4981break;
4982}
4983break;
4984case 3:
4985switch (this->args[0].kind()) {
4986case Arg::Tmp:
4987switch (this->args[1].kind()) {
4988case Arg::Tmp:
4989switch (this->args[2].kind()) {
4990case Arg::Tmp:
4991#if CPU(ARM64)
4992if (!args[0].tmp().isGP())
4993OPGEN_RETURN(false);
4994if (!args[1].tmp().isGP())
4995OPGEN_RETURN(false);
4996if (!args[2].tmp().isGP())
4997OPGEN_RETURN(false);
4998OPGEN_RETURN(true);
4999#endif
5000break;
5001break;
5002default:
5003break;
5004}
5005break;
5006default:
5007break;
5008}
5009break;
5010default:
5011break;
5012}
5013break;
5014default:
5015break;
5016}
5017break;
5018case Opcode::SubDouble:
5019switch (this->args.size()) {
5020case 3:
5021switch (this->args[0].kind()) {
5022case Arg::Tmp:
5023switch (this->args[1].kind()) {
5024case Arg::Tmp:
5025switch (this->args[2].kind()) {
5026case Arg::Tmp:
5027#if CPU(ARM64)
5028if (!args[0].tmp().isFP())
5029OPGEN_RETURN(false);
5030if (!args[1].tmp().isFP())
5031OPGEN_RETURN(false);
5032if (!args[2].tmp().isFP())
5033OPGEN_RETURN(false);
5034OPGEN_RETURN(true);
5035#endif
5036break;
5037break;
5038default:
5039break;
5040}
5041break;
5042case Arg::Addr:
5043case Arg::Stack:
5044case Arg::CallArg:
5045switch (this->args[2].kind()) {
5046case Arg::Tmp:
5047#if CPU(X86) || CPU(X86_64)
5048if (!args[0].tmp().isFP())
5049OPGEN_RETURN(false);
5050if (!Arg::isValidAddrForm(args[1].offset()))
5051OPGEN_RETURN(false);
5052if (!args[2].tmp().isFP())
5053OPGEN_RETURN(false);
5054OPGEN_RETURN(true);
5055#endif
5056break;
5057break;
5058default:
5059break;
5060}
5061break;
5062case Arg::Index:
5063switch (this->args[2].kind()) {
5064case Arg::Tmp:
5065#if CPU(X86) || CPU(X86_64)
5066if (!args[0].tmp().isFP())
5067OPGEN_RETURN(false);
5068if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
5069OPGEN_RETURN(false);
5070if (!args[2].tmp().isFP())
5071OPGEN_RETURN(false);
5072OPGEN_RETURN(true);
5073#endif
5074break;
5075break;
5076default:
5077break;
5078}
5079break;
5080default:
5081break;
5082}
5083break;
5084default:
5085break;
5086}
5087break;
5088case 2:
5089switch (this->args[0].kind()) {
5090case Arg::Tmp:
5091switch (this->args[1].kind()) {
5092case Arg::Tmp:
5093#if CPU(X86) || CPU(X86_64)
5094if (!args[0].tmp().isFP())
5095OPGEN_RETURN(false);
5096if (!args[1].tmp().isFP())
5097OPGEN_RETURN(false);
5098OPGEN_RETURN(true);
5099#endif
5100break;
5101break;
5102default:
5103break;
5104}
5105break;
5106case Arg::Addr:
5107case Arg::Stack:
5108case Arg::CallArg:
5109switch (this->args[1].kind()) {
5110case Arg::Tmp:
5111#if CPU(X86) || CPU(X86_64)
5112if (!Arg::isValidAddrForm(args[0].offset()))
5113OPGEN_RETURN(false);
5114if (!args[1].tmp().isFP())
5115OPGEN_RETURN(false);
5116OPGEN_RETURN(true);
5117#endif
5118break;
5119break;
5120default:
5121break;
5122}
5123break;
5124default:
5125break;
5126}
5127break;
5128default:
5129break;
5130}
5131break;
5132case Opcode::SubFloat:
5133switch (this->args.size()) {
5134case 3:
5135switch (this->args[0].kind()) {
5136case Arg::Tmp:
5137switch (this->args[1].kind()) {
5138case Arg::Tmp:
5139switch (this->args[2].kind()) {
5140case Arg::Tmp:
5141#if CPU(ARM64)
5142if (!args[0].tmp().isFP())
5143OPGEN_RETURN(false);
5144if (!args[1].tmp().isFP())
5145OPGEN_RETURN(false);
5146if (!args[2].tmp().isFP())
5147OPGEN_RETURN(false);
5148OPGEN_RETURN(true);
5149#endif
5150break;
5151break;
5152default:
5153break;
5154}
5155break;
5156case Arg::Addr:
5157case Arg::Stack:
5158case Arg::CallArg:
5159switch (this->args[2].kind()) {
5160case Arg::Tmp:
5161#if CPU(X86) || CPU(X86_64)
5162if (!args[0].tmp().isFP())
5163OPGEN_RETURN(false);
5164if (!Arg::isValidAddrForm(args[1].offset()))
5165OPGEN_RETURN(false);
5166if (!args[2].tmp().isFP())
5167OPGEN_RETURN(false);
5168OPGEN_RETURN(true);
5169#endif
5170break;
5171break;
5172default:
5173break;
5174}
5175break;
5176case Arg::Index:
5177switch (this->args[2].kind()) {
5178case Arg::Tmp:
5179#if CPU(X86) || CPU(X86_64)
5180if (!args[0].tmp().isFP())
5181OPGEN_RETURN(false);
5182if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
5183OPGEN_RETURN(false);
5184if (!args[2].tmp().isFP())
5185OPGEN_RETURN(false);
5186OPGEN_RETURN(true);
5187#endif
5188break;
5189break;
5190default:
5191break;
5192}
5193break;
5194default:
5195break;
5196}
5197break;
5198default:
5199break;
5200}
5201break;
5202case 2:
5203switch (this->args[0].kind()) {
5204case Arg::Tmp:
5205switch (this->args[1].kind()) {
5206case Arg::Tmp:
5207#if CPU(X86) || CPU(X86_64)
5208if (!args[0].tmp().isFP())
5209OPGEN_RETURN(false);
5210if (!args[1].tmp().isFP())
5211OPGEN_RETURN(false);
5212OPGEN_RETURN(true);
5213#endif
5214break;
5215break;
5216default:
5217break;
5218}
5219break;
5220case Arg::Addr:
5221case Arg::Stack:
5222case Arg::CallArg:
5223switch (this->args[1].kind()) {
5224case Arg::Tmp:
5225#if CPU(X86) || CPU(X86_64)
5226if (!Arg::isValidAddrForm(args[0].offset()))
5227OPGEN_RETURN(false);
5228if (!args[1].tmp().isFP())
5229OPGEN_RETURN(false);
5230OPGEN_RETURN(true);
5231#endif
5232break;
5233break;
5234default:
5235break;
5236}
5237break;
5238default:
5239break;
5240}
5241break;
5242default:
5243break;
5244}
5245break;
5246case Opcode::Neg32:
5247switch (this->args.size()) {
5248case 1:
5249switch (this->args[0].kind()) {
5250case Arg::Tmp:
5251if (!args[0].tmp().isGP())
5252OPGEN_RETURN(false);
5253OPGEN_RETURN(true);
5254break;
5255break;
5256case Arg::Addr:
5257case Arg::Stack:
5258case Arg::CallArg:
5259#if CPU(X86) || CPU(X86_64)
5260if (!Arg::isValidAddrForm(args[0].offset()))
5261OPGEN_RETURN(false);
5262OPGEN_RETURN(true);
5263#endif
5264break;
5265break;
5266case Arg::Index:
5267#if CPU(X86) || CPU(X86_64)
5268if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
5269OPGEN_RETURN(false);
5270OPGEN_RETURN(true);
5271#endif
5272break;
5273break;
5274default:
5275break;
5276}
5277break;
5278default:
5279break;
5280}
5281break;
5282case Opcode::Neg64:
5283switch (this->args.size()) {
5284case 1:
5285switch (this->args[0].kind()) {
5286case Arg::Tmp:
5287#if CPU(X86_64) || CPU(ARM64)
5288if (!args[0].tmp().isGP())
5289OPGEN_RETURN(false);
5290OPGEN_RETURN(true);
5291#endif
5292break;
5293break;
5294case Arg::Addr:
5295case Arg::Stack:
5296case Arg::CallArg:
5297#if CPU(X86_64)
5298if (!Arg::isValidAddrForm(args[0].offset()))
5299OPGEN_RETURN(false);
5300OPGEN_RETURN(true);
5301#endif
5302break;
5303break;
5304case Arg::Index:
5305#if CPU(X86_64)
5306if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
5307OPGEN_RETURN(false);
5308OPGEN_RETURN(true);
5309#endif
5310break;
5311break;
5312default:
5313break;
5314}
5315break;
5316default:
5317break;
5318}
5319break;
5320case Opcode::NegateDouble:
5321switch (this->args.size()) {
5322case 2:
5323switch (this->args[0].kind()) {
5324case Arg::Tmp:
5325switch (this->args[1].kind()) {
5326case Arg::Tmp:
5327#if CPU(ARM64)
5328if (!args[0].tmp().isFP())
5329OPGEN_RETURN(false);
5330if (!args[1].tmp().isFP())
5331OPGEN_RETURN(false);
5332OPGEN_RETURN(true);
5333#endif
5334break;
5335break;
5336default:
5337break;
5338}
5339break;
5340default:
5341break;
5342}
5343break;
5344default:
5345break;
5346}
5347break;
5348case Opcode::NegateFloat:
5349switch (this->args.size()) {
5350case 2:
5351switch (this->args[0].kind()) {
5352case Arg::Tmp:
5353switch (this->args[1].kind()) {
5354case Arg::Tmp:
5355#if CPU(ARM64)
5356if (!args[0].tmp().isFP())
5357OPGEN_RETURN(false);
5358if (!args[1].tmp().isFP())
5359OPGEN_RETURN(false);
5360OPGEN_RETURN(true);
5361#endif
5362break;
5363break;
5364default:
5365break;
5366}
5367break;
5368default:
5369break;
5370}
5371break;
5372default:
5373break;
5374}
5375break;
5376case Opcode::Mul32:
5377switch (this->args.size()) {
5378case 2:
5379switch (this->args[0].kind()) {
5380case Arg::Tmp:
5381switch (this->args[1].kind()) {
5382case Arg::Tmp:
5383if (!args[0].tmp().isGP())
5384OPGEN_RETURN(false);
5385if (!args[1].tmp().isGP())
5386OPGEN_RETURN(false);
5387OPGEN_RETURN(true);
5388break;
5389break;
5390default:
5391break;
5392}
5393break;
5394case Arg::Addr:
5395case Arg::Stack:
5396case Arg::CallArg:
5397switch (this->args[1].kind()) {
5398case Arg::Tmp:
5399#if CPU(X86) || CPU(X86_64)
5400if (!Arg::isValidAddrForm(args[0].offset()))
5401OPGEN_RETURN(false);
5402if (!args[1].tmp().isGP())
5403OPGEN_RETURN(false);
5404OPGEN_RETURN(true);
5405#endif
5406break;
5407break;
5408default:
5409break;
5410}
5411break;
5412default:
5413break;
5414}
5415break;
5416case 3:
5417switch (this->args[0].kind()) {
5418case Arg::Tmp:
5419switch (this->args[1].kind()) {
5420case Arg::Tmp:
5421switch (this->args[2].kind()) {
5422case Arg::Tmp:
5423if (!args[0].tmp().isGP())
5424OPGEN_RETURN(false);
5425if (!args[1].tmp().isGP())
5426OPGEN_RETURN(false);
5427if (!args[2].tmp().isGP())
5428OPGEN_RETURN(false);
5429OPGEN_RETURN(true);
5430break;
5431break;
5432default:
5433break;
5434}
5435break;
5436case Arg::Addr:
5437case Arg::Stack:
5438case Arg::CallArg:
5439switch (this->args[2].kind()) {
5440case Arg::Tmp:
5441#if CPU(X86) || CPU(X86_64)
5442if (!args[0].tmp().isGP())
5443OPGEN_RETURN(false);
5444if (!Arg::isValidAddrForm(args[1].offset()))
5445OPGEN_RETURN(false);
5446if (!args[2].tmp().isGP())
5447OPGEN_RETURN(false);
5448OPGEN_RETURN(true);
5449#endif
5450break;
5451break;
5452default:
5453break;
5454}
5455break;
5456default:
5457break;
5458}
5459break;
5460case Arg::Addr:
5461case Arg::Stack:
5462case Arg::CallArg:
5463switch (this->args[1].kind()) {
5464case Arg::Tmp:
5465switch (this->args[2].kind()) {
5466case Arg::Tmp:
5467#if CPU(X86) || CPU(X86_64)
5468if (!Arg::isValidAddrForm(args[0].offset()))
5469OPGEN_RETURN(false);
5470if (!args[1].tmp().isGP())
5471OPGEN_RETURN(false);
5472if (!args[2].tmp().isGP())
5473OPGEN_RETURN(false);
5474OPGEN_RETURN(true);
5475#endif
5476break;
5477break;
5478default:
5479break;
5480}
5481break;
5482default:
5483break;
5484}
5485break;
5486case Arg::Imm:
5487switch (this->args[1].kind()) {
5488case Arg::Tmp:
5489switch (this->args[2].kind()) {
5490case Arg::Tmp:
5491#if CPU(X86) || CPU(X86_64)
5492if (!Arg::isValidImmForm(args[0].value()))
5493OPGEN_RETURN(false);
5494if (!args[1].tmp().isGP())
5495OPGEN_RETURN(false);
5496if (!args[2].tmp().isGP())
5497OPGEN_RETURN(false);
5498OPGEN_RETURN(true);
5499#endif
5500break;
5501break;
5502default:
5503break;
5504}
5505break;
5506default:
5507break;
5508}
5509break;
5510default:
5511break;
5512}
5513break;
5514default:
5515break;
5516}
5517break;
5518case Opcode::Mul64:
5519switch (this->args.size()) {
5520case 2:
5521switch (this->args[0].kind()) {
5522case Arg::Tmp:
5523switch (this->args[1].kind()) {
5524case Arg::Tmp:
5525#if CPU(X86_64) || CPU(ARM64)
5526if (!args[0].tmp().isGP())
5527OPGEN_RETURN(false);
5528if (!args[1].tmp().isGP())
5529OPGEN_RETURN(false);
5530OPGEN_RETURN(true);
5531#endif
5532break;
5533break;
5534default:
5535break;
5536}
5537break;
5538default:
5539break;
5540}
5541break;
5542case 3:
5543switch (this->args[0].kind()) {
5544case Arg::Tmp:
5545switch (this->args[1].kind()) {
5546case Arg::Tmp:
5547switch (this->args[2].kind()) {
5548case Arg::Tmp:
5549if (!args[0].tmp().isGP())
5550OPGEN_RETURN(false);
5551if (!args[1].tmp().isGP())
5552OPGEN_RETURN(false);
5553if (!args[2].tmp().isGP())
5554OPGEN_RETURN(false);
5555OPGEN_RETURN(true);
5556break;
5557break;
5558default:
5559break;
5560}
5561break;
5562default:
5563break;
5564}
5565break;
5566default:
5567break;
5568}
5569break;
5570default:
5571break;
5572}
5573break;
5574case Opcode::MultiplyAdd32:
5575switch (this->args.size()) {
5576case 4:
5577switch (this->args[0].kind()) {
5578case Arg::Tmp:
5579switch (this->args[1].kind()) {
5580case Arg::Tmp:
5581switch (this->args[2].kind()) {
5582case Arg::Tmp:
5583switch (this->args[3].kind()) {
5584case Arg::Tmp:
5585#if CPU(ARM64)
5586if (!args[0].tmp().isGP())
5587OPGEN_RETURN(false);
5588if (!args[1].tmp().isGP())
5589OPGEN_RETURN(false);
5590if (!args[2].tmp().isGP())
5591OPGEN_RETURN(false);
5592if (!args[3].tmp().isGP())
5593OPGEN_RETURN(false);
5594OPGEN_RETURN(true);
5595#endif
5596break;
5597break;
5598default:
5599break;
5600}
5601break;
5602default:
5603break;
5604}
5605break;
5606default:
5607break;
5608}
5609break;
5610default:
5611break;
5612}
5613break;
5614default:
5615break;
5616}
5617break;
5618case Opcode::MultiplyAdd64:
5619switch (this->args.size()) {
5620case 4:
5621switch (this->args[0].kind()) {
5622case Arg::Tmp:
5623switch (this->args[1].kind()) {
5624case Arg::Tmp:
5625switch (this->args[2].kind()) {
5626case Arg::Tmp:
5627switch (this->args[3].kind()) {
5628case Arg::Tmp:
5629#if CPU(ARM64)
5630if (!args[0].tmp().isGP())
5631OPGEN_RETURN(false);
5632if (!args[1].tmp().isGP())
5633OPGEN_RETURN(false);
5634if (!args[2].tmp().isGP())
5635OPGEN_RETURN(false);
5636if (!args[3].tmp().isGP())
5637OPGEN_RETURN(false);
5638OPGEN_RETURN(true);
5639#endif
5640break;
5641break;
5642default:
5643break;
5644}
5645break;
5646default:
5647break;
5648}
5649break;
5650default:
5651break;
5652}
5653break;
5654default:
5655break;
5656}
5657break;
5658default:
5659break;
5660}
5661break;
5662case Opcode::MultiplySub32:
5663switch (this->args.size()) {
5664case 4:
5665switch (this->args[0].kind()) {
5666case Arg::Tmp:
5667switch (this->args[1].kind()) {
5668case Arg::Tmp:
5669switch (this->args[2].kind()) {
5670case Arg::Tmp:
5671switch (this->args[3].kind()) {
5672case Arg::Tmp:
5673#if CPU(ARM64)
5674if (!args[0].tmp().isGP())
5675OPGEN_RETURN(false);
5676if (!args[1].tmp().isGP())
5677OPGEN_RETURN(false);
5678if (!args[2].tmp().isGP())
5679OPGEN_RETURN(false);
5680if (!args[3].tmp().isGP())
5681OPGEN_RETURN(false);
5682OPGEN_RETURN(true);
5683#endif
5684break;
5685break;
5686default:
5687break;
5688}
5689break;
5690default:
5691break;
5692}
5693break;
5694default:
5695break;
5696}
5697break;
5698default:
5699break;
5700}
5701break;
5702default:
5703break;
5704}
5705break;
5706case Opcode::MultiplySub64:
5707switch (this->args.size()) {
5708case 4:
5709switch (this->args[0].kind()) {
5710case Arg::Tmp:
5711switch (this->args[1].kind()) {
5712case Arg::Tmp:
5713switch (this->args[2].kind()) {
5714case Arg::Tmp:
5715switch (this->args[3].kind()) {
5716case Arg::Tmp:
5717#if CPU(ARM64)
5718if (!args[0].tmp().isGP())
5719OPGEN_RETURN(false);
5720if (!args[1].tmp().isGP())
5721OPGEN_RETURN(false);
5722if (!args[2].tmp().isGP())
5723OPGEN_RETURN(false);
5724if (!args[3].tmp().isGP())
5725OPGEN_RETURN(false);
5726OPGEN_RETURN(true);
5727#endif
5728break;
5729break;
5730default:
5731break;
5732}
5733break;
5734default:
5735break;
5736}
5737break;
5738default:
5739break;
5740}
5741break;
5742default:
5743break;
5744}
5745break;
5746default:
5747break;
5748}
5749break;
5750case Opcode::MultiplyNeg32:
5751switch (this->args.size()) {
5752case 3:
5753switch (this->args[0].kind()) {
5754case Arg::Tmp:
5755switch (this->args[1].kind()) {
5756case Arg::Tmp:
5757switch (this->args[2].kind()) {
5758case Arg::Tmp:
5759#if CPU(ARM64)
5760if (!args[0].tmp().isGP())
5761OPGEN_RETURN(false);
5762if (!args[1].tmp().isGP())
5763OPGEN_RETURN(false);
5764if (!args[2].tmp().isGP())
5765OPGEN_RETURN(false);
5766OPGEN_RETURN(true);
5767#endif
5768break;
5769break;
5770default:
5771break;
5772}
5773break;
5774default:
5775break;
5776}
5777break;
5778default:
5779break;
5780}
5781break;
5782default:
5783break;
5784}
5785break;
5786case Opcode::MultiplyNeg64:
5787switch (this->args.size()) {
5788case 3:
5789switch (this->args[0].kind()) {
5790case Arg::Tmp:
5791switch (this->args[1].kind()) {
5792case Arg::Tmp:
5793switch (this->args[2].kind()) {
5794case Arg::Tmp:
5795#if CPU(ARM64)
5796if (!args[0].tmp().isGP())
5797OPGEN_RETURN(false);
5798if (!args[1].tmp().isGP())
5799OPGEN_RETURN(false);
5800if (!args[2].tmp().isGP())
5801OPGEN_RETURN(false);
5802OPGEN_RETURN(true);
5803#endif
5804break;
5805break;
5806default:
5807break;
5808}
5809break;
5810default:
5811break;
5812}
5813break;
5814default:
5815break;
5816}
5817break;
5818default:
5819break;
5820}
5821break;
5822case Opcode::Div32:
5823switch (this->args.size()) {
5824case 3:
5825switch (this->args[0].kind()) {
5826case Arg::Tmp:
5827switch (this->args[1].kind()) {
5828case Arg::Tmp:
5829switch (this->args[2].kind()) {
5830case Arg::Tmp:
5831#if CPU(ARM64)
5832if (!args[0].tmp().isGP())
5833OPGEN_RETURN(false);
5834if (!args[1].tmp().isGP())
5835OPGEN_RETURN(false);
5836if (!args[2].tmp().isGP())
5837OPGEN_RETURN(false);
5838OPGEN_RETURN(true);
5839#endif
5840break;
5841break;
5842default:
5843break;
5844}
5845break;
5846default:
5847break;
5848}
5849break;
5850default:
5851break;
5852}
5853break;
5854default:
5855break;
5856}
5857break;
5858case Opcode::UDiv32:
5859switch (this->args.size()) {
5860case 3:
5861switch (this->args[0].kind()) {
5862case Arg::Tmp:
5863switch (this->args[1].kind()) {
5864case Arg::Tmp:
5865switch (this->args[2].kind()) {
5866case Arg::Tmp:
5867#if CPU(ARM64)
5868if (!args[0].tmp().isGP())
5869OPGEN_RETURN(false);
5870if (!args[1].tmp().isGP())
5871OPGEN_RETURN(false);
5872if (!args[2].tmp().isGP())
5873OPGEN_RETURN(false);
5874OPGEN_RETURN(true);
5875#endif
5876break;
5877break;
5878default:
5879break;
5880}
5881break;
5882default:
5883break;
5884}
5885break;
5886default:
5887break;
5888}
5889break;
5890default:
5891break;
5892}
5893break;
5894case Opcode::Div64:
5895switch (this->args.size()) {
5896case 3:
5897switch (this->args[0].kind()) {
5898case Arg::Tmp:
5899switch (this->args[1].kind()) {
5900case Arg::Tmp:
5901switch (this->args[2].kind()) {
5902case Arg::Tmp:
5903#if CPU(ARM64)
5904if (!args[0].tmp().isGP())
5905OPGEN_RETURN(false);
5906if (!args[1].tmp().isGP())
5907OPGEN_RETURN(false);
5908if (!args[2].tmp().isGP())
5909OPGEN_RETURN(false);
5910OPGEN_RETURN(true);
5911#endif
5912break;
5913break;
5914default:
5915break;
5916}
5917break;
5918default:
5919break;
5920}
5921break;
5922default:
5923break;
5924}
5925break;
5926default:
5927break;
5928}
5929break;
5930case Opcode::UDiv64:
5931switch (this->args.size()) {
5932case 3:
5933switch (this->args[0].kind()) {
5934case Arg::Tmp:
5935switch (this->args[1].kind()) {
5936case Arg::Tmp:
5937switch (this->args[2].kind()) {
5938case Arg::Tmp:
5939#if CPU(ARM64)
5940if (!args[0].tmp().isGP())
5941OPGEN_RETURN(false);
5942if (!args[1].tmp().isGP())
5943OPGEN_RETURN(false);
5944if (!args[2].tmp().isGP())
5945OPGEN_RETURN(false);
5946OPGEN_RETURN(true);
5947#endif
5948break;
5949break;
5950default:
5951break;
5952}
5953break;
5954default:
5955break;
5956}
5957break;
5958default:
5959break;
5960}
5961break;
5962default:
5963break;
5964}
5965break;
5966case Opcode::MulDouble:
5967switch (this->args.size()) {
5968case 3:
5969switch (this->args[0].kind()) {
5970case Arg::Tmp:
5971switch (this->args[1].kind()) {
5972case Arg::Tmp:
5973switch (this->args[2].kind()) {
5974case Arg::Tmp:
5975if (!args[0].tmp().isFP())
5976OPGEN_RETURN(false);
5977if (!args[1].tmp().isFP())
5978OPGEN_RETURN(false);
5979if (!args[2].tmp().isFP())
5980OPGEN_RETURN(false);
5981OPGEN_RETURN(true);
5982break;
5983break;
5984default:
5985break;
5986}
5987break;
5988case Arg::Addr:
5989case Arg::Stack:
5990case Arg::CallArg:
5991switch (this->args[2].kind()) {
5992case Arg::Tmp:
5993#if CPU(X86) || CPU(X86_64)
5994if (!args[0].tmp().isFP())
5995OPGEN_RETURN(false);
5996if (!Arg::isValidAddrForm(args[1].offset()))
5997OPGEN_RETURN(false);
5998if (!args[2].tmp().isFP())
5999OPGEN_RETURN(false);
6000OPGEN_RETURN(true);
6001#endif
6002break;
6003break;
6004default:
6005break;
6006}
6007break;
6008default:
6009break;
6010}
6011break;
6012case Arg::Addr:
6013case Arg::Stack:
6014case Arg::CallArg:
6015switch (this->args[1].kind()) {
6016case Arg::Tmp:
6017switch (this->args[2].kind()) {
6018case Arg::Tmp:
6019#if CPU(X86) || CPU(X86_64)
6020if (!Arg::isValidAddrForm(args[0].offset()))
6021OPGEN_RETURN(false);
6022if (!args[1].tmp().isFP())
6023OPGEN_RETURN(false);
6024if (!args[2].tmp().isFP())
6025OPGEN_RETURN(false);
6026OPGEN_RETURN(true);
6027#endif
6028break;
6029break;
6030default:
6031break;
6032}
6033break;
6034default:
6035break;
6036}
6037break;
6038case Arg::Index:
6039switch (this->args[1].kind()) {
6040case Arg::Tmp:
6041switch (this->args[2].kind()) {
6042case Arg::Tmp:
6043#if CPU(X86) || CPU(X86_64)
6044if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
6045OPGEN_RETURN(false);
6046if (!args[1].tmp().isFP())
6047OPGEN_RETURN(false);
6048if (!args[2].tmp().isFP())
6049OPGEN_RETURN(false);
6050OPGEN_RETURN(true);
6051#endif
6052break;
6053break;
6054default:
6055break;
6056}
6057break;
6058default:
6059break;
6060}
6061break;
6062default:
6063break;
6064}
6065break;
6066case 2:
6067switch (this->args[0].kind()) {
6068case Arg::Tmp:
6069switch (this->args[1].kind()) {
6070case Arg::Tmp:
6071#if CPU(X86) || CPU(X86_64)
6072if (!args[0].tmp().isFP())
6073OPGEN_RETURN(false);
6074if (!args[1].tmp().isFP())
6075OPGEN_RETURN(false);
6076OPGEN_RETURN(true);
6077#endif
6078break;
6079break;
6080default:
6081break;
6082}
6083break;
6084case Arg::Addr:
6085case Arg::Stack:
6086case Arg::CallArg:
6087switch (this->args[1].kind()) {
6088case Arg::Tmp:
6089#if CPU(X86) || CPU(X86_64)
6090if (!Arg::isValidAddrForm(args[0].offset()))
6091OPGEN_RETURN(false);
6092if (!args[1].tmp().isFP())
6093OPGEN_RETURN(false);
6094OPGEN_RETURN(true);
6095#endif
6096break;
6097break;
6098default:
6099break;
6100}
6101break;
6102default:
6103break;
6104}
6105break;
6106default:
6107break;
6108}
6109break;
6110case Opcode::MulFloat:
6111switch (this->args.size()) {
6112case 3:
6113switch (this->args[0].kind()) {
6114case Arg::Tmp:
6115switch (this->args[1].kind()) {
6116case Arg::Tmp:
6117switch (this->args[2].kind()) {
6118case Arg::Tmp:
6119if (!args[0].tmp().isFP())
6120OPGEN_RETURN(false);
6121if (!args[1].tmp().isFP())
6122OPGEN_RETURN(false);
6123if (!args[2].tmp().isFP())
6124OPGEN_RETURN(false);
6125OPGEN_RETURN(true);
6126break;
6127break;
6128default:
6129break;
6130}
6131break;
6132case Arg::Addr:
6133case Arg::Stack:
6134case Arg::CallArg:
6135switch (this->args[2].kind()) {
6136case Arg::Tmp:
6137#if CPU(X86) || CPU(X86_64)
6138if (!args[0].tmp().isFP())
6139OPGEN_RETURN(false);
6140if (!Arg::isValidAddrForm(args[1].offset()))
6141OPGEN_RETURN(false);
6142if (!args[2].tmp().isFP())
6143OPGEN_RETURN(false);
6144OPGEN_RETURN(true);
6145#endif
6146break;
6147break;
6148default:
6149break;
6150}
6151break;
6152default:
6153break;
6154}
6155break;
6156case Arg::Addr:
6157case Arg::Stack:
6158case Arg::CallArg:
6159switch (this->args[1].kind()) {
6160case Arg::Tmp:
6161switch (this->args[2].kind()) {
6162case Arg::Tmp:
6163#if CPU(X86) || CPU(X86_64)
6164if (!Arg::isValidAddrForm(args[0].offset()))
6165OPGEN_RETURN(false);
6166if (!args[1].tmp().isFP())
6167OPGEN_RETURN(false);
6168if (!args[2].tmp().isFP())
6169OPGEN_RETURN(false);
6170OPGEN_RETURN(true);
6171#endif
6172break;
6173break;
6174default:
6175break;
6176}
6177break;
6178default:
6179break;
6180}
6181break;
6182case Arg::Index:
6183switch (this->args[1].kind()) {
6184case Arg::Tmp:
6185switch (this->args[2].kind()) {
6186case Arg::Tmp:
6187#if CPU(X86) || CPU(X86_64)
6188if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
6189OPGEN_RETURN(false);
6190if (!args[1].tmp().isFP())
6191OPGEN_RETURN(false);
6192if (!args[2].tmp().isFP())
6193OPGEN_RETURN(false);
6194OPGEN_RETURN(true);
6195#endif
6196break;
6197break;
6198default:
6199break;
6200}
6201break;
6202default:
6203break;
6204}
6205break;
6206default:
6207break;
6208}
6209break;
6210case 2:
6211switch (this->args[0].kind()) {
6212case Arg::Tmp:
6213switch (this->args[1].kind()) {
6214case Arg::Tmp:
6215#if CPU(X86) || CPU(X86_64)
6216if (!args[0].tmp().isFP())
6217OPGEN_RETURN(false);
6218if (!args[1].tmp().isFP())
6219OPGEN_RETURN(false);
6220OPGEN_RETURN(true);
6221#endif
6222break;
6223break;
6224default:
6225break;
6226}
6227break;
6228case Arg::Addr:
6229case Arg::Stack:
6230case Arg::CallArg:
6231switch (this->args[1].kind()) {
6232case Arg::Tmp:
6233#if CPU(X86) || CPU(X86_64)
6234if (!Arg::isValidAddrForm(args[0].offset()))
6235OPGEN_RETURN(false);
6236if (!args[1].tmp().isFP())
6237OPGEN_RETURN(false);
6238OPGEN_RETURN(true);
6239#endif
6240break;
6241break;
6242default:
6243break;
6244}
6245break;
6246default:
6247break;
6248}
6249break;
6250default:
6251break;
6252}
6253break;
6254case Opcode::DivDouble:
6255switch (this->args.size()) {
6256case 3:
6257switch (this->args[0].kind()) {
6258case Arg::Tmp:
6259switch (this->args[1].kind()) {
6260case Arg::Tmp:
6261switch (this->args[2].kind()) {
6262case Arg::Tmp:
6263#if CPU(ARM64)
6264if (!args[0].tmp().isFP())
6265OPGEN_RETURN(false);
6266if (!args[1].tmp().isFP())
6267OPGEN_RETURN(false);
6268if (!args[2].tmp().isFP())
6269OPGEN_RETURN(false);
6270OPGEN_RETURN(true);
6271#endif
6272break;
6273break;
6274default:
6275break;
6276}
6277break;
6278default:
6279break;
6280}
6281break;
6282default:
6283break;
6284}
6285break;
6286case 2:
6287switch (this->args[0].kind()) {
6288case Arg::Tmp:
6289switch (this->args[1].kind()) {
6290case Arg::Tmp:
6291#if CPU(X86) || CPU(X86_64)
6292if (!args[0].tmp().isFP())
6293OPGEN_RETURN(false);
6294if (!args[1].tmp().isFP())
6295OPGEN_RETURN(false);
6296OPGEN_RETURN(true);
6297#endif
6298break;
6299break;
6300default:
6301break;
6302}
6303break;
6304case Arg::Addr:
6305case Arg::Stack:
6306case Arg::CallArg:
6307switch (this->args[1].kind()) {
6308case Arg::Tmp:
6309#if CPU(X86) || CPU(X86_64)
6310if (!Arg::isValidAddrForm(args[0].offset()))
6311OPGEN_RETURN(false);
6312if (!args[1].tmp().isFP())
6313OPGEN_RETURN(false);
6314OPGEN_RETURN(true);
6315#endif
6316break;
6317break;
6318default:
6319break;
6320}
6321break;
6322default:
6323break;
6324}
6325break;
6326default:
6327break;
6328}
6329break;
6330case Opcode::DivFloat:
6331switch (this->args.size()) {
6332case 3:
6333switch (this->args[0].kind()) {
6334case Arg::Tmp:
6335switch (this->args[1].kind()) {
6336case Arg::Tmp:
6337switch (this->args[2].kind()) {
6338case Arg::Tmp:
6339#if CPU(ARM64)
6340if (!args[0].tmp().isFP())
6341OPGEN_RETURN(false);
6342if (!args[1].tmp().isFP())
6343OPGEN_RETURN(false);
6344if (!args[2].tmp().isFP())
6345OPGEN_RETURN(false);
6346OPGEN_RETURN(true);
6347#endif
6348break;
6349break;
6350default:
6351break;
6352}
6353break;
6354default:
6355break;
6356}
6357break;
6358default:
6359break;
6360}
6361break;
6362case 2:
6363switch (this->args[0].kind()) {
6364case Arg::Tmp:
6365switch (this->args[1].kind()) {
6366case Arg::Tmp:
6367#if CPU(X86) || CPU(X86_64)
6368if (!args[0].tmp().isFP())
6369OPGEN_RETURN(false);
6370if (!args[1].tmp().isFP())
6371OPGEN_RETURN(false);
6372OPGEN_RETURN(true);
6373#endif
6374break;
6375break;
6376default:
6377break;
6378}
6379break;
6380case Arg::Addr:
6381case Arg::Stack:
6382case Arg::CallArg:
6383switch (this->args[1].kind()) {
6384case Arg::Tmp:
6385#if CPU(X86) || CPU(X86_64)
6386if (!Arg::isValidAddrForm(args[0].offset()))
6387OPGEN_RETURN(false);
6388if (!args[1].tmp().isFP())
6389OPGEN_RETURN(false);
6390OPGEN_RETURN(true);
6391#endif
6392break;
6393break;
6394default:
6395break;
6396}
6397break;
6398default:
6399break;
6400}
6401break;
6402default:
6403break;
6404}
6405break;
6406case Opcode::X86ConvertToDoubleWord32:
6407switch (this->args.size()) {
6408case 2:
6409switch (this->args[0].kind()) {
6410case Arg::Tmp:
6411switch (this->args[1].kind()) {
6412case Arg::Tmp:
6413#if CPU(X86) || CPU(X86_64)
6414if (!args[0].tmp().isGP())
6415OPGEN_RETURN(false);
6416if (!args[1].tmp().isGP())
6417OPGEN_RETURN(false);
6418if (!isX86ConvertToDoubleWord32Valid(*this))
6419OPGEN_RETURN(false);
6420OPGEN_RETURN(true);
6421#endif
6422break;
6423break;
6424default:
6425break;
6426}
6427break;
6428default:
6429break;
6430}
6431break;
6432default:
6433break;
6434}
6435break;
6436case Opcode::X86ConvertToQuadWord64:
6437switch (this->args.size()) {
6438case 2:
6439switch (this->args[0].kind()) {
6440case Arg::Tmp:
6441switch (this->args[1].kind()) {
6442case Arg::Tmp:
6443#if CPU(X86_64)
6444if (!args[0].tmp().isGP())
6445OPGEN_RETURN(false);
6446if (!args[1].tmp().isGP())
6447OPGEN_RETURN(false);
6448if (!isX86ConvertToQuadWord64Valid(*this))
6449OPGEN_RETURN(false);
6450OPGEN_RETURN(true);
6451#endif
6452break;
6453break;
6454default:
6455break;
6456}
6457break;
6458default:
6459break;
6460}
6461break;
6462default:
6463break;
6464}
6465break;
6466case Opcode::X86Div32:
6467switch (this->args.size()) {
6468case 3:
6469switch (this->args[0].kind()) {
6470case Arg::Tmp:
6471switch (this->args[1].kind()) {
6472case Arg::Tmp:
6473switch (this->args[2].kind()) {
6474case Arg::Tmp:
6475#if CPU(X86) || CPU(X86_64)
6476if (!args[0].tmp().isGP())
6477OPGEN_RETURN(false);
6478if (!args[1].tmp().isGP())
6479OPGEN_RETURN(false);
6480if (!args[2].tmp().isGP())
6481OPGEN_RETURN(false);
6482if (!isX86Div32Valid(*this))
6483OPGEN_RETURN(false);
6484OPGEN_RETURN(true);
6485#endif
6486break;
6487break;
6488default:
6489break;
6490}
6491break;
6492default:
6493break;
6494}
6495break;
6496default:
6497break;
6498}
6499break;
6500default:
6501break;
6502}
6503break;
6504case Opcode::X86UDiv32:
6505switch (this->args.size()) {
6506case 3:
6507switch (this->args[0].kind()) {
6508case Arg::Tmp:
6509switch (this->args[1].kind()) {
6510case Arg::Tmp:
6511switch (this->args[2].kind()) {
6512case Arg::Tmp:
6513#if CPU(X86) || CPU(X86_64)
6514if (!args[0].tmp().isGP())
6515OPGEN_RETURN(false);
6516if (!args[1].tmp().isGP())
6517OPGEN_RETURN(false);
6518if (!args[2].tmp().isGP())
6519OPGEN_RETURN(false);
6520if (!isX86UDiv32Valid(*this))
6521OPGEN_RETURN(false);
6522OPGEN_RETURN(true);
6523#endif
6524break;
6525break;
6526default:
6527break;
6528}
6529break;
6530default:
6531break;
6532}
6533break;
6534default:
6535break;
6536}
6537break;
6538default:
6539break;
6540}
6541break;
6542case Opcode::X86Div64:
6543switch (this->args.size()) {
6544case 3:
6545switch (this->args[0].kind()) {
6546case Arg::Tmp:
6547switch (this->args[1].kind()) {
6548case Arg::Tmp:
6549switch (this->args[2].kind()) {
6550case Arg::Tmp:
6551#if CPU(X86_64)
6552if (!args[0].tmp().isGP())
6553OPGEN_RETURN(false);
6554if (!args[1].tmp().isGP())
6555OPGEN_RETURN(false);
6556if (!args[2].tmp().isGP())
6557OPGEN_RETURN(false);
6558if (!isX86Div64Valid(*this))
6559OPGEN_RETURN(false);
6560OPGEN_RETURN(true);
6561#endif
6562break;
6563break;
6564default:
6565break;
6566}
6567break;
6568default:
6569break;
6570}
6571break;
6572default:
6573break;
6574}
6575break;
6576default:
6577break;
6578}
6579break;
6580case Opcode::X86UDiv64:
6581switch (this->args.size()) {
6582case 3:
6583switch (this->args[0].kind()) {
6584case Arg::Tmp:
6585switch (this->args[1].kind()) {
6586case Arg::Tmp:
6587switch (this->args[2].kind()) {
6588case Arg::Tmp:
6589#if CPU(X86_64)
6590if (!args[0].tmp().isGP())
6591OPGEN_RETURN(false);
6592if (!args[1].tmp().isGP())
6593OPGEN_RETURN(false);
6594if (!args[2].tmp().isGP())
6595OPGEN_RETURN(false);
6596if (!isX86UDiv64Valid(*this))
6597OPGEN_RETURN(false);
6598OPGEN_RETURN(true);
6599#endif
6600break;
6601break;
6602default:
6603break;
6604}
6605break;
6606default:
6607break;
6608}
6609break;
6610default:
6611break;
6612}
6613break;
6614default:
6615break;
6616}
6617break;
6618case Opcode::Lea32:
6619switch (this->args.size()) {
6620case 2:
6621switch (this->args[0].kind()) {
6622case Arg::Addr:
6623case Arg::Stack:
6624case Arg::CallArg:
6625switch (this->args[1].kind()) {
6626case Arg::Tmp:
6627if (args[0].isStack() && args[0].stackSlot()->isSpill())
6628OPGEN_RETURN(false);
6629if (!Arg::isValidAddrForm(args[0].offset()))
6630OPGEN_RETURN(false);
6631if (!args[1].tmp().isGP())
6632OPGEN_RETURN(false);
6633OPGEN_RETURN(true);
6634break;
6635break;
6636default:
6637break;
6638}
6639break;
6640case Arg::Index:
6641switch (this->args[1].kind()) {
6642case Arg::Tmp:
6643#if CPU(X86) || CPU(X86_64)
6644if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
6645OPGEN_RETURN(false);
6646if (!args[1].tmp().isGP())
6647OPGEN_RETURN(false);
6648OPGEN_RETURN(true);
6649#endif
6650break;
6651break;
6652default:
6653break;
6654}
6655break;
6656default:
6657break;
6658}
6659break;
6660default:
6661break;
6662}
6663break;
6664case Opcode::Lea64:
6665switch (this->args.size()) {
6666case 2:
6667switch (this->args[0].kind()) {
6668case Arg::Addr:
6669case Arg::Stack:
6670case Arg::CallArg:
6671switch (this->args[1].kind()) {
6672case Arg::Tmp:
6673if (args[0].isStack() && args[0].stackSlot()->isSpill())
6674OPGEN_RETURN(false);
6675if (!Arg::isValidAddrForm(args[0].offset()))
6676OPGEN_RETURN(false);
6677if (!args[1].tmp().isGP())
6678OPGEN_RETURN(false);
6679OPGEN_RETURN(true);
6680break;
6681break;
6682default:
6683break;
6684}
6685break;
6686case Arg::Index:
6687switch (this->args[1].kind()) {
6688case Arg::Tmp:
6689#if CPU(X86) || CPU(X86_64)
6690if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
6691OPGEN_RETURN(false);
6692if (!args[1].tmp().isGP())
6693OPGEN_RETURN(false);
6694OPGEN_RETURN(true);
6695#endif
6696break;
6697break;
6698default:
6699break;
6700}
6701break;
6702default:
6703break;
6704}
6705break;
6706default:
6707break;
6708}
6709break;
6710case Opcode::And32:
6711switch (this->args.size()) {
6712case 3:
6713switch (this->args[0].kind()) {
6714case Arg::Tmp:
6715switch (this->args[1].kind()) {
6716case Arg::Tmp:
6717switch (this->args[2].kind()) {
6718case Arg::Tmp:
6719if (!args[0].tmp().isGP())
6720OPGEN_RETURN(false);
6721if (!args[1].tmp().isGP())
6722OPGEN_RETURN(false);
6723if (!args[2].tmp().isGP())
6724OPGEN_RETURN(false);
6725OPGEN_RETURN(true);
6726break;
6727break;
6728default:
6729break;
6730}
6731break;
6732case Arg::Addr:
6733case Arg::Stack:
6734case Arg::CallArg:
6735switch (this->args[2].kind()) {
6736case Arg::Tmp:
6737#if CPU(X86) || CPU(X86_64)
6738if (!args[0].tmp().isGP())
6739OPGEN_RETURN(false);
6740if (!Arg::isValidAddrForm(args[1].offset()))
6741OPGEN_RETURN(false);
6742if (!args[2].tmp().isGP())
6743OPGEN_RETURN(false);
6744OPGEN_RETURN(true);
6745#endif
6746break;
6747break;
6748default:
6749break;
6750}
6751break;
6752default:
6753break;
6754}
6755break;
6756case Arg::BitImm:
6757switch (this->args[1].kind()) {
6758case Arg::Tmp:
6759switch (this->args[2].kind()) {
6760case Arg::Tmp:
6761#if CPU(ARM64)
6762if (!Arg::isValidBitImmForm(args[0].value()))
6763OPGEN_RETURN(false);
6764if (!args[1].tmp().isGP())
6765OPGEN_RETURN(false);
6766if (!args[2].tmp().isGP())
6767OPGEN_RETURN(false);
6768OPGEN_RETURN(true);
6769#endif
6770break;
6771break;
6772default:
6773break;
6774}
6775break;
6776default:
6777break;
6778}
6779break;
6780case Arg::Addr:
6781case Arg::Stack:
6782case Arg::CallArg:
6783switch (this->args[1].kind()) {
6784case Arg::Tmp:
6785switch (this->args[2].kind()) {
6786case Arg::Tmp:
6787#if CPU(X86) || CPU(X86_64)
6788if (!Arg::isValidAddrForm(args[0].offset()))
6789OPGEN_RETURN(false);
6790if (!args[1].tmp().isGP())
6791OPGEN_RETURN(false);
6792if (!args[2].tmp().isGP())
6793OPGEN_RETURN(false);
6794OPGEN_RETURN(true);
6795#endif
6796break;
6797break;
6798default:
6799break;
6800}
6801break;
6802default:
6803break;
6804}
6805break;
6806default:
6807break;
6808}
6809break;
6810case 2:
6811switch (this->args[0].kind()) {
6812case Arg::Tmp:
6813switch (this->args[1].kind()) {
6814case Arg::Tmp:
6815if (!args[0].tmp().isGP())
6816OPGEN_RETURN(false);
6817if (!args[1].tmp().isGP())
6818OPGEN_RETURN(false);
6819OPGEN_RETURN(true);
6820break;
6821break;
6822case Arg::Addr:
6823case Arg::Stack:
6824case Arg::CallArg:
6825#if CPU(X86) || CPU(X86_64)
6826if (!args[0].tmp().isGP())
6827OPGEN_RETURN(false);
6828if (!Arg::isValidAddrForm(args[1].offset()))
6829OPGEN_RETURN(false);
6830OPGEN_RETURN(true);
6831#endif
6832break;
6833break;
6834case Arg::Index:
6835#if CPU(X86) || CPU(X86_64)
6836if (!args[0].tmp().isGP())
6837OPGEN_RETURN(false);
6838if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
6839OPGEN_RETURN(false);
6840OPGEN_RETURN(true);
6841#endif
6842break;
6843break;
6844default:
6845break;
6846}
6847break;
6848case Arg::Imm:
6849switch (this->args[1].kind()) {
6850case Arg::Tmp:
6851#if CPU(X86) || CPU(X86_64)
6852if (!Arg::isValidImmForm(args[0].value()))
6853OPGEN_RETURN(false);
6854if (!args[1].tmp().isGP())
6855OPGEN_RETURN(false);
6856OPGEN_RETURN(true);
6857#endif
6858break;
6859break;
6860case Arg::Addr:
6861case Arg::Stack:
6862case Arg::CallArg:
6863#if CPU(X86) || CPU(X86_64)
6864if (!Arg::isValidImmForm(args[0].value()))
6865OPGEN_RETURN(false);
6866if (!Arg::isValidAddrForm(args[1].offset()))
6867OPGEN_RETURN(false);
6868OPGEN_RETURN(true);
6869#endif
6870break;
6871break;
6872case Arg::Index:
6873#if CPU(X86) || CPU(X86_64)
6874if (!Arg::isValidImmForm(args[0].value()))
6875OPGEN_RETURN(false);
6876if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
6877OPGEN_RETURN(false);
6878OPGEN_RETURN(true);
6879#endif
6880break;
6881break;
6882default:
6883break;
6884}
6885break;
6886case Arg::Addr:
6887case Arg::Stack:
6888case Arg::CallArg:
6889switch (this->args[1].kind()) {
6890case Arg::Tmp:
6891#if CPU(X86) || CPU(X86_64)
6892if (!Arg::isValidAddrForm(args[0].offset()))
6893OPGEN_RETURN(false);
6894if (!args[1].tmp().isGP())
6895OPGEN_RETURN(false);
6896OPGEN_RETURN(true);
6897#endif
6898break;
6899break;
6900default:
6901break;
6902}
6903break;
6904case Arg::Index:
6905switch (this->args[1].kind()) {
6906case Arg::Tmp:
6907#if CPU(X86) || CPU(X86_64)
6908if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
6909OPGEN_RETURN(false);
6910if (!args[1].tmp().isGP())
6911OPGEN_RETURN(false);
6912OPGEN_RETURN(true);
6913#endif
6914break;
6915break;
6916default:
6917break;
6918}
6919break;
6920default:
6921break;
6922}
6923break;
6924default:
6925break;
6926}
6927break;
6928case Opcode::And64:
6929switch (this->args.size()) {
6930case 3:
6931switch (this->args[0].kind()) {
6932case Arg::Tmp:
6933switch (this->args[1].kind()) {
6934case Arg::Tmp:
6935switch (this->args[2].kind()) {
6936case Arg::Tmp:
6937#if CPU(X86_64) || CPU(ARM64)
6938if (!args[0].tmp().isGP())
6939OPGEN_RETURN(false);
6940if (!args[1].tmp().isGP())
6941OPGEN_RETURN(false);
6942if (!args[2].tmp().isGP())
6943OPGEN_RETURN(false);
6944OPGEN_RETURN(true);
6945#endif
6946break;
6947break;
6948default:
6949break;
6950}
6951break;
6952default:
6953break;
6954}
6955break;
6956#if USE(JSVALUE64)
6957case Arg::BitImm64:
6958switch (this->args[1].kind()) {
6959case Arg::Tmp:
6960switch (this->args[2].kind()) {
6961case Arg::Tmp:
6962#if CPU(ARM64)
6963if (!Arg::isValidBitImm64Form(args[0].value()))
6964OPGEN_RETURN(false);
6965if (!args[1].tmp().isGP())
6966OPGEN_RETURN(false);
6967if (!args[2].tmp().isGP())
6968OPGEN_RETURN(false);
6969OPGEN_RETURN(true);
6970#endif
6971break;
6972break;
6973default:
6974break;
6975}
6976break;
6977default:
6978break;
6979}
6980break;
6981#endif // USE(JSVALUE64)
6982default:
6983break;
6984}
6985break;
6986case 2:
6987switch (this->args[0].kind()) {
6988case Arg::Tmp:
6989switch (this->args[1].kind()) {
6990case Arg::Tmp:
6991#if CPU(X86_64)
6992if (!args[0].tmp().isGP())
6993OPGEN_RETURN(false);
6994if (!args[1].tmp().isGP())
6995OPGEN_RETURN(false);
6996OPGEN_RETURN(true);
6997#endif
6998break;
6999break;
7000case Arg::Addr:
7001case Arg::Stack:
7002case Arg::CallArg:
7003#if CPU(X86_64)
7004if (!args[0].tmp().isGP())
7005OPGEN_RETURN(false);
7006if (!Arg::isValidAddrForm(args[1].offset()))
7007OPGEN_RETURN(false);
7008OPGEN_RETURN(true);
7009#endif
7010break;
7011break;
7012case Arg::Index:
7013#if CPU(X86_64)
7014if (!args[0].tmp().isGP())
7015OPGEN_RETURN(false);
7016if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
7017OPGEN_RETURN(false);
7018OPGEN_RETURN(true);
7019#endif
7020break;
7021break;
7022default:
7023break;
7024}
7025break;
7026case Arg::Imm:
7027switch (this->args[1].kind()) {
7028case Arg::Tmp:
7029#if CPU(X86_64)
7030if (!Arg::isValidImmForm(args[0].value()))
7031OPGEN_RETURN(false);
7032if (!args[1].tmp().isGP())
7033OPGEN_RETURN(false);
7034OPGEN_RETURN(true);
7035#endif
7036break;
7037break;
7038case Arg::Addr:
7039case Arg::Stack:
7040case Arg::CallArg:
7041#if CPU(X86_64)
7042if (!Arg::isValidImmForm(args[0].value()))
7043OPGEN_RETURN(false);
7044if (!Arg::isValidAddrForm(args[1].offset()))
7045OPGEN_RETURN(false);
7046OPGEN_RETURN(true);
7047#endif
7048break;
7049break;
7050case Arg::Index:
7051#if CPU(X86_64)
7052if (!Arg::isValidImmForm(args[0].value()))
7053OPGEN_RETURN(false);
7054if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
7055OPGEN_RETURN(false);
7056OPGEN_RETURN(true);
7057#endif
7058break;
7059break;
7060default:
7061break;
7062}
7063break;
7064case Arg::Addr:
7065case Arg::Stack:
7066case Arg::CallArg:
7067switch (this->args[1].kind()) {
7068case Arg::Tmp:
7069#if CPU(X86_64)
7070if (!Arg::isValidAddrForm(args[0].offset()))
7071OPGEN_RETURN(false);
7072if (!args[1].tmp().isGP())
7073OPGEN_RETURN(false);
7074OPGEN_RETURN(true);
7075#endif
7076break;
7077break;
7078default:
7079break;
7080}
7081break;
7082case Arg::Index:
7083switch (this->args[1].kind()) {
7084case Arg::Tmp:
7085#if CPU(X86_64)
7086if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
7087OPGEN_RETURN(false);
7088if (!args[1].tmp().isGP())
7089OPGEN_RETURN(false);
7090OPGEN_RETURN(true);
7091#endif
7092break;
7093break;
7094default:
7095break;
7096}
7097break;
7098default:
7099break;
7100}
7101break;
7102default:
7103break;
7104}
7105break;
7106case Opcode::AndDouble:
7107switch (this->args.size()) {
7108case 3:
7109switch (this->args[0].kind()) {
7110case Arg::Tmp:
7111switch (this->args[1].kind()) {
7112case Arg::Tmp:
7113switch (this->args[2].kind()) {
7114case Arg::Tmp:
7115if (!args[0].tmp().isFP())
7116OPGEN_RETURN(false);
7117if (!args[1].tmp().isFP())
7118OPGEN_RETURN(false);
7119if (!args[2].tmp().isFP())
7120OPGEN_RETURN(false);
7121OPGEN_RETURN(true);
7122break;
7123break;
7124default:
7125break;
7126}
7127break;
7128default:
7129break;
7130}
7131break;
7132default:
7133break;
7134}
7135break;
7136case 2:
7137switch (this->args[0].kind()) {
7138case Arg::Tmp:
7139switch (this->args[1].kind()) {
7140case Arg::Tmp:
7141#if CPU(X86) || CPU(X86_64)
7142if (!args[0].tmp().isFP())
7143OPGEN_RETURN(false);
7144if (!args[1].tmp().isFP())
7145OPGEN_RETURN(false);
7146OPGEN_RETURN(true);
7147#endif
7148break;
7149break;
7150default:
7151break;
7152}
7153break;
7154default:
7155break;
7156}
7157break;
7158default:
7159break;
7160}
7161break;
7162case Opcode::AndFloat:
7163switch (this->args.size()) {
7164case 3:
7165switch (this->args[0].kind()) {
7166case Arg::Tmp:
7167switch (this->args[1].kind()) {
7168case Arg::Tmp:
7169switch (this->args[2].kind()) {
7170case Arg::Tmp:
7171if (!args[0].tmp().isFP())
7172OPGEN_RETURN(false);
7173if (!args[1].tmp().isFP())
7174OPGEN_RETURN(false);
7175if (!args[2].tmp().isFP())
7176OPGEN_RETURN(false);
7177OPGEN_RETURN(true);
7178break;
7179break;
7180default:
7181break;
7182}
7183break;
7184default:
7185break;
7186}
7187break;
7188default:
7189break;
7190}
7191break;
7192case 2:
7193switch (this->args[0].kind()) {
7194case Arg::Tmp:
7195switch (this->args[1].kind()) {
7196case Arg::Tmp:
7197#if CPU(X86) || CPU(X86_64)
7198if (!args[0].tmp().isFP())
7199OPGEN_RETURN(false);
7200if (!args[1].tmp().isFP())
7201OPGEN_RETURN(false);
7202OPGEN_RETURN(true);
7203#endif
7204break;
7205break;
7206default:
7207break;
7208}
7209break;
7210default:
7211break;
7212}
7213break;
7214default:
7215break;
7216}
7217break;
7218case Opcode::OrDouble:
7219switch (this->args.size()) {
7220case 3:
7221switch (this->args[0].kind()) {
7222case Arg::Tmp:
7223switch (this->args[1].kind()) {
7224case Arg::Tmp:
7225switch (this->args[2].kind()) {
7226case Arg::Tmp:
7227if (!args[0].tmp().isFP())
7228OPGEN_RETURN(false);
7229if (!args[1].tmp().isFP())
7230OPGEN_RETURN(false);
7231if (!args[2].tmp().isFP())
7232OPGEN_RETURN(false);
7233OPGEN_RETURN(true);
7234break;
7235break;
7236default:
7237break;
7238}
7239break;
7240default:
7241break;
7242}
7243break;
7244default:
7245break;
7246}
7247break;
7248case 2:
7249switch (this->args[0].kind()) {
7250case Arg::Tmp:
7251switch (this->args[1].kind()) {
7252case Arg::Tmp:
7253#if CPU(X86) || CPU(X86_64)
7254if (!args[0].tmp().isFP())
7255OPGEN_RETURN(false);
7256if (!args[1].tmp().isFP())
7257OPGEN_RETURN(false);
7258OPGEN_RETURN(true);
7259#endif
7260break;
7261break;
7262default:
7263break;
7264}
7265break;
7266default:
7267break;
7268}
7269break;
7270default:
7271break;
7272}
7273break;
7274case Opcode::OrFloat:
7275switch (this->args.size()) {
7276case 3:
7277switch (this->args[0].kind()) {
7278case Arg::Tmp:
7279switch (this->args[1].kind()) {
7280case Arg::Tmp:
7281switch (this->args[2].kind()) {
7282case Arg::Tmp:
7283if (!args[0].tmp().isFP())
7284OPGEN_RETURN(false);
7285if (!args[1].tmp().isFP())
7286OPGEN_RETURN(false);
7287if (!args[2].tmp().isFP())
7288OPGEN_RETURN(false);
7289OPGEN_RETURN(true);
7290break;
7291break;
7292default:
7293break;
7294}
7295break;
7296default:
7297break;
7298}
7299break;
7300default:
7301break;
7302}
7303break;
7304case 2:
7305switch (this->args[0].kind()) {
7306case Arg::Tmp:
7307switch (this->args[1].kind()) {
7308case Arg::Tmp:
7309#if CPU(X86) || CPU(X86_64)
7310if (!args[0].tmp().isFP())
7311OPGEN_RETURN(false);
7312if (!args[1].tmp().isFP())
7313OPGEN_RETURN(false);
7314OPGEN_RETURN(true);
7315#endif
7316break;
7317break;
7318default:
7319break;
7320}
7321break;
7322default:
7323break;
7324}
7325break;
7326default:
7327break;
7328}
7329break;
7330case Opcode::XorDouble:
7331switch (this->args.size()) {
7332case 3:
7333switch (this->args[0].kind()) {
7334case Arg::Tmp:
7335switch (this->args[1].kind()) {
7336case Arg::Tmp:
7337switch (this->args[2].kind()) {
7338case Arg::Tmp:
7339#if CPU(X86) || CPU(X86_64)
7340if (!args[0].tmp().isFP())
7341OPGEN_RETURN(false);
7342if (!args[1].tmp().isFP())
7343OPGEN_RETURN(false);
7344if (!args[2].tmp().isFP())
7345OPGEN_RETURN(false);
7346OPGEN_RETURN(true);
7347#endif
7348break;
7349break;
7350default:
7351break;
7352}
7353break;
7354default:
7355break;
7356}
7357break;
7358default:
7359break;
7360}
7361break;
7362case 2:
7363switch (this->args[0].kind()) {
7364case Arg::Tmp:
7365switch (this->args[1].kind()) {
7366case Arg::Tmp:
7367#if CPU(X86) || CPU(X86_64)
7368if (!args[0].tmp().isFP())
7369OPGEN_RETURN(false);
7370if (!args[1].tmp().isFP())
7371OPGEN_RETURN(false);
7372OPGEN_RETURN(true);
7373#endif
7374break;
7375break;
7376default:
7377break;
7378}
7379break;
7380default:
7381break;
7382}
7383break;
7384default:
7385break;
7386}
7387break;
7388case Opcode::XorFloat:
7389switch (this->args.size()) {
7390case 3:
7391switch (this->args[0].kind()) {
7392case Arg::Tmp:
7393switch (this->args[1].kind()) {
7394case Arg::Tmp:
7395switch (this->args[2].kind()) {
7396case Arg::Tmp:
7397#if CPU(X86) || CPU(X86_64)
7398if (!args[0].tmp().isFP())
7399OPGEN_RETURN(false);
7400if (!args[1].tmp().isFP())
7401OPGEN_RETURN(false);
7402if (!args[2].tmp().isFP())
7403OPGEN_RETURN(false);
7404OPGEN_RETURN(true);
7405#endif
7406break;
7407break;
7408default:
7409break;
7410}
7411break;
7412default:
7413break;
7414}
7415break;
7416default:
7417break;
7418}
7419break;
7420case 2:
7421switch (this->args[0].kind()) {
7422case Arg::Tmp:
7423switch (this->args[1].kind()) {
7424case Arg::Tmp:
7425#if CPU(X86) || CPU(X86_64)
7426if (!args[0].tmp().isFP())
7427OPGEN_RETURN(false);
7428if (!args[1].tmp().isFP())
7429OPGEN_RETURN(false);
7430OPGEN_RETURN(true);
7431#endif
7432break;
7433break;
7434default:
7435break;
7436}
7437break;
7438default:
7439break;
7440}
7441break;
7442default:
7443break;
7444}
7445break;
7446case Opcode::Lshift32:
7447switch (this->args.size()) {
7448case 3:
7449switch (this->args[0].kind()) {
7450case Arg::Tmp:
7451switch (this->args[1].kind()) {
7452case Arg::Tmp:
7453switch (this->args[2].kind()) {
7454case Arg::Tmp:
7455#if CPU(ARM64)
7456if (!args[0].tmp().isGP())
7457OPGEN_RETURN(false);
7458if (!args[1].tmp().isGP())
7459OPGEN_RETURN(false);
7460if (!args[2].tmp().isGP())
7461OPGEN_RETURN(false);
7462OPGEN_RETURN(true);
7463#endif
7464break;
7465break;
7466default:
7467break;
7468}
7469break;
7470case Arg::Imm:
7471switch (this->args[2].kind()) {
7472case Arg::Tmp:
7473#if CPU(ARM64)
7474if (!args[0].tmp().isGP())
7475OPGEN_RETURN(false);
7476if (!Arg::isValidImmForm(args[1].value()))
7477OPGEN_RETURN(false);
7478if (!args[2].tmp().isGP())
7479OPGEN_RETURN(false);
7480OPGEN_RETURN(true);
7481#endif
7482break;
7483break;
7484default:
7485break;
7486}
7487break;
7488default:
7489break;
7490}
7491break;
7492default:
7493break;
7494}
7495break;
7496case 2:
7497switch (this->args[0].kind()) {
7498case Arg::Tmp:
7499switch (this->args[1].kind()) {
7500case Arg::Tmp:
7501#if CPU(X86) || CPU(X86_64)
7502if (!args[0].tmp().isGP())
7503OPGEN_RETURN(false);
7504if (!args[1].tmp().isGP())
7505OPGEN_RETURN(false);
7506if (!isLshift32Valid(*this))
7507OPGEN_RETURN(false);
7508OPGEN_RETURN(true);
7509#endif
7510break;
7511break;
7512default:
7513break;
7514}
7515break;
7516case Arg::Imm:
7517switch (this->args[1].kind()) {
7518case Arg::Tmp:
7519#if CPU(X86) || CPU(X86_64)
7520if (!Arg::isValidImmForm(args[0].value()))
7521OPGEN_RETURN(false);
7522if (!args[1].tmp().isGP())
7523OPGEN_RETURN(false);
7524OPGEN_RETURN(true);
7525#endif
7526break;
7527break;
7528default:
7529break;
7530}
7531break;
7532default:
7533break;
7534}
7535break;
7536default:
7537break;
7538}
7539break;
7540case Opcode::Lshift64:
7541switch (this->args.size()) {
7542case 3:
7543switch (this->args[0].kind()) {
7544case Arg::Tmp:
7545switch (this->args[1].kind()) {
7546case Arg::Tmp:
7547switch (this->args[2].kind()) {
7548case Arg::Tmp:
7549#if CPU(ARM64)
7550if (!args[0].tmp().isGP())
7551OPGEN_RETURN(false);
7552if (!args[1].tmp().isGP())
7553OPGEN_RETURN(false);
7554if (!args[2].tmp().isGP())
7555OPGEN_RETURN(false);
7556OPGEN_RETURN(true);
7557#endif
7558break;
7559break;
7560default:
7561break;
7562}
7563break;
7564case Arg::Imm:
7565switch (this->args[2].kind()) {
7566case Arg::Tmp:
7567#if CPU(ARM64)
7568if (!args[0].tmp().isGP())
7569OPGEN_RETURN(false);
7570if (!Arg::isValidImmForm(args[1].value()))
7571OPGEN_RETURN(false);
7572if (!args[2].tmp().isGP())
7573OPGEN_RETURN(false);
7574OPGEN_RETURN(true);
7575#endif
7576break;
7577break;
7578default:
7579break;
7580}
7581break;
7582default:
7583break;
7584}
7585break;
7586default:
7587break;
7588}
7589break;
7590case 2:
7591switch (this->args[0].kind()) {
7592case Arg::Tmp:
7593switch (this->args[1].kind()) {
7594case Arg::Tmp:
7595#if CPU(X86_64)
7596if (!args[0].tmp().isGP())
7597OPGEN_RETURN(false);
7598if (!args[1].tmp().isGP())
7599OPGEN_RETURN(false);
7600if (!isLshift64Valid(*this))
7601OPGEN_RETURN(false);
7602OPGEN_RETURN(true);
7603#endif
7604break;
7605break;
7606default:
7607break;
7608}
7609break;
7610case Arg::Imm:
7611switch (this->args[1].kind()) {
7612case Arg::Tmp:
7613#if CPU(X86_64)
7614if (!Arg::isValidImmForm(args[0].value()))
7615OPGEN_RETURN(false);
7616if (!args[1].tmp().isGP())
7617OPGEN_RETURN(false);
7618OPGEN_RETURN(true);
7619#endif
7620break;
7621break;
7622default:
7623break;
7624}
7625break;
7626default:
7627break;
7628}
7629break;
7630default:
7631break;
7632}
7633break;
7634case Opcode::Rshift32:
7635switch (this->args.size()) {
7636case 3:
7637switch (this->args[0].kind()) {
7638case Arg::Tmp:
7639switch (this->args[1].kind()) {
7640case Arg::Tmp:
7641switch (this->args[2].kind()) {
7642case Arg::Tmp:
7643#if CPU(ARM64)
7644if (!args[0].tmp().isGP())
7645OPGEN_RETURN(false);
7646if (!args[1].tmp().isGP())
7647OPGEN_RETURN(false);
7648if (!args[2].tmp().isGP())
7649OPGEN_RETURN(false);
7650OPGEN_RETURN(true);
7651#endif
7652break;
7653break;
7654default:
7655break;
7656}
7657break;
7658case Arg::Imm:
7659switch (this->args[2].kind()) {
7660case Arg::Tmp:
7661#if CPU(ARM64)
7662if (!args[0].tmp().isGP())
7663OPGEN_RETURN(false);
7664if (!Arg::isValidImmForm(args[1].value()))
7665OPGEN_RETURN(false);
7666if (!args[2].tmp().isGP())
7667OPGEN_RETURN(false);
7668OPGEN_RETURN(true);
7669#endif
7670break;
7671break;
7672default:
7673break;
7674}
7675break;
7676default:
7677break;
7678}
7679break;
7680default:
7681break;
7682}
7683break;
7684case 2:
7685switch (this->args[0].kind()) {
7686case Arg::Tmp:
7687switch (this->args[1].kind()) {
7688case Arg::Tmp:
7689#if CPU(X86) || CPU(X86_64)
7690if (!args[0].tmp().isGP())
7691OPGEN_RETURN(false);
7692if (!args[1].tmp().isGP())
7693OPGEN_RETURN(false);
7694if (!isRshift32Valid(*this))
7695OPGEN_RETURN(false);
7696OPGEN_RETURN(true);
7697#endif
7698break;
7699break;
7700default:
7701break;
7702}
7703break;
7704case Arg::Imm:
7705switch (this->args[1].kind()) {
7706case Arg::Tmp:
7707#if CPU(X86) || CPU(X86_64)
7708if (!Arg::isValidImmForm(args[0].value()))
7709OPGEN_RETURN(false);
7710if (!args[1].tmp().isGP())
7711OPGEN_RETURN(false);
7712OPGEN_RETURN(true);
7713#endif
7714break;
7715break;
7716default:
7717break;
7718}
7719break;
7720default:
7721break;
7722}
7723break;
7724default:
7725break;
7726}
7727break;
7728case Opcode::Rshift64:
7729switch (this->args.size()) {
7730case 3:
7731switch (this->args[0].kind()) {
7732case Arg::Tmp:
7733switch (this->args[1].kind()) {
7734case Arg::Tmp:
7735switch (this->args[2].kind()) {
7736case Arg::Tmp:
7737#if CPU(ARM64)
7738if (!args[0].tmp().isGP())
7739OPGEN_RETURN(false);
7740if (!args[1].tmp().isGP())
7741OPGEN_RETURN(false);
7742if (!args[2].tmp().isGP())
7743OPGEN_RETURN(false);
7744OPGEN_RETURN(true);
7745#endif
7746break;
7747break;
7748default:
7749break;
7750}
7751break;
7752case Arg::Imm:
7753switch (this->args[2].kind()) {
7754case Arg::Tmp:
7755#if CPU(ARM64)
7756if (!args[0].tmp().isGP())
7757OPGEN_RETURN(false);
7758if (!Arg::isValidImmForm(args[1].value()))
7759OPGEN_RETURN(false);
7760if (!args[2].tmp().isGP())
7761OPGEN_RETURN(false);
7762OPGEN_RETURN(true);
7763#endif
7764break;
7765break;
7766default:
7767break;
7768}
7769break;
7770default:
7771break;
7772}
7773break;
7774default:
7775break;
7776}
7777break;
7778case 2:
7779switch (this->args[0].kind()) {
7780case Arg::Tmp:
7781switch (this->args[1].kind()) {
7782case Arg::Tmp:
7783#if CPU(X86_64)
7784if (!args[0].tmp().isGP())
7785OPGEN_RETURN(false);
7786if (!args[1].tmp().isGP())
7787OPGEN_RETURN(false);
7788if (!isRshift64Valid(*this))
7789OPGEN_RETURN(false);
7790OPGEN_RETURN(true);
7791#endif
7792break;
7793break;
7794default:
7795break;
7796}
7797break;
7798case Arg::Imm:
7799switch (this->args[1].kind()) {
7800case Arg::Tmp:
7801#if CPU(X86_64)
7802if (!Arg::isValidImmForm(args[0].value()))
7803OPGEN_RETURN(false);
7804if (!args[1].tmp().isGP())
7805OPGEN_RETURN(false);
7806OPGEN_RETURN(true);
7807#endif
7808break;
7809break;
7810default:
7811break;
7812}
7813break;
7814default:
7815break;
7816}
7817break;
7818default:
7819break;
7820}
7821break;
7822case Opcode::Urshift32:
7823switch (this->args.size()) {
7824case 3:
7825switch (this->args[0].kind()) {
7826case Arg::Tmp:
7827switch (this->args[1].kind()) {
7828case Arg::Tmp:
7829switch (this->args[2].kind()) {
7830case Arg::Tmp:
7831#if CPU(ARM64)
7832if (!args[0].tmp().isGP())
7833OPGEN_RETURN(false);
7834if (!args[1].tmp().isGP())
7835OPGEN_RETURN(false);
7836if (!args[2].tmp().isGP())
7837OPGEN_RETURN(false);
7838OPGEN_RETURN(true);
7839#endif
7840break;
7841break;
7842default:
7843break;
7844}
7845break;
7846case Arg::Imm:
7847switch (this->args[2].kind()) {
7848case Arg::Tmp:
7849#if CPU(ARM64)
7850if (!args[0].tmp().isGP())
7851OPGEN_RETURN(false);
7852if (!Arg::isValidImmForm(args[1].value()))
7853OPGEN_RETURN(false);
7854if (!args[2].tmp().isGP())
7855OPGEN_RETURN(false);
7856OPGEN_RETURN(true);
7857#endif
7858break;
7859break;
7860default:
7861break;
7862}
7863break;
7864default:
7865break;
7866}
7867break;
7868default:
7869break;
7870}
7871break;
7872case 2:
7873switch (this->args[0].kind()) {
7874case Arg::Tmp:
7875switch (this->args[1].kind()) {
7876case Arg::Tmp:
7877#if CPU(X86) || CPU(X86_64)
7878if (!args[0].tmp().isGP())
7879OPGEN_RETURN(false);
7880if (!args[1].tmp().isGP())
7881OPGEN_RETURN(false);
7882if (!isUrshift32Valid(*this))
7883OPGEN_RETURN(false);
7884OPGEN_RETURN(true);
7885#endif
7886break;
7887break;
7888default:
7889break;
7890}
7891break;
7892case Arg::Imm:
7893switch (this->args[1].kind()) {
7894case Arg::Tmp:
7895#if CPU(X86) || CPU(X86_64)
7896if (!Arg::isValidImmForm(args[0].value()))
7897OPGEN_RETURN(false);
7898if (!args[1].tmp().isGP())
7899OPGEN_RETURN(false);
7900OPGEN_RETURN(true);
7901#endif
7902break;
7903break;
7904default:
7905break;
7906}
7907break;
7908default:
7909break;
7910}
7911break;
7912default:
7913break;
7914}
7915break;
7916case Opcode::Urshift64:
7917switch (this->args.size()) {
7918case 3:
7919switch (this->args[0].kind()) {
7920case Arg::Tmp:
7921switch (this->args[1].kind()) {
7922case Arg::Tmp:
7923switch (this->args[2].kind()) {
7924case Arg::Tmp:
7925#if CPU(ARM64)
7926if (!args[0].tmp().isGP())
7927OPGEN_RETURN(false);
7928if (!args[1].tmp().isGP())
7929OPGEN_RETURN(false);
7930if (!args[2].tmp().isGP())
7931OPGEN_RETURN(false);
7932OPGEN_RETURN(true);
7933#endif
7934break;
7935break;
7936default:
7937break;
7938}
7939break;
7940case Arg::Imm:
7941switch (this->args[2].kind()) {
7942case Arg::Tmp:
7943#if CPU(ARM64)
7944if (!args[0].tmp().isGP())
7945OPGEN_RETURN(false);
7946if (!Arg::isValidImmForm(args[1].value()))
7947OPGEN_RETURN(false);
7948if (!args[2].tmp().isGP())
7949OPGEN_RETURN(false);
7950OPGEN_RETURN(true);
7951#endif
7952break;
7953break;
7954default:
7955break;
7956}
7957break;
7958default:
7959break;
7960}
7961break;
7962default:
7963break;
7964}
7965break;
7966case 2:
7967switch (this->args[0].kind()) {
7968case Arg::Tmp:
7969switch (this->args[1].kind()) {
7970case Arg::Tmp:
7971#if CPU(X86_64)
7972if (!args[0].tmp().isGP())
7973OPGEN_RETURN(false);
7974if (!args[1].tmp().isGP())
7975OPGEN_RETURN(false);
7976if (!isUrshift64Valid(*this))
7977OPGEN_RETURN(false);
7978OPGEN_RETURN(true);
7979#endif
7980break;
7981break;
7982default:
7983break;
7984}
7985break;
7986case Arg::Imm:
7987switch (this->args[1].kind()) {
7988case Arg::Tmp:
7989#if CPU(X86_64)
7990if (!Arg::isValidImmForm(args[0].value()))
7991OPGEN_RETURN(false);
7992if (!args[1].tmp().isGP())
7993OPGEN_RETURN(false);
7994OPGEN_RETURN(true);
7995#endif
7996break;
7997break;
7998default:
7999break;
8000}
8001break;
8002default:
8003break;
8004}
8005break;
8006default:
8007break;
8008}
8009break;
8010case Opcode::RotateRight32:
8011switch (this->args.size()) {
8012case 2:
8013switch (this->args[0].kind()) {
8014case Arg::Tmp:
8015switch (this->args[1].kind()) {
8016case Arg::Tmp:
8017#if CPU(X86_64)
8018if (!args[0].tmp().isGP())
8019OPGEN_RETURN(false);
8020if (!args[1].tmp().isGP())
8021OPGEN_RETURN(false);
8022if (!isRotateRight32Valid(*this))
8023OPGEN_RETURN(false);
8024OPGEN_RETURN(true);
8025#endif
8026break;
8027break;
8028default:
8029break;
8030}
8031break;
8032case Arg::Imm:
8033switch (this->args[1].kind()) {
8034case Arg::Tmp:
8035#if CPU(X86_64)
8036if (!Arg::isValidImmForm(args[0].value()))
8037OPGEN_RETURN(false);
8038if (!args[1].tmp().isGP())
8039OPGEN_RETURN(false);
8040OPGEN_RETURN(true);
8041#endif
8042break;
8043break;
8044default:
8045break;
8046}
8047break;
8048default:
8049break;
8050}
8051break;
8052case 3:
8053switch (this->args[0].kind()) {
8054case Arg::Tmp:
8055switch (this->args[1].kind()) {
8056case Arg::Tmp:
8057switch (this->args[2].kind()) {
8058case Arg::Tmp:
8059#if CPU(ARM64)
8060if (!args[0].tmp().isGP())
8061OPGEN_RETURN(false);
8062if (!args[1].tmp().isGP())
8063OPGEN_RETURN(false);
8064if (!args[2].tmp().isGP())
8065OPGEN_RETURN(false);
8066OPGEN_RETURN(true);
8067#endif
8068break;
8069break;
8070default:
8071break;
8072}
8073break;
8074case Arg::Imm:
8075switch (this->args[2].kind()) {
8076case Arg::Tmp:
8077#if CPU(ARM64)
8078if (!args[0].tmp().isGP())
8079OPGEN_RETURN(false);
8080if (!Arg::isValidImmForm(args[1].value()))
8081OPGEN_RETURN(false);
8082if (!args[2].tmp().isGP())
8083OPGEN_RETURN(false);
8084OPGEN_RETURN(true);
8085#endif
8086break;
8087break;
8088default:
8089break;
8090}
8091break;
8092default:
8093break;
8094}
8095break;
8096default:
8097break;
8098}
8099break;
8100default:
8101break;
8102}
8103break;
8104case Opcode::RotateRight64:
8105switch (this->args.size()) {
8106case 2:
8107switch (this->args[0].kind()) {
8108case Arg::Tmp:
8109switch (this->args[1].kind()) {
8110case Arg::Tmp:
8111#if CPU(X86_64)
8112if (!args[0].tmp().isGP())
8113OPGEN_RETURN(false);
8114if (!args[1].tmp().isGP())
8115OPGEN_RETURN(false);
8116if (!isRotateRight64Valid(*this))
8117OPGEN_RETURN(false);
8118OPGEN_RETURN(true);
8119#endif
8120break;
8121break;
8122default:
8123break;
8124}
8125break;
8126case Arg::Imm:
8127switch (this->args[1].kind()) {
8128case Arg::Tmp:
8129#if CPU(X86_64)
8130if (!Arg::isValidImmForm(args[0].value()))
8131OPGEN_RETURN(false);
8132if (!args[1].tmp().isGP())
8133OPGEN_RETURN(false);
8134OPGEN_RETURN(true);
8135#endif
8136break;
8137break;
8138default:
8139break;
8140}
8141break;
8142default:
8143break;
8144}
8145break;
8146case 3:
8147switch (this->args[0].kind()) {
8148case Arg::Tmp:
8149switch (this->args[1].kind()) {
8150case Arg::Tmp:
8151switch (this->args[2].kind()) {
8152case Arg::Tmp:
8153#if CPU(ARM64)
8154if (!args[0].tmp().isGP())
8155OPGEN_RETURN(false);
8156if (!args[1].tmp().isGP())
8157OPGEN_RETURN(false);
8158if (!args[2].tmp().isGP())
8159OPGEN_RETURN(false);
8160OPGEN_RETURN(true);
8161#endif
8162break;
8163break;
8164default:
8165break;
8166}
8167break;
8168case Arg::Imm:
8169switch (this->args[2].kind()) {
8170case Arg::Tmp:
8171#if CPU(ARM64)
8172if (!args[0].tmp().isGP())
8173OPGEN_RETURN(false);
8174if (!Arg::isValidImmForm(args[1].value()))
8175OPGEN_RETURN(false);
8176if (!args[2].tmp().isGP())
8177OPGEN_RETURN(false);
8178OPGEN_RETURN(true);
8179#endif
8180break;
8181break;
8182default:
8183break;
8184}
8185break;
8186default:
8187break;
8188}
8189break;
8190default:
8191break;
8192}
8193break;
8194default:
8195break;
8196}
8197break;
8198case Opcode::RotateLeft32:
8199switch (this->args.size()) {
8200case 2:
8201switch (this->args[0].kind()) {
8202case Arg::Tmp:
8203switch (this->args[1].kind()) {
8204case Arg::Tmp:
8205#if CPU(X86_64)
8206if (!args[0].tmp().isGP())
8207OPGEN_RETURN(false);
8208if (!args[1].tmp().isGP())
8209OPGEN_RETURN(false);
8210if (!isRotateLeft32Valid(*this))
8211OPGEN_RETURN(false);
8212OPGEN_RETURN(true);
8213#endif
8214break;
8215break;
8216default:
8217break;
8218}
8219break;
8220case Arg::Imm:
8221switch (this->args[1].kind()) {
8222case Arg::Tmp:
8223#if CPU(X86_64)
8224if (!Arg::isValidImmForm(args[0].value()))
8225OPGEN_RETURN(false);
8226if (!args[1].tmp().isGP())
8227OPGEN_RETURN(false);
8228OPGEN_RETURN(true);
8229#endif
8230break;
8231break;
8232default:
8233break;
8234}
8235break;
8236default:
8237break;
8238}
8239break;
8240default:
8241break;
8242}
8243break;
8244case Opcode::RotateLeft64:
8245switch (this->args.size()) {
8246case 2:
8247switch (this->args[0].kind()) {
8248case Arg::Tmp:
8249switch (this->args[1].kind()) {
8250case Arg::Tmp:
8251#if CPU(X86_64)
8252if (!args[0].tmp().isGP())
8253OPGEN_RETURN(false);
8254if (!args[1].tmp().isGP())
8255OPGEN_RETURN(false);
8256if (!isRotateLeft64Valid(*this))
8257OPGEN_RETURN(false);
8258OPGEN_RETURN(true);
8259#endif
8260break;
8261break;
8262default:
8263break;
8264}
8265break;
8266case Arg::Imm:
8267switch (this->args[1].kind()) {
8268case Arg::Tmp:
8269#if CPU(X86_64)
8270if (!Arg::isValidImmForm(args[0].value()))
8271OPGEN_RETURN(false);
8272if (!args[1].tmp().isGP())
8273OPGEN_RETURN(false);
8274OPGEN_RETURN(true);
8275#endif
8276break;
8277break;
8278default:
8279break;
8280}
8281break;
8282default:
8283break;
8284}
8285break;
8286default:
8287break;
8288}
8289break;
8290case Opcode::Or32:
8291switch (this->args.size()) {
8292case 3:
8293switch (this->args[0].kind()) {
8294case Arg::Tmp:
8295switch (this->args[1].kind()) {
8296case Arg::Tmp:
8297switch (this->args[2].kind()) {
8298case Arg::Tmp:
8299if (!args[0].tmp().isGP())
8300OPGEN_RETURN(false);
8301if (!args[1].tmp().isGP())
8302OPGEN_RETURN(false);
8303if (!args[2].tmp().isGP())
8304OPGEN_RETURN(false);
8305OPGEN_RETURN(true);
8306break;
8307break;
8308default:
8309break;
8310}
8311break;
8312case Arg::Addr:
8313case Arg::Stack:
8314case Arg::CallArg:
8315switch (this->args[2].kind()) {
8316case Arg::Tmp:
8317#if CPU(X86) || CPU(X86_64)
8318if (!args[0].tmp().isGP())
8319OPGEN_RETURN(false);
8320if (!Arg::isValidAddrForm(args[1].offset()))
8321OPGEN_RETURN(false);
8322if (!args[2].tmp().isGP())
8323OPGEN_RETURN(false);
8324OPGEN_RETURN(true);
8325#endif
8326break;
8327break;
8328default:
8329break;
8330}
8331break;
8332default:
8333break;
8334}
8335break;
8336case Arg::BitImm:
8337switch (this->args[1].kind()) {
8338case Arg::Tmp:
8339switch (this->args[2].kind()) {
8340case Arg::Tmp:
8341#if CPU(ARM64)
8342if (!Arg::isValidBitImmForm(args[0].value()))
8343OPGEN_RETURN(false);
8344if (!args[1].tmp().isGP())
8345OPGEN_RETURN(false);
8346if (!args[2].tmp().isGP())
8347OPGEN_RETURN(false);
8348OPGEN_RETURN(true);
8349#endif
8350break;
8351break;
8352default:
8353break;
8354}
8355break;
8356default:
8357break;
8358}
8359break;
8360case Arg::Addr:
8361case Arg::Stack:
8362case Arg::CallArg:
8363switch (this->args[1].kind()) {
8364case Arg::Tmp:
8365switch (this->args[2].kind()) {
8366case Arg::Tmp:
8367#if CPU(X86) || CPU(X86_64)
8368if (!Arg::isValidAddrForm(args[0].offset()))
8369OPGEN_RETURN(false);
8370if (!args[1].tmp().isGP())
8371OPGEN_RETURN(false);
8372if (!args[2].tmp().isGP())
8373OPGEN_RETURN(false);
8374OPGEN_RETURN(true);
8375#endif
8376break;
8377break;
8378default:
8379break;
8380}
8381break;
8382default:
8383break;
8384}
8385break;
8386default:
8387break;
8388}
8389break;
8390case 2:
8391switch (this->args[0].kind()) {
8392case Arg::Tmp:
8393switch (this->args[1].kind()) {
8394case Arg::Tmp:
8395if (!args[0].tmp().isGP())
8396OPGEN_RETURN(false);
8397if (!args[1].tmp().isGP())
8398OPGEN_RETURN(false);
8399OPGEN_RETURN(true);
8400break;
8401break;
8402case Arg::Addr:
8403case Arg::Stack:
8404case Arg::CallArg:
8405#if CPU(X86) || CPU(X86_64)
8406if (!args[0].tmp().isGP())
8407OPGEN_RETURN(false);
8408if (!Arg::isValidAddrForm(args[1].offset()))
8409OPGEN_RETURN(false);
8410OPGEN_RETURN(true);
8411#endif
8412break;
8413break;
8414case Arg::Index:
8415#if CPU(X86) || CPU(X86_64)
8416if (!args[0].tmp().isGP())
8417OPGEN_RETURN(false);
8418if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8419OPGEN_RETURN(false);
8420OPGEN_RETURN(true);
8421#endif
8422break;
8423break;
8424default:
8425break;
8426}
8427break;
8428case Arg::Imm:
8429switch (this->args[1].kind()) {
8430case Arg::Tmp:
8431#if CPU(X86) || CPU(X86_64)
8432if (!Arg::isValidImmForm(args[0].value()))
8433OPGEN_RETURN(false);
8434if (!args[1].tmp().isGP())
8435OPGEN_RETURN(false);
8436OPGEN_RETURN(true);
8437#endif
8438break;
8439break;
8440case Arg::Addr:
8441case Arg::Stack:
8442case Arg::CallArg:
8443#if CPU(X86) || CPU(X86_64)
8444if (!Arg::isValidImmForm(args[0].value()))
8445OPGEN_RETURN(false);
8446if (!Arg::isValidAddrForm(args[1].offset()))
8447OPGEN_RETURN(false);
8448OPGEN_RETURN(true);
8449#endif
8450break;
8451break;
8452case Arg::Index:
8453#if CPU(X86) || CPU(X86_64)
8454if (!Arg::isValidImmForm(args[0].value()))
8455OPGEN_RETURN(false);
8456if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8457OPGEN_RETURN(false);
8458OPGEN_RETURN(true);
8459#endif
8460break;
8461break;
8462default:
8463break;
8464}
8465break;
8466case Arg::Addr:
8467case Arg::Stack:
8468case Arg::CallArg:
8469switch (this->args[1].kind()) {
8470case Arg::Tmp:
8471#if CPU(X86) || CPU(X86_64)
8472if (!Arg::isValidAddrForm(args[0].offset()))
8473OPGEN_RETURN(false);
8474if (!args[1].tmp().isGP())
8475OPGEN_RETURN(false);
8476OPGEN_RETURN(true);
8477#endif
8478break;
8479break;
8480default:
8481break;
8482}
8483break;
8484case Arg::Index:
8485switch (this->args[1].kind()) {
8486case Arg::Tmp:
8487#if CPU(X86) || CPU(X86_64)
8488if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
8489OPGEN_RETURN(false);
8490if (!args[1].tmp().isGP())
8491OPGEN_RETURN(false);
8492OPGEN_RETURN(true);
8493#endif
8494break;
8495break;
8496default:
8497break;
8498}
8499break;
8500default:
8501break;
8502}
8503break;
8504default:
8505break;
8506}
8507break;
8508case Opcode::Or64:
8509switch (this->args.size()) {
8510case 3:
8511switch (this->args[0].kind()) {
8512case Arg::Tmp:
8513switch (this->args[1].kind()) {
8514case Arg::Tmp:
8515switch (this->args[2].kind()) {
8516case Arg::Tmp:
8517#if CPU(X86_64) || CPU(ARM64)
8518if (!args[0].tmp().isGP())
8519OPGEN_RETURN(false);
8520if (!args[1].tmp().isGP())
8521OPGEN_RETURN(false);
8522if (!args[2].tmp().isGP())
8523OPGEN_RETURN(false);
8524OPGEN_RETURN(true);
8525#endif
8526break;
8527break;
8528default:
8529break;
8530}
8531break;
8532default:
8533break;
8534}
8535break;
8536#if USE(JSVALUE64)
8537case Arg::BitImm64:
8538switch (this->args[1].kind()) {
8539case Arg::Tmp:
8540switch (this->args[2].kind()) {
8541case Arg::Tmp:
8542#if CPU(ARM64)
8543if (!Arg::isValidBitImm64Form(args[0].value()))
8544OPGEN_RETURN(false);
8545if (!args[1].tmp().isGP())
8546OPGEN_RETURN(false);
8547if (!args[2].tmp().isGP())
8548OPGEN_RETURN(false);
8549OPGEN_RETURN(true);
8550#endif
8551break;
8552break;
8553default:
8554break;
8555}
8556break;
8557default:
8558break;
8559}
8560break;
8561#endif // USE(JSVALUE64)
8562default:
8563break;
8564}
8565break;
8566case 2:
8567switch (this->args[0].kind()) {
8568case Arg::Tmp:
8569switch (this->args[1].kind()) {
8570case Arg::Tmp:
8571#if CPU(X86_64) || CPU(ARM64)
8572if (!args[0].tmp().isGP())
8573OPGEN_RETURN(false);
8574if (!args[1].tmp().isGP())
8575OPGEN_RETURN(false);
8576OPGEN_RETURN(true);
8577#endif
8578break;
8579break;
8580case Arg::Addr:
8581case Arg::Stack:
8582case Arg::CallArg:
8583#if CPU(X86_64)
8584if (!args[0].tmp().isGP())
8585OPGEN_RETURN(false);
8586if (!Arg::isValidAddrForm(args[1].offset()))
8587OPGEN_RETURN(false);
8588OPGEN_RETURN(true);
8589#endif
8590break;
8591break;
8592case Arg::Index:
8593#if CPU(X86_64)
8594if (!args[0].tmp().isGP())
8595OPGEN_RETURN(false);
8596if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
8597OPGEN_RETURN(false);
8598OPGEN_RETURN(true);
8599#endif
8600break;
8601break;
8602default:
8603break;
8604}
8605break;
8606case Arg::Imm:
8607switch (this->args[1].kind()) {
8608case Arg::Tmp:
8609#if CPU(X86_64)
8610if (!Arg::isValidImmForm(args[0].value()))
8611OPGEN_RETURN(false);
8612if (!args[1].tmp().isGP())
8613OPGEN_RETURN(false);
8614OPGEN_RETURN(true);
8615#endif
8616break;
8617break;
8618case Arg::Addr:
8619case Arg::Stack:
8620case Arg::CallArg:
8621#if CPU(X86_64)
8622if (!Arg::isValidImmForm(args[0].value()))
8623OPGEN_RETURN(false);
8624if (!Arg::isValidAddrForm(args[1].offset()))
8625OPGEN_RETURN(false);
8626OPGEN_RETURN(true);
8627#endif
8628break;
8629break;
8630case Arg::Index:
8631#if CPU(X86_64)
8632if (!Arg::isValidImmForm(args[0].value()))
8633OPGEN_RETURN(false);
8634if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
8635OPGEN_RETURN(false);
8636OPGEN_RETURN(true);
8637#endif
8638break;
8639break;
8640default:
8641break;
8642}
8643break;
8644case Arg::Addr:
8645case Arg::Stack:
8646case Arg::CallArg:
8647switch (this->args[1].kind()) {
8648case Arg::Tmp:
8649#if CPU(X86_64)
8650if (!Arg::isValidAddrForm(args[0].offset()))
8651OPGEN_RETURN(false);
8652if (!args[1].tmp().isGP())
8653OPGEN_RETURN(false);
8654OPGEN_RETURN(true);
8655#endif
8656break;
8657break;
8658default:
8659break;
8660}
8661break;
8662case Arg::Index:
8663switch (this->args[1].kind()) {
8664case Arg::Tmp:
8665#if CPU(X86_64)
8666if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
8667OPGEN_RETURN(false);
8668if (!args[1].tmp().isGP())
8669OPGEN_RETURN(false);
8670OPGEN_RETURN(true);
8671#endif
8672break;
8673break;
8674default:
8675break;
8676}
8677break;
8678default:
8679break;
8680}
8681break;
8682default:
8683break;
8684}
8685break;
8686case Opcode::Xor32:
8687switch (this->args.size()) {
8688case 3:
8689switch (this->args[0].kind()) {
8690case Arg::Tmp:
8691switch (this->args[1].kind()) {
8692case Arg::Tmp:
8693switch (this->args[2].kind()) {
8694case Arg::Tmp:
8695if (!args[0].tmp().isGP())
8696OPGEN_RETURN(false);
8697if (!args[1].tmp().isGP())
8698OPGEN_RETURN(false);
8699if (!args[2].tmp().isGP())
8700OPGEN_RETURN(false);
8701OPGEN_RETURN(true);
8702break;
8703break;
8704default:
8705break;
8706}
8707break;
8708case Arg::Addr:
8709case Arg::Stack:
8710case Arg::CallArg:
8711switch (this->args[2].kind()) {
8712case Arg::Tmp:
8713#if CPU(X86) || CPU(X86_64)
8714if (!args[0].tmp().isGP())
8715OPGEN_RETURN(false);
8716if (!Arg::isValidAddrForm(args[1].offset()))
8717OPGEN_RETURN(false);
8718if (!args[2].tmp().isGP())
8719OPGEN_RETURN(false);
8720OPGEN_RETURN(true);
8721#endif
8722break;
8723break;
8724default:
8725break;
8726}
8727break;
8728default:
8729break;
8730}
8731break;
8732case Arg::BitImm:
8733switch (this->args[1].kind()) {
8734case Arg::Tmp:
8735switch (this->args[2].kind()) {
8736case Arg::Tmp:
8737#if CPU(ARM64)
8738if (!Arg::isValidBitImmForm(args[0].value()))
8739OPGEN_RETURN(false);
8740if (!args[1].tmp().isGP())
8741OPGEN_RETURN(false);
8742if (!args[2].tmp().isGP())
8743OPGEN_RETURN(false);
8744OPGEN_RETURN(true);
8745#endif
8746break;
8747break;
8748default:
8749break;
8750}
8751break;
8752default:
8753break;
8754}
8755break;
8756case Arg::Addr:
8757case Arg::Stack:
8758case Arg::CallArg:
8759switch (this->args[1].kind()) {
8760case Arg::Tmp:
8761switch (this->args[2].kind()) {
8762case Arg::Tmp:
8763#if CPU(X86) || CPU(X86_64)
8764if (!Arg::isValidAddrForm(args[0].offset()))
8765OPGEN_RETURN(false);
8766if (!args[1].tmp().isGP())
8767OPGEN_RETURN(false);
8768if (!args[2].tmp().isGP())
8769OPGEN_RETURN(false);
8770OPGEN_RETURN(true);
8771#endif
8772break;
8773break;
8774default:
8775break;
8776}
8777break;
8778default:
8779break;
8780}
8781break;
8782default:
8783break;
8784}
8785break;
8786case 2:
8787switch (this->args[0].kind()) {
8788case Arg::Tmp:
8789switch (this->args[1].kind()) {
8790case Arg::Tmp:
8791if (!args[0].tmp().isGP())
8792OPGEN_RETURN(false);
8793if (!args[1].tmp().isGP())
8794OPGEN_RETURN(false);
8795OPGEN_RETURN(true);
8796break;
8797break;
8798case Arg::Addr:
8799case Arg::Stack:
8800case Arg::CallArg:
8801#if CPU(X86) || CPU(X86_64)
8802if (!args[0].tmp().isGP())
8803OPGEN_RETURN(false);
8804if (!Arg::isValidAddrForm(args[1].offset()))
8805OPGEN_RETURN(false);
8806OPGEN_RETURN(true);
8807#endif
8808break;
8809break;
8810case Arg::Index:
8811#if CPU(X86) || CPU(X86_64)
8812if (!args[0].tmp().isGP())
8813OPGEN_RETURN(false);
8814if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8815OPGEN_RETURN(false);
8816OPGEN_RETURN(true);
8817#endif
8818break;
8819break;
8820default:
8821break;
8822}
8823break;
8824case Arg::Imm:
8825switch (this->args[1].kind()) {
8826case Arg::Tmp:
8827#if CPU(X86) || CPU(X86_64)
8828if (!Arg::isValidImmForm(args[0].value()))
8829OPGEN_RETURN(false);
8830if (!args[1].tmp().isGP())
8831OPGEN_RETURN(false);
8832OPGEN_RETURN(true);
8833#endif
8834break;
8835break;
8836case Arg::Addr:
8837case Arg::Stack:
8838case Arg::CallArg:
8839#if CPU(X86) || CPU(X86_64)
8840if (!Arg::isValidImmForm(args[0].value()))
8841OPGEN_RETURN(false);
8842if (!Arg::isValidAddrForm(args[1].offset()))
8843OPGEN_RETURN(false);
8844OPGEN_RETURN(true);
8845#endif
8846break;
8847break;
8848case Arg::Index:
8849#if CPU(X86) || CPU(X86_64)
8850if (!Arg::isValidImmForm(args[0].value()))
8851OPGEN_RETURN(false);
8852if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
8853OPGEN_RETURN(false);
8854OPGEN_RETURN(true);
8855#endif
8856break;
8857break;
8858default:
8859break;
8860}
8861break;
8862case Arg::Addr:
8863case Arg::Stack:
8864case Arg::CallArg:
8865switch (this->args[1].kind()) {
8866case Arg::Tmp:
8867#if CPU(X86) || CPU(X86_64)
8868if (!Arg::isValidAddrForm(args[0].offset()))
8869OPGEN_RETURN(false);
8870if (!args[1].tmp().isGP())
8871OPGEN_RETURN(false);
8872OPGEN_RETURN(true);
8873#endif
8874break;
8875break;
8876default:
8877break;
8878}
8879break;
8880case Arg::Index:
8881switch (this->args[1].kind()) {
8882case Arg::Tmp:
8883#if CPU(X86) || CPU(X86_64)
8884if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
8885OPGEN_RETURN(false);
8886if (!args[1].tmp().isGP())
8887OPGEN_RETURN(false);
8888OPGEN_RETURN(true);
8889#endif
8890break;
8891break;
8892default:
8893break;
8894}
8895break;
8896default:
8897break;
8898}
8899break;
8900default:
8901break;
8902}
8903break;
8904case Opcode::Xor64:
8905switch (this->args.size()) {
8906case 3:
8907switch (this->args[0].kind()) {
8908case Arg::Tmp:
8909switch (this->args[1].kind()) {
8910case Arg::Tmp:
8911switch (this->args[2].kind()) {
8912case Arg::Tmp:
8913#if CPU(X86_64) || CPU(ARM64)
8914if (!args[0].tmp().isGP())
8915OPGEN_RETURN(false);
8916if (!args[1].tmp().isGP())
8917OPGEN_RETURN(false);
8918if (!args[2].tmp().isGP())
8919OPGEN_RETURN(false);
8920OPGEN_RETURN(true);
8921#endif
8922break;
8923break;
8924default:
8925break;
8926}
8927break;
8928default:
8929break;
8930}
8931break;
8932#if USE(JSVALUE64)
8933case Arg::BitImm64:
8934switch (this->args[1].kind()) {
8935case Arg::Tmp:
8936switch (this->args[2].kind()) {
8937case Arg::Tmp:
8938#if CPU(ARM64)
8939if (!Arg::isValidBitImm64Form(args[0].value()))
8940OPGEN_RETURN(false);
8941if (!args[1].tmp().isGP())
8942OPGEN_RETURN(false);
8943if (!args[2].tmp().isGP())
8944OPGEN_RETURN(false);
8945OPGEN_RETURN(true);
8946#endif
8947break;
8948break;
8949default:
8950break;
8951}
8952break;
8953default:
8954break;
8955}
8956break;
8957#endif // USE(JSVALUE64)
8958default:
8959break;
8960}
8961break;
8962case 2:
8963switch (this->args[0].kind()) {
8964case Arg::Tmp:
8965switch (this->args[1].kind()) {
8966case Arg::Tmp:
8967#if CPU(X86_64) || CPU(ARM64)
8968if (!args[0].tmp().isGP())
8969OPGEN_RETURN(false);
8970if (!args[1].tmp().isGP())
8971OPGEN_RETURN(false);
8972OPGEN_RETURN(true);
8973#endif
8974break;
8975break;
8976case Arg::Addr:
8977case Arg::Stack:
8978case Arg::CallArg:
8979#if CPU(X86_64)
8980if (!args[0].tmp().isGP())
8981OPGEN_RETURN(false);
8982if (!Arg::isValidAddrForm(args[1].offset()))
8983OPGEN_RETURN(false);
8984OPGEN_RETURN(true);
8985#endif
8986break;
8987break;
8988case Arg::Index:
8989#if CPU(X86_64)
8990if (!args[0].tmp().isGP())
8991OPGEN_RETURN(false);
8992if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
8993OPGEN_RETURN(false);
8994OPGEN_RETURN(true);
8995#endif
8996break;
8997break;
8998default:
8999break;
9000}
9001break;
9002case Arg::Addr:
9003case Arg::Stack:
9004case Arg::CallArg:
9005switch (this->args[1].kind()) {
9006case Arg::Tmp:
9007#if CPU(X86_64)
9008if (!Arg::isValidAddrForm(args[0].offset()))
9009OPGEN_RETURN(false);
9010if (!args[1].tmp().isGP())
9011OPGEN_RETURN(false);
9012OPGEN_RETURN(true);
9013#endif
9014break;
9015break;
9016default:
9017break;
9018}
9019break;
9020case Arg::Index:
9021switch (this->args[1].kind()) {
9022case Arg::Tmp:
9023#if CPU(X86_64)
9024if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
9025OPGEN_RETURN(false);
9026if (!args[1].tmp().isGP())
9027OPGEN_RETURN(false);
9028OPGEN_RETURN(true);
9029#endif
9030break;
9031break;
9032default:
9033break;
9034}
9035break;
9036case Arg::Imm:
9037switch (this->args[1].kind()) {
9038case Arg::Addr:
9039case Arg::Stack:
9040case Arg::CallArg:
9041#if CPU(X86_64)
9042if (!Arg::isValidImmForm(args[0].value()))
9043OPGEN_RETURN(false);
9044if (!Arg::isValidAddrForm(args[1].offset()))
9045OPGEN_RETURN(false);
9046OPGEN_RETURN(true);
9047#endif
9048break;
9049break;
9050case Arg::Index:
9051#if CPU(X86_64)
9052if (!Arg::isValidImmForm(args[0].value()))
9053OPGEN_RETURN(false);
9054if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
9055OPGEN_RETURN(false);
9056OPGEN_RETURN(true);
9057#endif
9058break;
9059break;
9060case Arg::Tmp:
9061#if CPU(X86_64)
9062if (!Arg::isValidImmForm(args[0].value()))
9063OPGEN_RETURN(false);
9064if (!args[1].tmp().isGP())
9065OPGEN_RETURN(false);
9066OPGEN_RETURN(true);
9067#endif
9068break;
9069break;
9070default:
9071break;
9072}
9073break;
9074default:
9075break;
9076}
9077break;
9078default:
9079break;
9080}
9081break;
9082case Opcode::Not32:
9083switch (this->args.size()) {
9084case 2:
9085switch (this->args[0].kind()) {
9086case Arg::Tmp:
9087switch (this->args[1].kind()) {
9088case Arg::Tmp:
9089#if CPU(ARM64)
9090if (!args[0].tmp().isGP())
9091OPGEN_RETURN(false);
9092if (!args[1].tmp().isGP())
9093OPGEN_RETURN(false);
9094OPGEN_RETURN(true);
9095#endif
9096break;
9097break;
9098default:
9099break;
9100}
9101break;
9102default:
9103break;
9104}
9105break;
9106case 1:
9107switch (this->args[0].kind()) {
9108case Arg::Tmp:
9109#if CPU(X86) || CPU(X86_64)
9110if (!args[0].tmp().isGP())
9111OPGEN_RETURN(false);
9112OPGEN_RETURN(true);
9113#endif
9114break;
9115break;
9116case Arg::Addr:
9117case Arg::Stack:
9118case Arg::CallArg:
9119#if CPU(X86) || CPU(X86_64)
9120if (!Arg::isValidAddrForm(args[0].offset()))
9121OPGEN_RETURN(false);
9122OPGEN_RETURN(true);
9123#endif
9124break;
9125break;
9126case Arg::Index:
9127#if CPU(X86) || CPU(X86_64)
9128if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
9129OPGEN_RETURN(false);
9130OPGEN_RETURN(true);
9131#endif
9132break;
9133break;
9134default:
9135break;
9136}
9137break;
9138default:
9139break;
9140}
9141break;
9142case Opcode::Not64:
9143switch (this->args.size()) {
9144case 2:
9145switch (this->args[0].kind()) {
9146case Arg::Tmp:
9147switch (this->args[1].kind()) {
9148case Arg::Tmp:
9149#if CPU(ARM64)
9150if (!args[0].tmp().isGP())
9151OPGEN_RETURN(false);
9152if (!args[1].tmp().isGP())
9153OPGEN_RETURN(false);
9154OPGEN_RETURN(true);
9155#endif
9156break;
9157break;
9158default:
9159break;
9160}
9161break;
9162default:
9163break;
9164}
9165break;
9166case 1:
9167switch (this->args[0].kind()) {
9168case Arg::Tmp:
9169#if CPU(X86_64)
9170if (!args[0].tmp().isGP())
9171OPGEN_RETURN(false);
9172OPGEN_RETURN(true);
9173#endif
9174break;
9175break;
9176case Arg::Addr:
9177case Arg::Stack:
9178case Arg::CallArg:
9179#if CPU(X86_64)
9180if (!Arg::isValidAddrForm(args[0].offset()))
9181OPGEN_RETURN(false);
9182OPGEN_RETURN(true);
9183#endif
9184break;
9185break;
9186case Arg::Index:
9187#if CPU(X86_64)
9188if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
9189OPGEN_RETURN(false);
9190OPGEN_RETURN(true);
9191#endif
9192break;
9193break;
9194default:
9195break;
9196}
9197break;
9198default:
9199break;
9200}
9201break;
9202case Opcode::AbsDouble:
9203switch (this->args.size()) {
9204case 2:
9205switch (this->args[0].kind()) {
9206case Arg::Tmp:
9207switch (this->args[1].kind()) {
9208case Arg::Tmp:
9209#if CPU(ARM64)
9210if (!args[0].tmp().isFP())
9211OPGEN_RETURN(false);
9212if (!args[1].tmp().isFP())
9213OPGEN_RETURN(false);
9214OPGEN_RETURN(true);
9215#endif
9216break;
9217break;
9218default:
9219break;
9220}
9221break;
9222default:
9223break;
9224}
9225break;
9226default:
9227break;
9228}
9229break;
9230case Opcode::AbsFloat:
9231switch (this->args.size()) {
9232case 2:
9233switch (this->args[0].kind()) {
9234case Arg::Tmp:
9235switch (this->args[1].kind()) {
9236case Arg::Tmp:
9237#if CPU(ARM64)
9238if (!args[0].tmp().isFP())
9239OPGEN_RETURN(false);
9240if (!args[1].tmp().isFP())
9241OPGEN_RETURN(false);
9242OPGEN_RETURN(true);
9243#endif
9244break;
9245break;
9246default:
9247break;
9248}
9249break;
9250default:
9251break;
9252}
9253break;
9254default:
9255break;
9256}
9257break;
9258case Opcode::CeilDouble:
9259switch (this->args.size()) {
9260case 2:
9261switch (this->args[0].kind()) {
9262case Arg::Tmp:
9263switch (this->args[1].kind()) {
9264case Arg::Tmp:
9265if (!args[0].tmp().isFP())
9266OPGEN_RETURN(false);
9267if (!args[1].tmp().isFP())
9268OPGEN_RETURN(false);
9269OPGEN_RETURN(true);
9270break;
9271break;
9272default:
9273break;
9274}
9275break;
9276case Arg::Addr:
9277case Arg::Stack:
9278case Arg::CallArg:
9279switch (this->args[1].kind()) {
9280case Arg::Tmp:
9281#if CPU(X86) || CPU(X86_64)
9282if (!Arg::isValidAddrForm(args[0].offset()))
9283OPGEN_RETURN(false);
9284if (!args[1].tmp().isFP())
9285OPGEN_RETURN(false);
9286OPGEN_RETURN(true);
9287#endif
9288break;
9289break;
9290default:
9291break;
9292}
9293break;
9294default:
9295break;
9296}
9297break;
9298default:
9299break;
9300}
9301break;
9302case Opcode::CeilFloat:
9303switch (this->args.size()) {
9304case 2:
9305switch (this->args[0].kind()) {
9306case Arg::Tmp:
9307switch (this->args[1].kind()) {
9308case Arg::Tmp:
9309if (!args[0].tmp().isFP())
9310OPGEN_RETURN(false);
9311if (!args[1].tmp().isFP())
9312OPGEN_RETURN(false);
9313OPGEN_RETURN(true);
9314break;
9315break;
9316default:
9317break;
9318}
9319break;
9320case Arg::Addr:
9321case Arg::Stack:
9322case Arg::CallArg:
9323switch (this->args[1].kind()) {
9324case Arg::Tmp:
9325#if CPU(X86) || CPU(X86_64)
9326if (!Arg::isValidAddrForm(args[0].offset()))
9327OPGEN_RETURN(false);
9328if (!args[1].tmp().isFP())
9329OPGEN_RETURN(false);
9330OPGEN_RETURN(true);
9331#endif
9332break;
9333break;
9334default:
9335break;
9336}
9337break;
9338default:
9339break;
9340}
9341break;
9342default:
9343break;
9344}
9345break;
9346case Opcode::FloorDouble:
9347switch (this->args.size()) {
9348case 2:
9349switch (this->args[0].kind()) {
9350case Arg::Tmp:
9351switch (this->args[1].kind()) {
9352case Arg::Tmp:
9353if (!args[0].tmp().isFP())
9354OPGEN_RETURN(false);
9355if (!args[1].tmp().isFP())
9356OPGEN_RETURN(false);
9357OPGEN_RETURN(true);
9358break;
9359break;
9360default:
9361break;
9362}
9363break;
9364case Arg::Addr:
9365case Arg::Stack:
9366case Arg::CallArg:
9367switch (this->args[1].kind()) {
9368case Arg::Tmp:
9369#if CPU(X86) || CPU(X86_64)
9370if (!Arg::isValidAddrForm(args[0].offset()))
9371OPGEN_RETURN(false);
9372if (!args[1].tmp().isFP())
9373OPGEN_RETURN(false);
9374OPGEN_RETURN(true);
9375#endif
9376break;
9377break;
9378default:
9379break;
9380}
9381break;
9382default:
9383break;
9384}
9385break;
9386default:
9387break;
9388}
9389break;
9390case Opcode::FloorFloat:
9391switch (this->args.size()) {
9392case 2:
9393switch (this->args[0].kind()) {
9394case Arg::Tmp:
9395switch (this->args[1].kind()) {
9396case Arg::Tmp:
9397if (!args[0].tmp().isFP())
9398OPGEN_RETURN(false);
9399if (!args[1].tmp().isFP())
9400OPGEN_RETURN(false);
9401OPGEN_RETURN(true);
9402break;
9403break;
9404default:
9405break;
9406}
9407break;
9408case Arg::Addr:
9409case Arg::Stack:
9410case Arg::CallArg:
9411switch (this->args[1].kind()) {
9412case Arg::Tmp:
9413#if CPU(X86) || CPU(X86_64)
9414if (!Arg::isValidAddrForm(args[0].offset()))
9415OPGEN_RETURN(false);
9416if (!args[1].tmp().isFP())
9417OPGEN_RETURN(false);
9418OPGEN_RETURN(true);
9419#endif
9420break;
9421break;
9422default:
9423break;
9424}
9425break;
9426default:
9427break;
9428}
9429break;
9430default:
9431break;
9432}
9433break;
9434case Opcode::SqrtDouble:
9435switch (this->args.size()) {
9436case 2:
9437switch (this->args[0].kind()) {
9438case Arg::Tmp:
9439switch (this->args[1].kind()) {
9440case Arg::Tmp:
9441if (!args[0].tmp().isFP())
9442OPGEN_RETURN(false);
9443if (!args[1].tmp().isFP())
9444OPGEN_RETURN(false);
9445OPGEN_RETURN(true);
9446break;
9447break;
9448default:
9449break;
9450}
9451break;
9452case Arg::Addr:
9453case Arg::Stack:
9454case Arg::CallArg:
9455switch (this->args[1].kind()) {
9456case Arg::Tmp:
9457#if CPU(X86) || CPU(X86_64)
9458if (!Arg::isValidAddrForm(args[0].offset()))
9459OPGEN_RETURN(false);
9460if (!args[1].tmp().isFP())
9461OPGEN_RETURN(false);
9462OPGEN_RETURN(true);
9463#endif
9464break;
9465break;
9466default:
9467break;
9468}
9469break;
9470default:
9471break;
9472}
9473break;
9474default:
9475break;
9476}
9477break;
9478case Opcode::SqrtFloat:
9479switch (this->args.size()) {
9480case 2:
9481switch (this->args[0].kind()) {
9482case Arg::Tmp:
9483switch (this->args[1].kind()) {
9484case Arg::Tmp:
9485if (!args[0].tmp().isFP())
9486OPGEN_RETURN(false);
9487if (!args[1].tmp().isFP())
9488OPGEN_RETURN(false);
9489OPGEN_RETURN(true);
9490break;
9491break;
9492default:
9493break;
9494}
9495break;
9496case Arg::Addr:
9497case Arg::Stack:
9498case Arg::CallArg:
9499switch (this->args[1].kind()) {
9500case Arg::Tmp:
9501#if CPU(X86) || CPU(X86_64)
9502if (!Arg::isValidAddrForm(args[0].offset()))
9503OPGEN_RETURN(false);
9504if (!args[1].tmp().isFP())
9505OPGEN_RETURN(false);
9506OPGEN_RETURN(true);
9507#endif
9508break;
9509break;
9510default:
9511break;
9512}
9513break;
9514default:
9515break;
9516}
9517break;
9518default:
9519break;
9520}
9521break;
9522case Opcode::ConvertInt32ToDouble:
9523switch (this->args.size()) {
9524case 2:
9525switch (this->args[0].kind()) {
9526case Arg::Tmp:
9527switch (this->args[1].kind()) {
9528case Arg::Tmp:
9529if (!args[0].tmp().isGP())
9530OPGEN_RETURN(false);
9531if (!args[1].tmp().isFP())
9532OPGEN_RETURN(false);
9533OPGEN_RETURN(true);
9534break;
9535break;
9536default:
9537break;
9538}
9539break;
9540case Arg::Addr:
9541case Arg::Stack:
9542case Arg::CallArg:
9543switch (this->args[1].kind()) {
9544case Arg::Tmp:
9545#if CPU(X86) || CPU(X86_64)
9546if (!Arg::isValidAddrForm(args[0].offset()))
9547OPGEN_RETURN(false);
9548if (!args[1].tmp().isFP())
9549OPGEN_RETURN(false);
9550OPGEN_RETURN(true);
9551#endif
9552break;
9553break;
9554default:
9555break;
9556}
9557break;
9558default:
9559break;
9560}
9561break;
9562default:
9563break;
9564}
9565break;
9566case Opcode::ConvertInt64ToDouble:
9567switch (this->args.size()) {
9568case 2:
9569switch (this->args[0].kind()) {
9570case Arg::Tmp:
9571switch (this->args[1].kind()) {
9572case Arg::Tmp:
9573#if CPU(X86_64) || CPU(ARM64)
9574if (!args[0].tmp().isGP())
9575OPGEN_RETURN(false);
9576if (!args[1].tmp().isFP())
9577OPGEN_RETURN(false);
9578OPGEN_RETURN(true);
9579#endif
9580break;
9581break;
9582default:
9583break;
9584}
9585break;
9586case Arg::Addr:
9587case Arg::Stack:
9588case Arg::CallArg:
9589switch (this->args[1].kind()) {
9590case Arg::Tmp:
9591#if CPU(X86_64)
9592if (!Arg::isValidAddrForm(args[0].offset()))
9593OPGEN_RETURN(false);
9594if (!args[1].tmp().isFP())
9595OPGEN_RETURN(false);
9596OPGEN_RETURN(true);
9597#endif
9598break;
9599break;
9600default:
9601break;
9602}
9603break;
9604default:
9605break;
9606}
9607break;
9608default:
9609break;
9610}
9611break;
9612case Opcode::ConvertInt32ToFloat:
9613switch (this->args.size()) {
9614case 2:
9615switch (this->args[0].kind()) {
9616case Arg::Tmp:
9617switch (this->args[1].kind()) {
9618case Arg::Tmp:
9619if (!args[0].tmp().isGP())
9620OPGEN_RETURN(false);
9621if (!args[1].tmp().isFP())
9622OPGEN_RETURN(false);
9623OPGEN_RETURN(true);
9624break;
9625break;
9626default:
9627break;
9628}
9629break;
9630case Arg::Addr:
9631case Arg::Stack:
9632case Arg::CallArg:
9633switch (this->args[1].kind()) {
9634case Arg::Tmp:
9635#if CPU(X86) || CPU(X86_64)
9636if (!Arg::isValidAddrForm(args[0].offset()))
9637OPGEN_RETURN(false);
9638if (!args[1].tmp().isFP())
9639OPGEN_RETURN(false);
9640OPGEN_RETURN(true);
9641#endif
9642break;
9643break;
9644default:
9645break;
9646}
9647break;
9648default:
9649break;
9650}
9651break;
9652default:
9653break;
9654}
9655break;
9656case Opcode::ConvertInt64ToFloat:
9657switch (this->args.size()) {
9658case 2:
9659switch (this->args[0].kind()) {
9660case Arg::Tmp:
9661switch (this->args[1].kind()) {
9662case Arg::Tmp:
9663#if CPU(X86_64) || CPU(ARM64)
9664if (!args[0].tmp().isGP())
9665OPGEN_RETURN(false);
9666if (!args[1].tmp().isFP())
9667OPGEN_RETURN(false);
9668OPGEN_RETURN(true);
9669#endif
9670break;
9671break;
9672default:
9673break;
9674}
9675break;
9676case Arg::Addr:
9677case Arg::Stack:
9678case Arg::CallArg:
9679switch (this->args[1].kind()) {
9680case Arg::Tmp:
9681#if CPU(X86_64)
9682if (!Arg::isValidAddrForm(args[0].offset()))
9683OPGEN_RETURN(false);
9684if (!args[1].tmp().isFP())
9685OPGEN_RETURN(false);
9686OPGEN_RETURN(true);
9687#endif
9688break;
9689break;
9690default:
9691break;
9692}
9693break;
9694default:
9695break;
9696}
9697break;
9698default:
9699break;
9700}
9701break;
9702case Opcode::CountLeadingZeros32:
9703switch (this->args.size()) {
9704case 2:
9705switch (this->args[0].kind()) {
9706case Arg::Tmp:
9707switch (this->args[1].kind()) {
9708case Arg::Tmp:
9709if (!args[0].tmp().isGP())
9710OPGEN_RETURN(false);
9711if (!args[1].tmp().isGP())
9712OPGEN_RETURN(false);
9713OPGEN_RETURN(true);
9714break;
9715break;
9716default:
9717break;
9718}
9719break;
9720case Arg::Addr:
9721case Arg::Stack:
9722case Arg::CallArg:
9723switch (this->args[1].kind()) {
9724case Arg::Tmp:
9725#if CPU(X86) || CPU(X86_64)
9726if (!Arg::isValidAddrForm(args[0].offset()))
9727OPGEN_RETURN(false);
9728if (!args[1].tmp().isGP())
9729OPGEN_RETURN(false);
9730OPGEN_RETURN(true);
9731#endif
9732break;
9733break;
9734default:
9735break;
9736}
9737break;
9738default:
9739break;
9740}
9741break;
9742default:
9743break;
9744}
9745break;
9746case Opcode::CountLeadingZeros64:
9747switch (this->args.size()) {
9748case 2:
9749switch (this->args[0].kind()) {
9750case Arg::Tmp:
9751switch (this->args[1].kind()) {
9752case Arg::Tmp:
9753#if CPU(X86_64) || CPU(ARM64)
9754if (!args[0].tmp().isGP())
9755OPGEN_RETURN(false);
9756if (!args[1].tmp().isGP())
9757OPGEN_RETURN(false);
9758OPGEN_RETURN(true);
9759#endif
9760break;
9761break;
9762default:
9763break;
9764}
9765break;
9766case Arg::Addr:
9767case Arg::Stack:
9768case Arg::CallArg:
9769switch (this->args[1].kind()) {
9770case Arg::Tmp:
9771#if CPU(X86_64)
9772if (!Arg::isValidAddrForm(args[0].offset()))
9773OPGEN_RETURN(false);
9774if (!args[1].tmp().isGP())
9775OPGEN_RETURN(false);
9776OPGEN_RETURN(true);
9777#endif
9778break;
9779break;
9780default:
9781break;
9782}
9783break;
9784default:
9785break;
9786}
9787break;
9788default:
9789break;
9790}
9791break;
9792case Opcode::ConvertDoubleToFloat:
9793switch (this->args.size()) {
9794case 2:
9795switch (this->args[0].kind()) {
9796case Arg::Tmp:
9797switch (this->args[1].kind()) {
9798case Arg::Tmp:
9799if (!args[0].tmp().isFP())
9800OPGEN_RETURN(false);
9801if (!args[1].tmp().isFP())
9802OPGEN_RETURN(false);
9803OPGEN_RETURN(true);
9804break;
9805break;
9806default:
9807break;
9808}
9809break;
9810case Arg::Addr:
9811case Arg::Stack:
9812case Arg::CallArg:
9813switch (this->args[1].kind()) {
9814case Arg::Tmp:
9815#if CPU(X86) || CPU(X86_64)
9816if (!Arg::isValidAddrForm(args[0].offset()))
9817OPGEN_RETURN(false);
9818if (!args[1].tmp().isFP())
9819OPGEN_RETURN(false);
9820OPGEN_RETURN(true);
9821#endif
9822break;
9823break;
9824default:
9825break;
9826}
9827break;
9828default:
9829break;
9830}
9831break;
9832default:
9833break;
9834}
9835break;
9836case Opcode::ConvertFloatToDouble:
9837switch (this->args.size()) {
9838case 2:
9839switch (this->args[0].kind()) {
9840case Arg::Tmp:
9841switch (this->args[1].kind()) {
9842case Arg::Tmp:
9843if (!args[0].tmp().isFP())
9844OPGEN_RETURN(false);
9845if (!args[1].tmp().isFP())
9846OPGEN_RETURN(false);
9847OPGEN_RETURN(true);
9848break;
9849break;
9850default:
9851break;
9852}
9853break;
9854case Arg::Addr:
9855case Arg::Stack:
9856case Arg::CallArg:
9857switch (this->args[1].kind()) {
9858case Arg::Tmp:
9859#if CPU(X86) || CPU(X86_64)
9860if (!Arg::isValidAddrForm(args[0].offset()))
9861OPGEN_RETURN(false);
9862if (!args[1].tmp().isFP())
9863OPGEN_RETURN(false);
9864OPGEN_RETURN(true);
9865#endif
9866break;
9867break;
9868default:
9869break;
9870}
9871break;
9872default:
9873break;
9874}
9875break;
9876default:
9877break;
9878}
9879break;
9880case Opcode::Move:
9881switch (this->args.size()) {
9882case 2:
9883switch (this->args[0].kind()) {
9884case Arg::Tmp:
9885switch (this->args[1].kind()) {
9886case Arg::Tmp:
9887if (!args[0].tmp().isGP())
9888OPGEN_RETURN(false);
9889if (!args[1].tmp().isGP())
9890OPGEN_RETURN(false);
9891OPGEN_RETURN(true);
9892break;
9893break;
9894case Arg::Addr:
9895case Arg::Stack:
9896case Arg::CallArg:
9897if (!args[0].tmp().isGP())
9898OPGEN_RETURN(false);
9899if (!Arg::isValidAddrForm(args[1].offset()))
9900OPGEN_RETURN(false);
9901OPGEN_RETURN(true);
9902break;
9903break;
9904case Arg::Index:
9905if (!args[0].tmp().isGP())
9906OPGEN_RETURN(false);
9907if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), POINTER_WIDTH))
9908OPGEN_RETURN(false);
9909OPGEN_RETURN(true);
9910break;
9911break;
9912default:
9913break;
9914}
9915break;
9916case Arg::Imm:
9917switch (this->args[1].kind()) {
9918case Arg::Tmp:
9919if (!Arg::isValidImmForm(args[0].value()))
9920OPGEN_RETURN(false);
9921if (!args[1].tmp().isGP())
9922OPGEN_RETURN(false);
9923OPGEN_RETURN(true);
9924break;
9925break;
9926case Arg::Addr:
9927case Arg::Stack:
9928case Arg::CallArg:
9929#if CPU(X86) || CPU(X86_64)
9930if (!Arg::isValidImmForm(args[0].value()))
9931OPGEN_RETURN(false);
9932if (!Arg::isValidAddrForm(args[1].offset()))
9933OPGEN_RETURN(false);
9934OPGEN_RETURN(true);
9935#endif
9936break;
9937break;
9938default:
9939break;
9940}
9941break;
9942#if USE(JSVALUE64)
9943case Arg::BigImm:
9944switch (this->args[1].kind()) {
9945case Arg::Tmp:
9946if (!args[1].tmp().isGP())
9947OPGEN_RETURN(false);
9948OPGEN_RETURN(true);
9949break;
9950break;
9951default:
9952break;
9953}
9954break;
9955#endif // USE(JSVALUE64)
9956case Arg::Addr:
9957case Arg::Stack:
9958case Arg::CallArg:
9959switch (this->args[1].kind()) {
9960case Arg::Tmp:
9961if (!Arg::isValidAddrForm(args[0].offset()))
9962OPGEN_RETURN(false);
9963if (!args[1].tmp().isGP())
9964OPGEN_RETURN(false);
9965OPGEN_RETURN(true);
9966break;
9967break;
9968default:
9969break;
9970}
9971break;
9972case Arg::Index:
9973switch (this->args[1].kind()) {
9974case Arg::Tmp:
9975if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), POINTER_WIDTH))
9976OPGEN_RETURN(false);
9977if (!args[1].tmp().isGP())
9978OPGEN_RETURN(false);
9979OPGEN_RETURN(true);
9980break;
9981break;
9982default:
9983break;
9984}
9985break;
9986default:
9987break;
9988}
9989break;
9990case 3:
9991switch (this->args[0].kind()) {
9992case Arg::Addr:
9993case Arg::Stack:
9994case Arg::CallArg:
9995switch (this->args[1].kind()) {
9996case Arg::Addr:
9997case Arg::Stack:
9998case Arg::CallArg:
9999switch (this->args[2].kind()) {
10000case Arg::Tmp:
10001if (!Arg::isValidAddrForm(args[0].offset()))
10002OPGEN_RETURN(false);
10003if (!Arg::isValidAddrForm(args[1].offset()))
10004OPGEN_RETURN(false);
10005if (!args[2].tmp().isGP())
10006OPGEN_RETURN(false);
10007OPGEN_RETURN(true);
10008break;
10009break;
10010default:
10011break;
10012}
10013break;
10014default:
10015break;
10016}
10017break;
10018default:
10019break;
10020}
10021break;
10022default:
10023break;
10024}
10025break;
10026case Opcode::Swap32:
10027switch (this->args.size()) {
10028case 2:
10029switch (this->args[0].kind()) {
10030case Arg::Tmp:
10031switch (this->args[1].kind()) {
10032case Arg::Tmp:
10033#if CPU(X86) || CPU(X86_64)
10034if (!args[0].tmp().isGP())
10035OPGEN_RETURN(false);
10036if (!args[1].tmp().isGP())
10037OPGEN_RETURN(false);
10038OPGEN_RETURN(true);
10039#endif
10040break;
10041break;
10042case Arg::Addr:
10043case Arg::Stack:
10044case Arg::CallArg:
10045#if CPU(X86) || CPU(X86_64)
10046if (!args[0].tmp().isGP())
10047OPGEN_RETURN(false);
10048if (!Arg::isValidAddrForm(args[1].offset()))
10049OPGEN_RETURN(false);
10050OPGEN_RETURN(true);
10051#endif
10052break;
10053break;
10054default:
10055break;
10056}
10057break;
10058default:
10059break;
10060}
10061break;
10062default:
10063break;
10064}
10065break;
10066case Opcode::Swap64:
10067switch (this->args.size()) {
10068case 2:
10069switch (this->args[0].kind()) {
10070case Arg::Tmp:
10071switch (this->args[1].kind()) {
10072case Arg::Tmp:
10073#if CPU(X86_64)
10074if (!args[0].tmp().isGP())
10075OPGEN_RETURN(false);
10076if (!args[1].tmp().isGP())
10077OPGEN_RETURN(false);
10078OPGEN_RETURN(true);
10079#endif
10080break;
10081break;
10082case Arg::Addr:
10083case Arg::Stack:
10084case Arg::CallArg:
10085#if CPU(X86_64)
10086if (!args[0].tmp().isGP())
10087OPGEN_RETURN(false);
10088if (!Arg::isValidAddrForm(args[1].offset()))
10089OPGEN_RETURN(false);
10090OPGEN_RETURN(true);
10091#endif
10092break;
10093break;
10094default:
10095break;
10096}
10097break;
10098default:
10099break;
10100}
10101break;
10102default:
10103break;
10104}
10105break;
10106case Opcode::Move32:
10107switch (this->args.size()) {
10108case 2:
10109switch (this->args[0].kind()) {
10110case Arg::Tmp:
10111switch (this->args[1].kind()) {
10112case Arg::Tmp:
10113if (!args[0].tmp().isGP())
10114OPGEN_RETURN(false);
10115if (!args[1].tmp().isGP())
10116OPGEN_RETURN(false);
10117OPGEN_RETURN(true);
10118break;
10119break;
10120case Arg::Addr:
10121case Arg::Stack:
10122case Arg::CallArg:
10123if (!args[0].tmp().isGP())
10124OPGEN_RETURN(false);
10125if (!Arg::isValidAddrForm(args[1].offset()))
10126OPGEN_RETURN(false);
10127OPGEN_RETURN(true);
10128break;
10129break;
10130case Arg::Index:
10131if (!args[0].tmp().isGP())
10132OPGEN_RETURN(false);
10133if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
10134OPGEN_RETURN(false);
10135OPGEN_RETURN(true);
10136break;
10137break;
10138default:
10139break;
10140}
10141break;
10142case Arg::Addr:
10143case Arg::Stack:
10144case Arg::CallArg:
10145switch (this->args[1].kind()) {
10146case Arg::Tmp:
10147if (!Arg::isValidAddrForm(args[0].offset()))
10148OPGEN_RETURN(false);
10149if (!args[1].tmp().isGP())
10150OPGEN_RETURN(false);
10151OPGEN_RETURN(true);
10152break;
10153break;
10154default:
10155break;
10156}
10157break;
10158case Arg::Index:
10159switch (this->args[1].kind()) {
10160case Arg::Tmp:
10161if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10162OPGEN_RETURN(false);
10163if (!args[1].tmp().isGP())
10164OPGEN_RETURN(false);
10165OPGEN_RETURN(true);
10166break;
10167break;
10168default:
10169break;
10170}
10171break;
10172case Arg::Imm:
10173switch (this->args[1].kind()) {
10174case Arg::Tmp:
10175#if CPU(X86) || CPU(X86_64)
10176if (!Arg::isValidImmForm(args[0].value()))
10177OPGEN_RETURN(false);
10178if (!args[1].tmp().isGP())
10179OPGEN_RETURN(false);
10180OPGEN_RETURN(true);
10181#endif
10182break;
10183break;
10184case Arg::Addr:
10185case Arg::Stack:
10186case Arg::CallArg:
10187#if CPU(X86) || CPU(X86_64)
10188if (!Arg::isValidImmForm(args[0].value()))
10189OPGEN_RETURN(false);
10190if (!Arg::isValidAddrForm(args[1].offset()))
10191OPGEN_RETURN(false);
10192OPGEN_RETURN(true);
10193#endif
10194break;
10195break;
10196case Arg::Index:
10197#if CPU(X86) || CPU(X86_64)
10198if (!Arg::isValidImmForm(args[0].value()))
10199OPGEN_RETURN(false);
10200if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
10201OPGEN_RETURN(false);
10202OPGEN_RETURN(true);
10203#endif
10204break;
10205break;
10206default:
10207break;
10208}
10209break;
10210default:
10211break;
10212}
10213break;
10214case 3:
10215switch (this->args[0].kind()) {
10216case Arg::Addr:
10217case Arg::Stack:
10218case Arg::CallArg:
10219switch (this->args[1].kind()) {
10220case Arg::Addr:
10221case Arg::Stack:
10222case Arg::CallArg:
10223switch (this->args[2].kind()) {
10224case Arg::Tmp:
10225if (!Arg::isValidAddrForm(args[0].offset()))
10226OPGEN_RETURN(false);
10227if (!Arg::isValidAddrForm(args[1].offset()))
10228OPGEN_RETURN(false);
10229if (!args[2].tmp().isGP())
10230OPGEN_RETURN(false);
10231OPGEN_RETURN(true);
10232break;
10233break;
10234default:
10235break;
10236}
10237break;
10238default:
10239break;
10240}
10241break;
10242default:
10243break;
10244}
10245break;
10246default:
10247break;
10248}
10249break;
10250case Opcode::StoreZero32:
10251switch (this->args.size()) {
10252case 1:
10253switch (this->args[0].kind()) {
10254case Arg::Addr:
10255case Arg::Stack:
10256case Arg::CallArg:
10257if (!Arg::isValidAddrForm(args[0].offset()))
10258OPGEN_RETURN(false);
10259OPGEN_RETURN(true);
10260break;
10261break;
10262case Arg::Index:
10263if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10264OPGEN_RETURN(false);
10265OPGEN_RETURN(true);
10266break;
10267break;
10268default:
10269break;
10270}
10271break;
10272default:
10273break;
10274}
10275break;
10276case Opcode::StoreZero64:
10277switch (this->args.size()) {
10278case 1:
10279switch (this->args[0].kind()) {
10280case Arg::Addr:
10281case Arg::Stack:
10282case Arg::CallArg:
10283#if CPU(X86_64) || CPU(ARM64)
10284if (!Arg::isValidAddrForm(args[0].offset()))
10285OPGEN_RETURN(false);
10286OPGEN_RETURN(true);
10287#endif
10288break;
10289break;
10290case Arg::Index:
10291#if CPU(X86_64) || CPU(ARM64)
10292if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10293OPGEN_RETURN(false);
10294OPGEN_RETURN(true);
10295#endif
10296break;
10297break;
10298default:
10299break;
10300}
10301break;
10302default:
10303break;
10304}
10305break;
10306case Opcode::SignExtend32ToPtr:
10307switch (this->args.size()) {
10308case 2:
10309switch (this->args[0].kind()) {
10310case Arg::Tmp:
10311switch (this->args[1].kind()) {
10312case Arg::Tmp:
10313if (!args[0].tmp().isGP())
10314OPGEN_RETURN(false);
10315if (!args[1].tmp().isGP())
10316OPGEN_RETURN(false);
10317OPGEN_RETURN(true);
10318break;
10319break;
10320default:
10321break;
10322}
10323break;
10324default:
10325break;
10326}
10327break;
10328default:
10329break;
10330}
10331break;
10332case Opcode::ZeroExtend8To32:
10333switch (this->args.size()) {
10334case 2:
10335switch (this->args[0].kind()) {
10336case Arg::Tmp:
10337switch (this->args[1].kind()) {
10338case Arg::Tmp:
10339if (!args[0].tmp().isGP())
10340OPGEN_RETURN(false);
10341if (!args[1].tmp().isGP())
10342OPGEN_RETURN(false);
10343OPGEN_RETURN(true);
10344break;
10345break;
10346default:
10347break;
10348}
10349break;
10350case Arg::Addr:
10351case Arg::Stack:
10352case Arg::CallArg:
10353switch (this->args[1].kind()) {
10354case Arg::Tmp:
10355#if CPU(X86) || CPU(X86_64)
10356if (!Arg::isValidAddrForm(args[0].offset()))
10357OPGEN_RETURN(false);
10358if (!args[1].tmp().isGP())
10359OPGEN_RETURN(false);
10360OPGEN_RETURN(true);
10361#endif
10362break;
10363break;
10364default:
10365break;
10366}
10367break;
10368case Arg::Index:
10369switch (this->args[1].kind()) {
10370case Arg::Tmp:
10371#if CPU(X86) || CPU(X86_64)
10372if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
10373OPGEN_RETURN(false);
10374if (!args[1].tmp().isGP())
10375OPGEN_RETURN(false);
10376OPGEN_RETURN(true);
10377#endif
10378break;
10379break;
10380default:
10381break;
10382}
10383break;
10384default:
10385break;
10386}
10387break;
10388default:
10389break;
10390}
10391break;
10392case Opcode::SignExtend8To32:
10393switch (this->args.size()) {
10394case 2:
10395switch (this->args[0].kind()) {
10396case Arg::Tmp:
10397switch (this->args[1].kind()) {
10398case Arg::Tmp:
10399if (!args[0].tmp().isGP())
10400OPGEN_RETURN(false);
10401if (!args[1].tmp().isGP())
10402OPGEN_RETURN(false);
10403OPGEN_RETURN(true);
10404break;
10405break;
10406default:
10407break;
10408}
10409break;
10410case Arg::Addr:
10411case Arg::Stack:
10412case Arg::CallArg:
10413switch (this->args[1].kind()) {
10414case Arg::Tmp:
10415#if CPU(X86) || CPU(X86_64)
10416if (!Arg::isValidAddrForm(args[0].offset()))
10417OPGEN_RETURN(false);
10418if (!args[1].tmp().isGP())
10419OPGEN_RETURN(false);
10420OPGEN_RETURN(true);
10421#endif
10422break;
10423break;
10424default:
10425break;
10426}
10427break;
10428case Arg::Index:
10429switch (this->args[1].kind()) {
10430case Arg::Tmp:
10431#if CPU(X86) || CPU(X86_64)
10432if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
10433OPGEN_RETURN(false);
10434if (!args[1].tmp().isGP())
10435OPGEN_RETURN(false);
10436OPGEN_RETURN(true);
10437#endif
10438break;
10439break;
10440default:
10441break;
10442}
10443break;
10444default:
10445break;
10446}
10447break;
10448default:
10449break;
10450}
10451break;
10452case Opcode::ZeroExtend16To32:
10453switch (this->args.size()) {
10454case 2:
10455switch (this->args[0].kind()) {
10456case Arg::Tmp:
10457switch (this->args[1].kind()) {
10458case Arg::Tmp:
10459if (!args[0].tmp().isGP())
10460OPGEN_RETURN(false);
10461if (!args[1].tmp().isGP())
10462OPGEN_RETURN(false);
10463OPGEN_RETURN(true);
10464break;
10465break;
10466default:
10467break;
10468}
10469break;
10470case Arg::Addr:
10471case Arg::Stack:
10472case Arg::CallArg:
10473switch (this->args[1].kind()) {
10474case Arg::Tmp:
10475#if CPU(X86) || CPU(X86_64)
10476if (!Arg::isValidAddrForm(args[0].offset()))
10477OPGEN_RETURN(false);
10478if (!args[1].tmp().isGP())
10479OPGEN_RETURN(false);
10480OPGEN_RETURN(true);
10481#endif
10482break;
10483break;
10484default:
10485break;
10486}
10487break;
10488case Arg::Index:
10489switch (this->args[1].kind()) {
10490case Arg::Tmp:
10491#if CPU(X86) || CPU(X86_64)
10492if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
10493OPGEN_RETURN(false);
10494if (!args[1].tmp().isGP())
10495OPGEN_RETURN(false);
10496OPGEN_RETURN(true);
10497#endif
10498break;
10499break;
10500default:
10501break;
10502}
10503break;
10504default:
10505break;
10506}
10507break;
10508default:
10509break;
10510}
10511break;
10512case Opcode::SignExtend16To32:
10513switch (this->args.size()) {
10514case 2:
10515switch (this->args[0].kind()) {
10516case Arg::Tmp:
10517switch (this->args[1].kind()) {
10518case Arg::Tmp:
10519if (!args[0].tmp().isGP())
10520OPGEN_RETURN(false);
10521if (!args[1].tmp().isGP())
10522OPGEN_RETURN(false);
10523OPGEN_RETURN(true);
10524break;
10525break;
10526default:
10527break;
10528}
10529break;
10530case Arg::Addr:
10531case Arg::Stack:
10532case Arg::CallArg:
10533switch (this->args[1].kind()) {
10534case Arg::Tmp:
10535#if CPU(X86) || CPU(X86_64)
10536if (!Arg::isValidAddrForm(args[0].offset()))
10537OPGEN_RETURN(false);
10538if (!args[1].tmp().isGP())
10539OPGEN_RETURN(false);
10540OPGEN_RETURN(true);
10541#endif
10542break;
10543break;
10544default:
10545break;
10546}
10547break;
10548case Arg::Index:
10549switch (this->args[1].kind()) {
10550case Arg::Tmp:
10551#if CPU(X86) || CPU(X86_64)
10552if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
10553OPGEN_RETURN(false);
10554if (!args[1].tmp().isGP())
10555OPGEN_RETURN(false);
10556OPGEN_RETURN(true);
10557#endif
10558break;
10559break;
10560default:
10561break;
10562}
10563break;
10564default:
10565break;
10566}
10567break;
10568default:
10569break;
10570}
10571break;
10572case Opcode::MoveFloat:
10573switch (this->args.size()) {
10574case 2:
10575switch (this->args[0].kind()) {
10576case Arg::Tmp:
10577switch (this->args[1].kind()) {
10578case Arg::Tmp:
10579if (!args[0].tmp().isFP())
10580OPGEN_RETURN(false);
10581if (!args[1].tmp().isFP())
10582OPGEN_RETURN(false);
10583OPGEN_RETURN(true);
10584break;
10585break;
10586case Arg::Addr:
10587case Arg::Stack:
10588case Arg::CallArg:
10589if (!args[0].tmp().isFP())
10590OPGEN_RETURN(false);
10591if (!Arg::isValidAddrForm(args[1].offset()))
10592OPGEN_RETURN(false);
10593OPGEN_RETURN(true);
10594break;
10595break;
10596case Arg::Index:
10597if (!args[0].tmp().isFP())
10598OPGEN_RETURN(false);
10599if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
10600OPGEN_RETURN(false);
10601OPGEN_RETURN(true);
10602break;
10603break;
10604default:
10605break;
10606}
10607break;
10608case Arg::Addr:
10609case Arg::Stack:
10610case Arg::CallArg:
10611switch (this->args[1].kind()) {
10612case Arg::Tmp:
10613if (!Arg::isValidAddrForm(args[0].offset()))
10614OPGEN_RETURN(false);
10615if (!args[1].tmp().isFP())
10616OPGEN_RETURN(false);
10617OPGEN_RETURN(true);
10618break;
10619break;
10620default:
10621break;
10622}
10623break;
10624case Arg::Index:
10625switch (this->args[1].kind()) {
10626case Arg::Tmp:
10627if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10628OPGEN_RETURN(false);
10629if (!args[1].tmp().isFP())
10630OPGEN_RETURN(false);
10631OPGEN_RETURN(true);
10632break;
10633break;
10634default:
10635break;
10636}
10637break;
10638default:
10639break;
10640}
10641break;
10642case 3:
10643switch (this->args[0].kind()) {
10644case Arg::Addr:
10645case Arg::Stack:
10646case Arg::CallArg:
10647switch (this->args[1].kind()) {
10648case Arg::Addr:
10649case Arg::Stack:
10650case Arg::CallArg:
10651switch (this->args[2].kind()) {
10652case Arg::Tmp:
10653if (!Arg::isValidAddrForm(args[0].offset()))
10654OPGEN_RETURN(false);
10655if (!Arg::isValidAddrForm(args[1].offset()))
10656OPGEN_RETURN(false);
10657if (!args[2].tmp().isFP())
10658OPGEN_RETURN(false);
10659OPGEN_RETURN(true);
10660break;
10661break;
10662default:
10663break;
10664}
10665break;
10666default:
10667break;
10668}
10669break;
10670default:
10671break;
10672}
10673break;
10674default:
10675break;
10676}
10677break;
10678case Opcode::MoveDouble:
10679switch (this->args.size()) {
10680case 2:
10681switch (this->args[0].kind()) {
10682case Arg::Tmp:
10683switch (this->args[1].kind()) {
10684case Arg::Tmp:
10685if (!args[0].tmp().isFP())
10686OPGEN_RETURN(false);
10687if (!args[1].tmp().isFP())
10688OPGEN_RETURN(false);
10689OPGEN_RETURN(true);
10690break;
10691break;
10692case Arg::Addr:
10693case Arg::Stack:
10694case Arg::CallArg:
10695if (!args[0].tmp().isFP())
10696OPGEN_RETURN(false);
10697if (!Arg::isValidAddrForm(args[1].offset()))
10698OPGEN_RETURN(false);
10699OPGEN_RETURN(true);
10700break;
10701break;
10702case Arg::Index:
10703if (!args[0].tmp().isFP())
10704OPGEN_RETURN(false);
10705if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
10706OPGEN_RETURN(false);
10707OPGEN_RETURN(true);
10708break;
10709break;
10710default:
10711break;
10712}
10713break;
10714case Arg::Addr:
10715case Arg::Stack:
10716case Arg::CallArg:
10717switch (this->args[1].kind()) {
10718case Arg::Tmp:
10719if (!Arg::isValidAddrForm(args[0].offset()))
10720OPGEN_RETURN(false);
10721if (!args[1].tmp().isFP())
10722OPGEN_RETURN(false);
10723OPGEN_RETURN(true);
10724break;
10725break;
10726default:
10727break;
10728}
10729break;
10730case Arg::Index:
10731switch (this->args[1].kind()) {
10732case Arg::Tmp:
10733if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10734OPGEN_RETURN(false);
10735if (!args[1].tmp().isFP())
10736OPGEN_RETURN(false);
10737OPGEN_RETURN(true);
10738break;
10739break;
10740default:
10741break;
10742}
10743break;
10744default:
10745break;
10746}
10747break;
10748case 3:
10749switch (this->args[0].kind()) {
10750case Arg::Addr:
10751case Arg::Stack:
10752case Arg::CallArg:
10753switch (this->args[1].kind()) {
10754case Arg::Addr:
10755case Arg::Stack:
10756case Arg::CallArg:
10757switch (this->args[2].kind()) {
10758case Arg::Tmp:
10759if (!Arg::isValidAddrForm(args[0].offset()))
10760OPGEN_RETURN(false);
10761if (!Arg::isValidAddrForm(args[1].offset()))
10762OPGEN_RETURN(false);
10763if (!args[2].tmp().isFP())
10764OPGEN_RETURN(false);
10765OPGEN_RETURN(true);
10766break;
10767break;
10768default:
10769break;
10770}
10771break;
10772default:
10773break;
10774}
10775break;
10776default:
10777break;
10778}
10779break;
10780default:
10781break;
10782}
10783break;
10784case Opcode::MoveZeroToDouble:
10785switch (this->args.size()) {
10786case 1:
10787switch (this->args[0].kind()) {
10788case Arg::Tmp:
10789if (!args[0].tmp().isFP())
10790OPGEN_RETURN(false);
10791OPGEN_RETURN(true);
10792break;
10793break;
10794default:
10795break;
10796}
10797break;
10798default:
10799break;
10800}
10801break;
10802case Opcode::Move64ToDouble:
10803switch (this->args.size()) {
10804case 2:
10805switch (this->args[0].kind()) {
10806case Arg::Tmp:
10807switch (this->args[1].kind()) {
10808case Arg::Tmp:
10809#if CPU(X86_64) || CPU(ARM64)
10810if (!args[0].tmp().isGP())
10811OPGEN_RETURN(false);
10812if (!args[1].tmp().isFP())
10813OPGEN_RETURN(false);
10814OPGEN_RETURN(true);
10815#endif
10816break;
10817break;
10818default:
10819break;
10820}
10821break;
10822case Arg::Addr:
10823case Arg::Stack:
10824case Arg::CallArg:
10825switch (this->args[1].kind()) {
10826case Arg::Tmp:
10827#if CPU(X86_64)
10828if (!Arg::isValidAddrForm(args[0].offset()))
10829OPGEN_RETURN(false);
10830if (!args[1].tmp().isFP())
10831OPGEN_RETURN(false);
10832OPGEN_RETURN(true);
10833#endif
10834break;
10835break;
10836default:
10837break;
10838}
10839break;
10840case Arg::Index:
10841switch (this->args[1].kind()) {
10842case Arg::Tmp:
10843#if CPU(X86_64) || CPU(ARM64)
10844if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10845OPGEN_RETURN(false);
10846if (!args[1].tmp().isFP())
10847OPGEN_RETURN(false);
10848OPGEN_RETURN(true);
10849#endif
10850break;
10851break;
10852default:
10853break;
10854}
10855break;
10856default:
10857break;
10858}
10859break;
10860default:
10861break;
10862}
10863break;
10864case Opcode::Move32ToFloat:
10865switch (this->args.size()) {
10866case 2:
10867switch (this->args[0].kind()) {
10868case Arg::Tmp:
10869switch (this->args[1].kind()) {
10870case Arg::Tmp:
10871if (!args[0].tmp().isGP())
10872OPGEN_RETURN(false);
10873if (!args[1].tmp().isFP())
10874OPGEN_RETURN(false);
10875OPGEN_RETURN(true);
10876break;
10877break;
10878default:
10879break;
10880}
10881break;
10882case Arg::Addr:
10883case Arg::Stack:
10884case Arg::CallArg:
10885switch (this->args[1].kind()) {
10886case Arg::Tmp:
10887#if CPU(X86) || CPU(X86_64)
10888if (!Arg::isValidAddrForm(args[0].offset()))
10889OPGEN_RETURN(false);
10890if (!args[1].tmp().isFP())
10891OPGEN_RETURN(false);
10892OPGEN_RETURN(true);
10893#endif
10894break;
10895break;
10896default:
10897break;
10898}
10899break;
10900case Arg::Index:
10901switch (this->args[1].kind()) {
10902case Arg::Tmp:
10903if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
10904OPGEN_RETURN(false);
10905if (!args[1].tmp().isFP())
10906OPGEN_RETURN(false);
10907OPGEN_RETURN(true);
10908break;
10909break;
10910default:
10911break;
10912}
10913break;
10914default:
10915break;
10916}
10917break;
10918default:
10919break;
10920}
10921break;
10922case Opcode::MoveDoubleTo64:
10923switch (this->args.size()) {
10924case 2:
10925switch (this->args[0].kind()) {
10926case Arg::Tmp:
10927switch (this->args[1].kind()) {
10928case Arg::Tmp:
10929#if CPU(X86_64) || CPU(ARM64)
10930if (!args[0].tmp().isFP())
10931OPGEN_RETURN(false);
10932if (!args[1].tmp().isGP())
10933OPGEN_RETURN(false);
10934OPGEN_RETURN(true);
10935#endif
10936break;
10937break;
10938default:
10939break;
10940}
10941break;
10942case Arg::Addr:
10943case Arg::Stack:
10944case Arg::CallArg:
10945switch (this->args[1].kind()) {
10946case Arg::Tmp:
10947#if CPU(X86_64) || CPU(ARM64)
10948if (!Arg::isValidAddrForm(args[0].offset()))
10949OPGEN_RETURN(false);
10950if (!args[1].tmp().isGP())
10951OPGEN_RETURN(false);
10952OPGEN_RETURN(true);
10953#endif
10954break;
10955break;
10956default:
10957break;
10958}
10959break;
10960case Arg::Index:
10961switch (this->args[1].kind()) {
10962case Arg::Tmp:
10963#if CPU(X86_64) || CPU(ARM64)
10964if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
10965OPGEN_RETURN(false);
10966if (!args[1].tmp().isGP())
10967OPGEN_RETURN(false);
10968OPGEN_RETURN(true);
10969#endif
10970break;
10971break;
10972default:
10973break;
10974}
10975break;
10976default:
10977break;
10978}
10979break;
10980default:
10981break;
10982}
10983break;
10984case Opcode::MoveFloatTo32:
10985switch (this->args.size()) {
10986case 2:
10987switch (this->args[0].kind()) {
10988case Arg::Tmp:
10989switch (this->args[1].kind()) {
10990case Arg::Tmp:
10991if (!args[0].tmp().isFP())
10992OPGEN_RETURN(false);
10993if (!args[1].tmp().isGP())
10994OPGEN_RETURN(false);
10995OPGEN_RETURN(true);
10996break;
10997break;
10998default:
10999break;
11000}
11001break;
11002case Arg::Addr:
11003case Arg::Stack:
11004case Arg::CallArg:
11005switch (this->args[1].kind()) {
11006case Arg::Tmp:
11007if (!Arg::isValidAddrForm(args[0].offset()))
11008OPGEN_RETURN(false);
11009if (!args[1].tmp().isGP())
11010OPGEN_RETURN(false);
11011OPGEN_RETURN(true);
11012break;
11013break;
11014default:
11015break;
11016}
11017break;
11018case Arg::Index:
11019switch (this->args[1].kind()) {
11020case Arg::Tmp:
11021if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
11022OPGEN_RETURN(false);
11023if (!args[1].tmp().isGP())
11024OPGEN_RETURN(false);
11025OPGEN_RETURN(true);
11026break;
11027break;
11028default:
11029break;
11030}
11031break;
11032default:
11033break;
11034}
11035break;
11036default:
11037break;
11038}
11039break;
11040case Opcode::Load8:
11041switch (this->args.size()) {
11042case 2:
11043switch (this->args[0].kind()) {
11044case Arg::Addr:
11045case Arg::Stack:
11046case Arg::CallArg:
11047switch (this->args[1].kind()) {
11048case Arg::Tmp:
11049if (!Arg::isValidAddrForm(args[0].offset()))
11050OPGEN_RETURN(false);
11051if (!args[1].tmp().isGP())
11052OPGEN_RETURN(false);
11053OPGEN_RETURN(true);
11054break;
11055break;
11056default:
11057break;
11058}
11059break;
11060case Arg::Index:
11061switch (this->args[1].kind()) {
11062case Arg::Tmp:
11063if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
11064OPGEN_RETURN(false);
11065if (!args[1].tmp().isGP())
11066OPGEN_RETURN(false);
11067OPGEN_RETURN(true);
11068break;
11069break;
11070default:
11071break;
11072}
11073break;
11074default:
11075break;
11076}
11077break;
11078default:
11079break;
11080}
11081break;
11082case Opcode::LoadAcq8:
11083switch (this->args.size()) {
11084case 2:
11085switch (this->args[0].kind()) {
11086case Arg::SimpleAddr:
11087switch (this->args[1].kind()) {
11088case Arg::Tmp:
11089#if CPU(ARMv7) || CPU(ARM64)
11090if (!args[0].ptr().isGP())
11091OPGEN_RETURN(false);
11092if (!args[1].tmp().isGP())
11093OPGEN_RETURN(false);
11094OPGEN_RETURN(true);
11095#endif
11096break;
11097break;
11098default:
11099break;
11100}
11101break;
11102default:
11103break;
11104}
11105break;
11106default:
11107break;
11108}
11109break;
11110case Opcode::Store8:
11111switch (this->args.size()) {
11112case 2:
11113switch (this->args[0].kind()) {
11114case Arg::Tmp:
11115switch (this->args[1].kind()) {
11116case Arg::Index:
11117if (!args[0].tmp().isGP())
11118OPGEN_RETURN(false);
11119if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
11120OPGEN_RETURN(false);
11121OPGEN_RETURN(true);
11122break;
11123break;
11124case Arg::Addr:
11125case Arg::Stack:
11126case Arg::CallArg:
11127if (!args[0].tmp().isGP())
11128OPGEN_RETURN(false);
11129if (!Arg::isValidAddrForm(args[1].offset()))
11130OPGEN_RETURN(false);
11131OPGEN_RETURN(true);
11132break;
11133break;
11134default:
11135break;
11136}
11137break;
11138case Arg::Imm:
11139switch (this->args[1].kind()) {
11140case Arg::Index:
11141#if CPU(X86) || CPU(X86_64)
11142if (!Arg::isValidImmForm(args[0].value()))
11143OPGEN_RETURN(false);
11144if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
11145OPGEN_RETURN(false);
11146OPGEN_RETURN(true);
11147#endif
11148break;
11149break;
11150case Arg::Addr:
11151case Arg::Stack:
11152case Arg::CallArg:
11153#if CPU(X86) || CPU(X86_64)
11154if (!Arg::isValidImmForm(args[0].value()))
11155OPGEN_RETURN(false);
11156if (!Arg::isValidAddrForm(args[1].offset()))
11157OPGEN_RETURN(false);
11158OPGEN_RETURN(true);
11159#endif
11160break;
11161break;
11162default:
11163break;
11164}
11165break;
11166default:
11167break;
11168}
11169break;
11170default:
11171break;
11172}
11173break;
11174case Opcode::StoreRel8:
11175switch (this->args.size()) {
11176case 2:
11177switch (this->args[0].kind()) {
11178case Arg::Tmp:
11179switch (this->args[1].kind()) {
11180case Arg::SimpleAddr:
11181#if CPU(ARMv7) || CPU(ARM64)
11182if (!args[0].tmp().isGP())
11183OPGEN_RETURN(false);
11184if (!args[1].ptr().isGP())
11185OPGEN_RETURN(false);
11186OPGEN_RETURN(true);
11187#endif
11188break;
11189break;
11190default:
11191break;
11192}
11193break;
11194default:
11195break;
11196}
11197break;
11198default:
11199break;
11200}
11201break;
11202case Opcode::Load8SignedExtendTo32:
11203switch (this->args.size()) {
11204case 2:
11205switch (this->args[0].kind()) {
11206case Arg::Addr:
11207case Arg::Stack:
11208case Arg::CallArg:
11209switch (this->args[1].kind()) {
11210case Arg::Tmp:
11211if (!Arg::isValidAddrForm(args[0].offset()))
11212OPGEN_RETURN(false);
11213if (!args[1].tmp().isGP())
11214OPGEN_RETURN(false);
11215OPGEN_RETURN(true);
11216break;
11217break;
11218default:
11219break;
11220}
11221break;
11222case Arg::Index:
11223switch (this->args[1].kind()) {
11224case Arg::Tmp:
11225if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
11226OPGEN_RETURN(false);
11227if (!args[1].tmp().isGP())
11228OPGEN_RETURN(false);
11229OPGEN_RETURN(true);
11230break;
11231break;
11232default:
11233break;
11234}
11235break;
11236default:
11237break;
11238}
11239break;
11240default:
11241break;
11242}
11243break;
11244case Opcode::LoadAcq8SignedExtendTo32:
11245switch (this->args.size()) {
11246case 2:
11247switch (this->args[0].kind()) {
11248case Arg::SimpleAddr:
11249switch (this->args[1].kind()) {
11250case Arg::Tmp:
11251#if CPU(ARMv7) || CPU(ARM64)
11252if (!args[0].ptr().isGP())
11253OPGEN_RETURN(false);
11254if (!args[1].tmp().isGP())
11255OPGEN_RETURN(false);
11256OPGEN_RETURN(true);
11257#endif
11258break;
11259break;
11260default:
11261break;
11262}
11263break;
11264default:
11265break;
11266}
11267break;
11268default:
11269break;
11270}
11271break;
11272case Opcode::Load16:
11273switch (this->args.size()) {
11274case 2:
11275switch (this->args[0].kind()) {
11276case Arg::Addr:
11277case Arg::Stack:
11278case Arg::CallArg:
11279switch (this->args[1].kind()) {
11280case Arg::Tmp:
11281if (!Arg::isValidAddrForm(args[0].offset()))
11282OPGEN_RETURN(false);
11283if (!args[1].tmp().isGP())
11284OPGEN_RETURN(false);
11285OPGEN_RETURN(true);
11286break;
11287break;
11288default:
11289break;
11290}
11291break;
11292case Arg::Index:
11293switch (this->args[1].kind()) {
11294case Arg::Tmp:
11295if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
11296OPGEN_RETURN(false);
11297if (!args[1].tmp().isGP())
11298OPGEN_RETURN(false);
11299OPGEN_RETURN(true);
11300break;
11301break;
11302default:
11303break;
11304}
11305break;
11306default:
11307break;
11308}
11309break;
11310default:
11311break;
11312}
11313break;
11314case Opcode::LoadAcq16:
11315switch (this->args.size()) {
11316case 2:
11317switch (this->args[0].kind()) {
11318case Arg::SimpleAddr:
11319switch (this->args[1].kind()) {
11320case Arg::Tmp:
11321#if CPU(ARMv7) || CPU(ARM64)
11322if (!args[0].ptr().isGP())
11323OPGEN_RETURN(false);
11324if (!args[1].tmp().isGP())
11325OPGEN_RETURN(false);
11326OPGEN_RETURN(true);
11327#endif
11328break;
11329break;
11330default:
11331break;
11332}
11333break;
11334default:
11335break;
11336}
11337break;
11338default:
11339break;
11340}
11341break;
11342case Opcode::Load16SignedExtendTo32:
11343switch (this->args.size()) {
11344case 2:
11345switch (this->args[0].kind()) {
11346case Arg::Addr:
11347case Arg::Stack:
11348case Arg::CallArg:
11349switch (this->args[1].kind()) {
11350case Arg::Tmp:
11351if (!Arg::isValidAddrForm(args[0].offset()))
11352OPGEN_RETURN(false);
11353if (!args[1].tmp().isGP())
11354OPGEN_RETURN(false);
11355OPGEN_RETURN(true);
11356break;
11357break;
11358default:
11359break;
11360}
11361break;
11362case Arg::Index:
11363switch (this->args[1].kind()) {
11364case Arg::Tmp:
11365if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
11366OPGEN_RETURN(false);
11367if (!args[1].tmp().isGP())
11368OPGEN_RETURN(false);
11369OPGEN_RETURN(true);
11370break;
11371break;
11372default:
11373break;
11374}
11375break;
11376default:
11377break;
11378}
11379break;
11380default:
11381break;
11382}
11383break;
11384case Opcode::LoadAcq16SignedExtendTo32:
11385switch (this->args.size()) {
11386case 2:
11387switch (this->args[0].kind()) {
11388case Arg::SimpleAddr:
11389switch (this->args[1].kind()) {
11390case Arg::Tmp:
11391#if CPU(ARMv7) || CPU(ARM64)
11392if (!args[0].ptr().isGP())
11393OPGEN_RETURN(false);
11394if (!args[1].tmp().isGP())
11395OPGEN_RETURN(false);
11396OPGEN_RETURN(true);
11397#endif
11398break;
11399break;
11400default:
11401break;
11402}
11403break;
11404default:
11405break;
11406}
11407break;
11408default:
11409break;
11410}
11411break;
11412case Opcode::Store16:
11413switch (this->args.size()) {
11414case 2:
11415switch (this->args[0].kind()) {
11416case Arg::Tmp:
11417switch (this->args[1].kind()) {
11418case Arg::Index:
11419if (!args[0].tmp().isGP())
11420OPGEN_RETURN(false);
11421if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
11422OPGEN_RETURN(false);
11423OPGEN_RETURN(true);
11424break;
11425break;
11426case Arg::Addr:
11427case Arg::Stack:
11428case Arg::CallArg:
11429if (!args[0].tmp().isGP())
11430OPGEN_RETURN(false);
11431if (!Arg::isValidAddrForm(args[1].offset()))
11432OPGEN_RETURN(false);
11433OPGEN_RETURN(true);
11434break;
11435break;
11436default:
11437break;
11438}
11439break;
11440case Arg::Imm:
11441switch (this->args[1].kind()) {
11442case Arg::Index:
11443#if CPU(X86) || CPU(X86_64)
11444if (!Arg::isValidImmForm(args[0].value()))
11445OPGEN_RETURN(false);
11446if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
11447OPGEN_RETURN(false);
11448OPGEN_RETURN(true);
11449#endif
11450break;
11451break;
11452case Arg::Addr:
11453case Arg::Stack:
11454case Arg::CallArg:
11455#if CPU(X86) || CPU(X86_64)
11456if (!Arg::isValidImmForm(args[0].value()))
11457OPGEN_RETURN(false);
11458if (!Arg::isValidAddrForm(args[1].offset()))
11459OPGEN_RETURN(false);
11460OPGEN_RETURN(true);
11461#endif
11462break;
11463break;
11464default:
11465break;
11466}
11467break;
11468default:
11469break;
11470}
11471break;
11472default:
11473break;
11474}
11475break;
11476case Opcode::StoreRel16:
11477switch (this->args.size()) {
11478case 2:
11479switch (this->args[0].kind()) {
11480case Arg::Tmp:
11481switch (this->args[1].kind()) {
11482case Arg::SimpleAddr:
11483#if CPU(ARMv7) || CPU(ARM64)
11484if (!args[0].tmp().isGP())
11485OPGEN_RETURN(false);
11486if (!args[1].ptr().isGP())
11487OPGEN_RETURN(false);
11488OPGEN_RETURN(true);
11489#endif
11490break;
11491break;
11492default:
11493break;
11494}
11495break;
11496default:
11497break;
11498}
11499break;
11500default:
11501break;
11502}
11503break;
11504case Opcode::LoadAcq32:
11505switch (this->args.size()) {
11506case 2:
11507switch (this->args[0].kind()) {
11508case Arg::SimpleAddr:
11509switch (this->args[1].kind()) {
11510case Arg::Tmp:
11511#if CPU(ARMv7) || CPU(ARM64)
11512if (!args[0].ptr().isGP())
11513OPGEN_RETURN(false);
11514if (!args[1].tmp().isGP())
11515OPGEN_RETURN(false);
11516OPGEN_RETURN(true);
11517#endif
11518break;
11519break;
11520default:
11521break;
11522}
11523break;
11524default:
11525break;
11526}
11527break;
11528default:
11529break;
11530}
11531break;
11532case Opcode::StoreRel32:
11533switch (this->args.size()) {
11534case 2:
11535switch (this->args[0].kind()) {
11536case Arg::Tmp:
11537switch (this->args[1].kind()) {
11538case Arg::SimpleAddr:
11539#if CPU(ARMv7) || CPU(ARM64)
11540if (!args[0].tmp().isGP())
11541OPGEN_RETURN(false);
11542if (!args[1].ptr().isGP())
11543OPGEN_RETURN(false);
11544OPGEN_RETURN(true);
11545#endif
11546break;
11547break;
11548default:
11549break;
11550}
11551break;
11552default:
11553break;
11554}
11555break;
11556default:
11557break;
11558}
11559break;
11560case Opcode::LoadAcq64:
11561switch (this->args.size()) {
11562case 2:
11563switch (this->args[0].kind()) {
11564case Arg::SimpleAddr:
11565switch (this->args[1].kind()) {
11566case Arg::Tmp:
11567#if CPU(ARM64)
11568if (!args[0].ptr().isGP())
11569OPGEN_RETURN(false);
11570if (!args[1].tmp().isGP())
11571OPGEN_RETURN(false);
11572OPGEN_RETURN(true);
11573#endif
11574break;
11575break;
11576default:
11577break;
11578}
11579break;
11580default:
11581break;
11582}
11583break;
11584default:
11585break;
11586}
11587break;
11588case Opcode::StoreRel64:
11589switch (this->args.size()) {
11590case 2:
11591switch (this->args[0].kind()) {
11592case Arg::Tmp:
11593switch (this->args[1].kind()) {
11594case Arg::SimpleAddr:
11595#if CPU(ARM64)
11596if (!args[0].tmp().isGP())
11597OPGEN_RETURN(false);
11598if (!args[1].ptr().isGP())
11599OPGEN_RETURN(false);
11600OPGEN_RETURN(true);
11601#endif
11602break;
11603break;
11604default:
11605break;
11606}
11607break;
11608default:
11609break;
11610}
11611break;
11612default:
11613break;
11614}
11615break;
11616case Opcode::Xchg8:
11617switch (this->args.size()) {
11618case 2:
11619switch (this->args[0].kind()) {
11620case Arg::Tmp:
11621switch (this->args[1].kind()) {
11622case Arg::Addr:
11623case Arg::Stack:
11624case Arg::CallArg:
11625#if CPU(X86) || CPU(X86_64)
11626if (!args[0].tmp().isGP())
11627OPGEN_RETURN(false);
11628if (!Arg::isValidAddrForm(args[1].offset()))
11629OPGEN_RETURN(false);
11630OPGEN_RETURN(true);
11631#endif
11632break;
11633break;
11634case Arg::Index:
11635#if CPU(X86) || CPU(X86_64)
11636if (!args[0].tmp().isGP())
11637OPGEN_RETURN(false);
11638if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
11639OPGEN_RETURN(false);
11640OPGEN_RETURN(true);
11641#endif
11642break;
11643break;
11644default:
11645break;
11646}
11647break;
11648default:
11649break;
11650}
11651break;
11652default:
11653break;
11654}
11655break;
11656case Opcode::Xchg16:
11657switch (this->args.size()) {
11658case 2:
11659switch (this->args[0].kind()) {
11660case Arg::Tmp:
11661switch (this->args[1].kind()) {
11662case Arg::Addr:
11663case Arg::Stack:
11664case Arg::CallArg:
11665#if CPU(X86) || CPU(X86_64)
11666if (!args[0].tmp().isGP())
11667OPGEN_RETURN(false);
11668if (!Arg::isValidAddrForm(args[1].offset()))
11669OPGEN_RETURN(false);
11670OPGEN_RETURN(true);
11671#endif
11672break;
11673break;
11674case Arg::Index:
11675#if CPU(X86) || CPU(X86_64)
11676if (!args[0].tmp().isGP())
11677OPGEN_RETURN(false);
11678if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
11679OPGEN_RETURN(false);
11680OPGEN_RETURN(true);
11681#endif
11682break;
11683break;
11684default:
11685break;
11686}
11687break;
11688default:
11689break;
11690}
11691break;
11692default:
11693break;
11694}
11695break;
11696case Opcode::Xchg32:
11697switch (this->args.size()) {
11698case 2:
11699switch (this->args[0].kind()) {
11700case Arg::Tmp:
11701switch (this->args[1].kind()) {
11702case Arg::Addr:
11703case Arg::Stack:
11704case Arg::CallArg:
11705#if CPU(X86) || CPU(X86_64)
11706if (!args[0].tmp().isGP())
11707OPGEN_RETURN(false);
11708if (!Arg::isValidAddrForm(args[1].offset()))
11709OPGEN_RETURN(false);
11710OPGEN_RETURN(true);
11711#endif
11712break;
11713break;
11714case Arg::Index:
11715#if CPU(X86) || CPU(X86_64)
11716if (!args[0].tmp().isGP())
11717OPGEN_RETURN(false);
11718if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
11719OPGEN_RETURN(false);
11720OPGEN_RETURN(true);
11721#endif
11722break;
11723break;
11724default:
11725break;
11726}
11727break;
11728default:
11729break;
11730}
11731break;
11732default:
11733break;
11734}
11735break;
11736case Opcode::Xchg64:
11737switch (this->args.size()) {
11738case 2:
11739switch (this->args[0].kind()) {
11740case Arg::Tmp:
11741switch (this->args[1].kind()) {
11742case Arg::Addr:
11743case Arg::Stack:
11744case Arg::CallArg:
11745#if CPU(X86_64)
11746if (!args[0].tmp().isGP())
11747OPGEN_RETURN(false);
11748if (!Arg::isValidAddrForm(args[1].offset()))
11749OPGEN_RETURN(false);
11750OPGEN_RETURN(true);
11751#endif
11752break;
11753break;
11754case Arg::Index:
11755#if CPU(X86_64)
11756if (!args[0].tmp().isGP())
11757OPGEN_RETURN(false);
11758if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
11759OPGEN_RETURN(false);
11760OPGEN_RETURN(true);
11761#endif
11762break;
11763break;
11764default:
11765break;
11766}
11767break;
11768default:
11769break;
11770}
11771break;
11772default:
11773break;
11774}
11775break;
11776case Opcode::AtomicStrongCAS8:
11777switch (this->args.size()) {
11778case 5:
11779switch (this->args[0].kind()) {
11780case Arg::StatusCond:
11781switch (this->args[1].kind()) {
11782case Arg::Tmp:
11783switch (this->args[2].kind()) {
11784case Arg::Tmp:
11785switch (this->args[3].kind()) {
11786case Arg::Addr:
11787case Arg::Stack:
11788case Arg::CallArg:
11789switch (this->args[4].kind()) {
11790case Arg::Tmp:
11791#if CPU(X86) || CPU(X86_64)
11792if (!args[1].tmp().isGP())
11793OPGEN_RETURN(false);
11794if (!args[2].tmp().isGP())
11795OPGEN_RETURN(false);
11796if (!Arg::isValidAddrForm(args[3].offset()))
11797OPGEN_RETURN(false);
11798if (!args[4].tmp().isGP())
11799OPGEN_RETURN(false);
11800if (!isAtomicStrongCAS8Valid(*this))
11801OPGEN_RETURN(false);
11802OPGEN_RETURN(true);
11803#endif
11804break;
11805break;
11806default:
11807break;
11808}
11809break;
11810case Arg::Index:
11811switch (this->args[4].kind()) {
11812case Arg::Tmp:
11813#if CPU(X86) || CPU(X86_64)
11814if (!args[1].tmp().isGP())
11815OPGEN_RETURN(false);
11816if (!args[2].tmp().isGP())
11817OPGEN_RETURN(false);
11818if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width8))
11819OPGEN_RETURN(false);
11820if (!args[4].tmp().isGP())
11821OPGEN_RETURN(false);
11822if (!isAtomicStrongCAS8Valid(*this))
11823OPGEN_RETURN(false);
11824OPGEN_RETURN(true);
11825#endif
11826break;
11827break;
11828default:
11829break;
11830}
11831break;
11832default:
11833break;
11834}
11835break;
11836default:
11837break;
11838}
11839break;
11840default:
11841break;
11842}
11843break;
11844default:
11845break;
11846}
11847break;
11848case 3:
11849switch (this->args[0].kind()) {
11850case Arg::Tmp:
11851switch (this->args[1].kind()) {
11852case Arg::Tmp:
11853switch (this->args[2].kind()) {
11854case Arg::Addr:
11855case Arg::Stack:
11856case Arg::CallArg:
11857#if CPU(X86) || CPU(X86_64)
11858if (!args[0].tmp().isGP())
11859OPGEN_RETURN(false);
11860if (!args[1].tmp().isGP())
11861OPGEN_RETURN(false);
11862if (!Arg::isValidAddrForm(args[2].offset()))
11863OPGEN_RETURN(false);
11864if (!isAtomicStrongCAS8Valid(*this))
11865OPGEN_RETURN(false);
11866OPGEN_RETURN(true);
11867#endif
11868break;
11869break;
11870case Arg::Index:
11871#if CPU(X86) || CPU(X86_64)
11872if (!args[0].tmp().isGP())
11873OPGEN_RETURN(false);
11874if (!args[1].tmp().isGP())
11875OPGEN_RETURN(false);
11876if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width8))
11877OPGEN_RETURN(false);
11878if (!isAtomicStrongCAS8Valid(*this))
11879OPGEN_RETURN(false);
11880OPGEN_RETURN(true);
11881#endif
11882break;
11883break;
11884default:
11885break;
11886}
11887break;
11888default:
11889break;
11890}
11891break;
11892default:
11893break;
11894}
11895break;
11896default:
11897break;
11898}
11899break;
11900case Opcode::AtomicStrongCAS16:
11901switch (this->args.size()) {
11902case 5:
11903switch (this->args[0].kind()) {
11904case Arg::StatusCond:
11905switch (this->args[1].kind()) {
11906case Arg::Tmp:
11907switch (this->args[2].kind()) {
11908case Arg::Tmp:
11909switch (this->args[3].kind()) {
11910case Arg::Addr:
11911case Arg::Stack:
11912case Arg::CallArg:
11913switch (this->args[4].kind()) {
11914case Arg::Tmp:
11915#if CPU(X86) || CPU(X86_64)
11916if (!args[1].tmp().isGP())
11917OPGEN_RETURN(false);
11918if (!args[2].tmp().isGP())
11919OPGEN_RETURN(false);
11920if (!Arg::isValidAddrForm(args[3].offset()))
11921OPGEN_RETURN(false);
11922if (!args[4].tmp().isGP())
11923OPGEN_RETURN(false);
11924if (!isAtomicStrongCAS16Valid(*this))
11925OPGEN_RETURN(false);
11926OPGEN_RETURN(true);
11927#endif
11928break;
11929break;
11930default:
11931break;
11932}
11933break;
11934case Arg::Index:
11935switch (this->args[4].kind()) {
11936case Arg::Tmp:
11937#if CPU(X86) || CPU(X86_64)
11938if (!args[1].tmp().isGP())
11939OPGEN_RETURN(false);
11940if (!args[2].tmp().isGP())
11941OPGEN_RETURN(false);
11942if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width16))
11943OPGEN_RETURN(false);
11944if (!args[4].tmp().isGP())
11945OPGEN_RETURN(false);
11946if (!isAtomicStrongCAS16Valid(*this))
11947OPGEN_RETURN(false);
11948OPGEN_RETURN(true);
11949#endif
11950break;
11951break;
11952default:
11953break;
11954}
11955break;
11956default:
11957break;
11958}
11959break;
11960default:
11961break;
11962}
11963break;
11964default:
11965break;
11966}
11967break;
11968default:
11969break;
11970}
11971break;
11972case 3:
11973switch (this->args[0].kind()) {
11974case Arg::Tmp:
11975switch (this->args[1].kind()) {
11976case Arg::Tmp:
11977switch (this->args[2].kind()) {
11978case Arg::Addr:
11979case Arg::Stack:
11980case Arg::CallArg:
11981#if CPU(X86) || CPU(X86_64)
11982if (!args[0].tmp().isGP())
11983OPGEN_RETURN(false);
11984if (!args[1].tmp().isGP())
11985OPGEN_RETURN(false);
11986if (!Arg::isValidAddrForm(args[2].offset()))
11987OPGEN_RETURN(false);
11988if (!isAtomicStrongCAS16Valid(*this))
11989OPGEN_RETURN(false);
11990OPGEN_RETURN(true);
11991#endif
11992break;
11993break;
11994case Arg::Index:
11995#if CPU(X86) || CPU(X86_64)
11996if (!args[0].tmp().isGP())
11997OPGEN_RETURN(false);
11998if (!args[1].tmp().isGP())
11999OPGEN_RETURN(false);
12000if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width16))
12001OPGEN_RETURN(false);
12002if (!isAtomicStrongCAS16Valid(*this))
12003OPGEN_RETURN(false);
12004OPGEN_RETURN(true);
12005#endif
12006break;
12007break;
12008default:
12009break;
12010}
12011break;
12012default:
12013break;
12014}
12015break;
12016default:
12017break;
12018}
12019break;
12020default:
12021break;
12022}
12023break;
12024case Opcode::AtomicStrongCAS32:
12025switch (this->args.size()) {
12026case 5:
12027switch (this->args[0].kind()) {
12028case Arg::StatusCond:
12029switch (this->args[1].kind()) {
12030case Arg::Tmp:
12031switch (this->args[2].kind()) {
12032case Arg::Tmp:
12033switch (this->args[3].kind()) {
12034case Arg::Addr:
12035case Arg::Stack:
12036case Arg::CallArg:
12037switch (this->args[4].kind()) {
12038case Arg::Tmp:
12039#if CPU(X86) || CPU(X86_64)
12040if (!args[1].tmp().isGP())
12041OPGEN_RETURN(false);
12042if (!args[2].tmp().isGP())
12043OPGEN_RETURN(false);
12044if (!Arg::isValidAddrForm(args[3].offset()))
12045OPGEN_RETURN(false);
12046if (!args[4].tmp().isGP())
12047OPGEN_RETURN(false);
12048if (!isAtomicStrongCAS32Valid(*this))
12049OPGEN_RETURN(false);
12050OPGEN_RETURN(true);
12051#endif
12052break;
12053break;
12054default:
12055break;
12056}
12057break;
12058case Arg::Index:
12059switch (this->args[4].kind()) {
12060case Arg::Tmp:
12061#if CPU(X86) || CPU(X86_64)
12062if (!args[1].tmp().isGP())
12063OPGEN_RETURN(false);
12064if (!args[2].tmp().isGP())
12065OPGEN_RETURN(false);
12066if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width32))
12067OPGEN_RETURN(false);
12068if (!args[4].tmp().isGP())
12069OPGEN_RETURN(false);
12070if (!isAtomicStrongCAS32Valid(*this))
12071OPGEN_RETURN(false);
12072OPGEN_RETURN(true);
12073#endif
12074break;
12075break;
12076default:
12077break;
12078}
12079break;
12080default:
12081break;
12082}
12083break;
12084default:
12085break;
12086}
12087break;
12088default:
12089break;
12090}
12091break;
12092default:
12093break;
12094}
12095break;
12096case 3:
12097switch (this->args[0].kind()) {
12098case Arg::Tmp:
12099switch (this->args[1].kind()) {
12100case Arg::Tmp:
12101switch (this->args[2].kind()) {
12102case Arg::Addr:
12103case Arg::Stack:
12104case Arg::CallArg:
12105#if CPU(X86) || CPU(X86_64)
12106if (!args[0].tmp().isGP())
12107OPGEN_RETURN(false);
12108if (!args[1].tmp().isGP())
12109OPGEN_RETURN(false);
12110if (!Arg::isValidAddrForm(args[2].offset()))
12111OPGEN_RETURN(false);
12112if (!isAtomicStrongCAS32Valid(*this))
12113OPGEN_RETURN(false);
12114OPGEN_RETURN(true);
12115#endif
12116break;
12117break;
12118case Arg::Index:
12119#if CPU(X86) || CPU(X86_64)
12120if (!args[0].tmp().isGP())
12121OPGEN_RETURN(false);
12122if (!args[1].tmp().isGP())
12123OPGEN_RETURN(false);
12124if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width32))
12125OPGEN_RETURN(false);
12126if (!isAtomicStrongCAS32Valid(*this))
12127OPGEN_RETURN(false);
12128OPGEN_RETURN(true);
12129#endif
12130break;
12131break;
12132default:
12133break;
12134}
12135break;
12136default:
12137break;
12138}
12139break;
12140default:
12141break;
12142}
12143break;
12144default:
12145break;
12146}
12147break;
12148case Opcode::AtomicStrongCAS64:
12149switch (this->args.size()) {
12150case 5:
12151switch (this->args[0].kind()) {
12152case Arg::StatusCond:
12153switch (this->args[1].kind()) {
12154case Arg::Tmp:
12155switch (this->args[2].kind()) {
12156case Arg::Tmp:
12157switch (this->args[3].kind()) {
12158case Arg::Addr:
12159case Arg::Stack:
12160case Arg::CallArg:
12161switch (this->args[4].kind()) {
12162case Arg::Tmp:
12163#if CPU(X86_64)
12164if (!args[1].tmp().isGP())
12165OPGEN_RETURN(false);
12166if (!args[2].tmp().isGP())
12167OPGEN_RETURN(false);
12168if (!Arg::isValidAddrForm(args[3].offset()))
12169OPGEN_RETURN(false);
12170if (!args[4].tmp().isGP())
12171OPGEN_RETURN(false);
12172if (!isAtomicStrongCAS64Valid(*this))
12173OPGEN_RETURN(false);
12174OPGEN_RETURN(true);
12175#endif
12176break;
12177break;
12178default:
12179break;
12180}
12181break;
12182case Arg::Index:
12183switch (this->args[4].kind()) {
12184case Arg::Tmp:
12185#if CPU(X86_64)
12186if (!args[1].tmp().isGP())
12187OPGEN_RETURN(false);
12188if (!args[2].tmp().isGP())
12189OPGEN_RETURN(false);
12190if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width64))
12191OPGEN_RETURN(false);
12192if (!args[4].tmp().isGP())
12193OPGEN_RETURN(false);
12194if (!isAtomicStrongCAS64Valid(*this))
12195OPGEN_RETURN(false);
12196OPGEN_RETURN(true);
12197#endif
12198break;
12199break;
12200default:
12201break;
12202}
12203break;
12204default:
12205break;
12206}
12207break;
12208default:
12209break;
12210}
12211break;
12212default:
12213break;
12214}
12215break;
12216default:
12217break;
12218}
12219break;
12220case 3:
12221switch (this->args[0].kind()) {
12222case Arg::Tmp:
12223switch (this->args[1].kind()) {
12224case Arg::Tmp:
12225switch (this->args[2].kind()) {
12226case Arg::Addr:
12227case Arg::Stack:
12228case Arg::CallArg:
12229#if CPU(X86_64)
12230if (!args[0].tmp().isGP())
12231OPGEN_RETURN(false);
12232if (!args[1].tmp().isGP())
12233OPGEN_RETURN(false);
12234if (!Arg::isValidAddrForm(args[2].offset()))
12235OPGEN_RETURN(false);
12236if (!isAtomicStrongCAS64Valid(*this))
12237OPGEN_RETURN(false);
12238OPGEN_RETURN(true);
12239#endif
12240break;
12241break;
12242case Arg::Index:
12243#if CPU(X86_64)
12244if (!args[0].tmp().isGP())
12245OPGEN_RETURN(false);
12246if (!args[1].tmp().isGP())
12247OPGEN_RETURN(false);
12248if (!Arg::isValidIndexForm(args[2].scale(), args[2].offset(), Width64))
12249OPGEN_RETURN(false);
12250if (!isAtomicStrongCAS64Valid(*this))
12251OPGEN_RETURN(false);
12252OPGEN_RETURN(true);
12253#endif
12254break;
12255break;
12256default:
12257break;
12258}
12259break;
12260default:
12261break;
12262}
12263break;
12264default:
12265break;
12266}
12267break;
12268default:
12269break;
12270}
12271break;
12272case Opcode::BranchAtomicStrongCAS8:
12273switch (this->args.size()) {
12274case 4:
12275switch (this->args[0].kind()) {
12276case Arg::StatusCond:
12277switch (this->args[1].kind()) {
12278case Arg::Tmp:
12279switch (this->args[2].kind()) {
12280case Arg::Tmp:
12281switch (this->args[3].kind()) {
12282case Arg::Addr:
12283case Arg::Stack:
12284case Arg::CallArg:
12285#if CPU(X86) || CPU(X86_64)
12286if (!args[1].tmp().isGP())
12287OPGEN_RETURN(false);
12288if (!args[2].tmp().isGP())
12289OPGEN_RETURN(false);
12290if (!Arg::isValidAddrForm(args[3].offset()))
12291OPGEN_RETURN(false);
12292if (!isBranchAtomicStrongCAS8Valid(*this))
12293OPGEN_RETURN(false);
12294OPGEN_RETURN(true);
12295#endif
12296break;
12297break;
12298case Arg::Index:
12299#if CPU(X86) || CPU(X86_64)
12300if (!args[1].tmp().isGP())
12301OPGEN_RETURN(false);
12302if (!args[2].tmp().isGP())
12303OPGEN_RETURN(false);
12304if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width8))
12305OPGEN_RETURN(false);
12306if (!isBranchAtomicStrongCAS8Valid(*this))
12307OPGEN_RETURN(false);
12308OPGEN_RETURN(true);
12309#endif
12310break;
12311break;
12312default:
12313break;
12314}
12315break;
12316default:
12317break;
12318}
12319break;
12320default:
12321break;
12322}
12323break;
12324default:
12325break;
12326}
12327break;
12328default:
12329break;
12330}
12331break;
12332case Opcode::BranchAtomicStrongCAS16:
12333switch (this->args.size()) {
12334case 4:
12335switch (this->args[0].kind()) {
12336case Arg::StatusCond:
12337switch (this->args[1].kind()) {
12338case Arg::Tmp:
12339switch (this->args[2].kind()) {
12340case Arg::Tmp:
12341switch (this->args[3].kind()) {
12342case Arg::Addr:
12343case Arg::Stack:
12344case Arg::CallArg:
12345#if CPU(X86) || CPU(X86_64)
12346if (!args[1].tmp().isGP())
12347OPGEN_RETURN(false);
12348if (!args[2].tmp().isGP())
12349OPGEN_RETURN(false);
12350if (!Arg::isValidAddrForm(args[3].offset()))
12351OPGEN_RETURN(false);
12352if (!isBranchAtomicStrongCAS16Valid(*this))
12353OPGEN_RETURN(false);
12354OPGEN_RETURN(true);
12355#endif
12356break;
12357break;
12358case Arg::Index:
12359#if CPU(X86) || CPU(X86_64)
12360if (!args[1].tmp().isGP())
12361OPGEN_RETURN(false);
12362if (!args[2].tmp().isGP())
12363OPGEN_RETURN(false);
12364if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width16))
12365OPGEN_RETURN(false);
12366if (!isBranchAtomicStrongCAS16Valid(*this))
12367OPGEN_RETURN(false);
12368OPGEN_RETURN(true);
12369#endif
12370break;
12371break;
12372default:
12373break;
12374}
12375break;
12376default:
12377break;
12378}
12379break;
12380default:
12381break;
12382}
12383break;
12384default:
12385break;
12386}
12387break;
12388default:
12389break;
12390}
12391break;
12392case Opcode::BranchAtomicStrongCAS32:
12393switch (this->args.size()) {
12394case 4:
12395switch (this->args[0].kind()) {
12396case Arg::StatusCond:
12397switch (this->args[1].kind()) {
12398case Arg::Tmp:
12399switch (this->args[2].kind()) {
12400case Arg::Tmp:
12401switch (this->args[3].kind()) {
12402case Arg::Addr:
12403case Arg::Stack:
12404case Arg::CallArg:
12405#if CPU(X86) || CPU(X86_64)
12406if (!args[1].tmp().isGP())
12407OPGEN_RETURN(false);
12408if (!args[2].tmp().isGP())
12409OPGEN_RETURN(false);
12410if (!Arg::isValidAddrForm(args[3].offset()))
12411OPGEN_RETURN(false);
12412if (!isBranchAtomicStrongCAS32Valid(*this))
12413OPGEN_RETURN(false);
12414OPGEN_RETURN(true);
12415#endif
12416break;
12417break;
12418case Arg::Index:
12419#if CPU(X86) || CPU(X86_64)
12420if (!args[1].tmp().isGP())
12421OPGEN_RETURN(false);
12422if (!args[2].tmp().isGP())
12423OPGEN_RETURN(false);
12424if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width32))
12425OPGEN_RETURN(false);
12426if (!isBranchAtomicStrongCAS32Valid(*this))
12427OPGEN_RETURN(false);
12428OPGEN_RETURN(true);
12429#endif
12430break;
12431break;
12432default:
12433break;
12434}
12435break;
12436default:
12437break;
12438}
12439break;
12440default:
12441break;
12442}
12443break;
12444default:
12445break;
12446}
12447break;
12448default:
12449break;
12450}
12451break;
12452case Opcode::BranchAtomicStrongCAS64:
12453switch (this->args.size()) {
12454case 4:
12455switch (this->args[0].kind()) {
12456case Arg::StatusCond:
12457switch (this->args[1].kind()) {
12458case Arg::Tmp:
12459switch (this->args[2].kind()) {
12460case Arg::Tmp:
12461switch (this->args[3].kind()) {
12462case Arg::Addr:
12463case Arg::Stack:
12464case Arg::CallArg:
12465#if CPU(X86_64)
12466if (!args[1].tmp().isGP())
12467OPGEN_RETURN(false);
12468if (!args[2].tmp().isGP())
12469OPGEN_RETURN(false);
12470if (!Arg::isValidAddrForm(args[3].offset()))
12471OPGEN_RETURN(false);
12472if (!isBranchAtomicStrongCAS64Valid(*this))
12473OPGEN_RETURN(false);
12474OPGEN_RETURN(true);
12475#endif
12476break;
12477break;
12478case Arg::Index:
12479#if CPU(X86_64)
12480if (!args[1].tmp().isGP())
12481OPGEN_RETURN(false);
12482if (!args[2].tmp().isGP())
12483OPGEN_RETURN(false);
12484if (!Arg::isValidIndexForm(args[3].scale(), args[3].offset(), Width64))
12485OPGEN_RETURN(false);
12486if (!isBranchAtomicStrongCAS64Valid(*this))
12487OPGEN_RETURN(false);
12488OPGEN_RETURN(true);
12489#endif
12490break;
12491break;
12492default:
12493break;
12494}
12495break;
12496default:
12497break;
12498}
12499break;
12500default:
12501break;
12502}
12503break;
12504default:
12505break;
12506}
12507break;
12508default:
12509break;
12510}
12511break;
12512case Opcode::AtomicAdd8:
12513switch (this->args.size()) {
12514case 2:
12515switch (this->args[0].kind()) {
12516case Arg::Imm:
12517switch (this->args[1].kind()) {
12518case Arg::Addr:
12519case Arg::Stack:
12520case Arg::CallArg:
12521#if CPU(X86) || CPU(X86_64)
12522if (!Arg::isValidImmForm(args[0].value()))
12523OPGEN_RETURN(false);
12524if (!Arg::isValidAddrForm(args[1].offset()))
12525OPGEN_RETURN(false);
12526OPGEN_RETURN(true);
12527#endif
12528break;
12529break;
12530case Arg::Index:
12531#if CPU(X86) || CPU(X86_64)
12532if (!Arg::isValidImmForm(args[0].value()))
12533OPGEN_RETURN(false);
12534if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12535OPGEN_RETURN(false);
12536OPGEN_RETURN(true);
12537#endif
12538break;
12539break;
12540default:
12541break;
12542}
12543break;
12544case Arg::Tmp:
12545switch (this->args[1].kind()) {
12546case Arg::Addr:
12547case Arg::Stack:
12548case Arg::CallArg:
12549#if CPU(X86) || CPU(X86_64)
12550if (!args[0].tmp().isGP())
12551OPGEN_RETURN(false);
12552if (!Arg::isValidAddrForm(args[1].offset()))
12553OPGEN_RETURN(false);
12554OPGEN_RETURN(true);
12555#endif
12556break;
12557break;
12558case Arg::Index:
12559#if CPU(X86) || CPU(X86_64)
12560if (!args[0].tmp().isGP())
12561OPGEN_RETURN(false);
12562if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12563OPGEN_RETURN(false);
12564OPGEN_RETURN(true);
12565#endif
12566break;
12567break;
12568default:
12569break;
12570}
12571break;
12572default:
12573break;
12574}
12575break;
12576default:
12577break;
12578}
12579break;
12580case Opcode::AtomicAdd16:
12581switch (this->args.size()) {
12582case 2:
12583switch (this->args[0].kind()) {
12584case Arg::Imm:
12585switch (this->args[1].kind()) {
12586case Arg::Addr:
12587case Arg::Stack:
12588case Arg::CallArg:
12589#if CPU(X86) || CPU(X86_64)
12590if (!Arg::isValidImmForm(args[0].value()))
12591OPGEN_RETURN(false);
12592if (!Arg::isValidAddrForm(args[1].offset()))
12593OPGEN_RETURN(false);
12594OPGEN_RETURN(true);
12595#endif
12596break;
12597break;
12598case Arg::Index:
12599#if CPU(X86) || CPU(X86_64)
12600if (!Arg::isValidImmForm(args[0].value()))
12601OPGEN_RETURN(false);
12602if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12603OPGEN_RETURN(false);
12604OPGEN_RETURN(true);
12605#endif
12606break;
12607break;
12608default:
12609break;
12610}
12611break;
12612case Arg::Tmp:
12613switch (this->args[1].kind()) {
12614case Arg::Addr:
12615case Arg::Stack:
12616case Arg::CallArg:
12617#if CPU(X86) || CPU(X86_64)
12618if (!args[0].tmp().isGP())
12619OPGEN_RETURN(false);
12620if (!Arg::isValidAddrForm(args[1].offset()))
12621OPGEN_RETURN(false);
12622OPGEN_RETURN(true);
12623#endif
12624break;
12625break;
12626case Arg::Index:
12627#if CPU(X86) || CPU(X86_64)
12628if (!args[0].tmp().isGP())
12629OPGEN_RETURN(false);
12630if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12631OPGEN_RETURN(false);
12632OPGEN_RETURN(true);
12633#endif
12634break;
12635break;
12636default:
12637break;
12638}
12639break;
12640default:
12641break;
12642}
12643break;
12644default:
12645break;
12646}
12647break;
12648case Opcode::AtomicAdd32:
12649switch (this->args.size()) {
12650case 2:
12651switch (this->args[0].kind()) {
12652case Arg::Imm:
12653switch (this->args[1].kind()) {
12654case Arg::Addr:
12655case Arg::Stack:
12656case Arg::CallArg:
12657#if CPU(X86) || CPU(X86_64)
12658if (!Arg::isValidImmForm(args[0].value()))
12659OPGEN_RETURN(false);
12660if (!Arg::isValidAddrForm(args[1].offset()))
12661OPGEN_RETURN(false);
12662OPGEN_RETURN(true);
12663#endif
12664break;
12665break;
12666case Arg::Index:
12667#if CPU(X86) || CPU(X86_64)
12668if (!Arg::isValidImmForm(args[0].value()))
12669OPGEN_RETURN(false);
12670if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
12671OPGEN_RETURN(false);
12672OPGEN_RETURN(true);
12673#endif
12674break;
12675break;
12676default:
12677break;
12678}
12679break;
12680case Arg::Tmp:
12681switch (this->args[1].kind()) {
12682case Arg::Addr:
12683case Arg::Stack:
12684case Arg::CallArg:
12685#if CPU(X86) || CPU(X86_64)
12686if (!args[0].tmp().isGP())
12687OPGEN_RETURN(false);
12688if (!Arg::isValidAddrForm(args[1].offset()))
12689OPGEN_RETURN(false);
12690OPGEN_RETURN(true);
12691#endif
12692break;
12693break;
12694case Arg::Index:
12695#if CPU(X86) || CPU(X86_64)
12696if (!args[0].tmp().isGP())
12697OPGEN_RETURN(false);
12698if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
12699OPGEN_RETURN(false);
12700OPGEN_RETURN(true);
12701#endif
12702break;
12703break;
12704default:
12705break;
12706}
12707break;
12708default:
12709break;
12710}
12711break;
12712default:
12713break;
12714}
12715break;
12716case Opcode::AtomicAdd64:
12717switch (this->args.size()) {
12718case 2:
12719switch (this->args[0].kind()) {
12720case Arg::Imm:
12721switch (this->args[1].kind()) {
12722case Arg::Addr:
12723case Arg::Stack:
12724case Arg::CallArg:
12725#if CPU(X86_64)
12726if (!Arg::isValidImmForm(args[0].value()))
12727OPGEN_RETURN(false);
12728if (!Arg::isValidAddrForm(args[1].offset()))
12729OPGEN_RETURN(false);
12730OPGEN_RETURN(true);
12731#endif
12732break;
12733break;
12734case Arg::Index:
12735#if CPU(X86_64)
12736if (!Arg::isValidImmForm(args[0].value()))
12737OPGEN_RETURN(false);
12738if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
12739OPGEN_RETURN(false);
12740OPGEN_RETURN(true);
12741#endif
12742break;
12743break;
12744default:
12745break;
12746}
12747break;
12748case Arg::Tmp:
12749switch (this->args[1].kind()) {
12750case Arg::Addr:
12751case Arg::Stack:
12752case Arg::CallArg:
12753#if CPU(X86_64)
12754if (!args[0].tmp().isGP())
12755OPGEN_RETURN(false);
12756if (!Arg::isValidAddrForm(args[1].offset()))
12757OPGEN_RETURN(false);
12758OPGEN_RETURN(true);
12759#endif
12760break;
12761break;
12762case Arg::Index:
12763#if CPU(X86_64)
12764if (!args[0].tmp().isGP())
12765OPGEN_RETURN(false);
12766if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
12767OPGEN_RETURN(false);
12768OPGEN_RETURN(true);
12769#endif
12770break;
12771break;
12772default:
12773break;
12774}
12775break;
12776default:
12777break;
12778}
12779break;
12780default:
12781break;
12782}
12783break;
12784case Opcode::AtomicSub8:
12785switch (this->args.size()) {
12786case 2:
12787switch (this->args[0].kind()) {
12788case Arg::Imm:
12789switch (this->args[1].kind()) {
12790case Arg::Addr:
12791case Arg::Stack:
12792case Arg::CallArg:
12793#if CPU(X86) || CPU(X86_64)
12794if (!Arg::isValidImmForm(args[0].value()))
12795OPGEN_RETURN(false);
12796if (!Arg::isValidAddrForm(args[1].offset()))
12797OPGEN_RETURN(false);
12798OPGEN_RETURN(true);
12799#endif
12800break;
12801break;
12802case Arg::Index:
12803#if CPU(X86) || CPU(X86_64)
12804if (!Arg::isValidImmForm(args[0].value()))
12805OPGEN_RETURN(false);
12806if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12807OPGEN_RETURN(false);
12808OPGEN_RETURN(true);
12809#endif
12810break;
12811break;
12812default:
12813break;
12814}
12815break;
12816case Arg::Tmp:
12817switch (this->args[1].kind()) {
12818case Arg::Addr:
12819case Arg::Stack:
12820case Arg::CallArg:
12821#if CPU(X86) || CPU(X86_64)
12822if (!args[0].tmp().isGP())
12823OPGEN_RETURN(false);
12824if (!Arg::isValidAddrForm(args[1].offset()))
12825OPGEN_RETURN(false);
12826OPGEN_RETURN(true);
12827#endif
12828break;
12829break;
12830case Arg::Index:
12831#if CPU(X86) || CPU(X86_64)
12832if (!args[0].tmp().isGP())
12833OPGEN_RETURN(false);
12834if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
12835OPGEN_RETURN(false);
12836OPGEN_RETURN(true);
12837#endif
12838break;
12839break;
12840default:
12841break;
12842}
12843break;
12844default:
12845break;
12846}
12847break;
12848default:
12849break;
12850}
12851break;
12852case Opcode::AtomicSub16:
12853switch (this->args.size()) {
12854case 2:
12855switch (this->args[0].kind()) {
12856case Arg::Imm:
12857switch (this->args[1].kind()) {
12858case Arg::Addr:
12859case Arg::Stack:
12860case Arg::CallArg:
12861#if CPU(X86) || CPU(X86_64)
12862if (!Arg::isValidImmForm(args[0].value()))
12863OPGEN_RETURN(false);
12864if (!Arg::isValidAddrForm(args[1].offset()))
12865OPGEN_RETURN(false);
12866OPGEN_RETURN(true);
12867#endif
12868break;
12869break;
12870case Arg::Index:
12871#if CPU(X86) || CPU(X86_64)
12872if (!Arg::isValidImmForm(args[0].value()))
12873OPGEN_RETURN(false);
12874if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12875OPGEN_RETURN(false);
12876OPGEN_RETURN(true);
12877#endif
12878break;
12879break;
12880default:
12881break;
12882}
12883break;
12884case Arg::Tmp:
12885switch (this->args[1].kind()) {
12886case Arg::Addr:
12887case Arg::Stack:
12888case Arg::CallArg:
12889#if CPU(X86) || CPU(X86_64)
12890if (!args[0].tmp().isGP())
12891OPGEN_RETURN(false);
12892if (!Arg::isValidAddrForm(args[1].offset()))
12893OPGEN_RETURN(false);
12894OPGEN_RETURN(true);
12895#endif
12896break;
12897break;
12898case Arg::Index:
12899#if CPU(X86) || CPU(X86_64)
12900if (!args[0].tmp().isGP())
12901OPGEN_RETURN(false);
12902if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
12903OPGEN_RETURN(false);
12904OPGEN_RETURN(true);
12905#endif
12906break;
12907break;
12908default:
12909break;
12910}
12911break;
12912default:
12913break;
12914}
12915break;
12916default:
12917break;
12918}
12919break;
12920case Opcode::AtomicSub32:
12921switch (this->args.size()) {
12922case 2:
12923switch (this->args[0].kind()) {
12924case Arg::Imm:
12925switch (this->args[1].kind()) {
12926case Arg::Addr:
12927case Arg::Stack:
12928case Arg::CallArg:
12929#if CPU(X86) || CPU(X86_64)
12930if (!Arg::isValidImmForm(args[0].value()))
12931OPGEN_RETURN(false);
12932if (!Arg::isValidAddrForm(args[1].offset()))
12933OPGEN_RETURN(false);
12934OPGEN_RETURN(true);
12935#endif
12936break;
12937break;
12938case Arg::Index:
12939#if CPU(X86) || CPU(X86_64)
12940if (!Arg::isValidImmForm(args[0].value()))
12941OPGEN_RETURN(false);
12942if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
12943OPGEN_RETURN(false);
12944OPGEN_RETURN(true);
12945#endif
12946break;
12947break;
12948default:
12949break;
12950}
12951break;
12952case Arg::Tmp:
12953switch (this->args[1].kind()) {
12954case Arg::Addr:
12955case Arg::Stack:
12956case Arg::CallArg:
12957#if CPU(X86) || CPU(X86_64)
12958if (!args[0].tmp().isGP())
12959OPGEN_RETURN(false);
12960if (!Arg::isValidAddrForm(args[1].offset()))
12961OPGEN_RETURN(false);
12962OPGEN_RETURN(true);
12963#endif
12964break;
12965break;
12966case Arg::Index:
12967#if CPU(X86) || CPU(X86_64)
12968if (!args[0].tmp().isGP())
12969OPGEN_RETURN(false);
12970if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
12971OPGEN_RETURN(false);
12972OPGEN_RETURN(true);
12973#endif
12974break;
12975break;
12976default:
12977break;
12978}
12979break;
12980default:
12981break;
12982}
12983break;
12984default:
12985break;
12986}
12987break;
12988case Opcode::AtomicSub64:
12989switch (this->args.size()) {
12990case 2:
12991switch (this->args[0].kind()) {
12992case Arg::Imm:
12993switch (this->args[1].kind()) {
12994case Arg::Addr:
12995case Arg::Stack:
12996case Arg::CallArg:
12997#if CPU(X86_64)
12998if (!Arg::isValidImmForm(args[0].value()))
12999OPGEN_RETURN(false);
13000if (!Arg::isValidAddrForm(args[1].offset()))
13001OPGEN_RETURN(false);
13002OPGEN_RETURN(true);
13003#endif
13004break;
13005break;
13006case Arg::Index:
13007#if CPU(X86_64)
13008if (!Arg::isValidImmForm(args[0].value()))
13009OPGEN_RETURN(false);
13010if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13011OPGEN_RETURN(false);
13012OPGEN_RETURN(true);
13013#endif
13014break;
13015break;
13016default:
13017break;
13018}
13019break;
13020case Arg::Tmp:
13021switch (this->args[1].kind()) {
13022case Arg::Addr:
13023case Arg::Stack:
13024case Arg::CallArg:
13025#if CPU(X86_64)
13026if (!args[0].tmp().isGP())
13027OPGEN_RETURN(false);
13028if (!Arg::isValidAddrForm(args[1].offset()))
13029OPGEN_RETURN(false);
13030OPGEN_RETURN(true);
13031#endif
13032break;
13033break;
13034case Arg::Index:
13035#if CPU(X86_64)
13036if (!args[0].tmp().isGP())
13037OPGEN_RETURN(false);
13038if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13039OPGEN_RETURN(false);
13040OPGEN_RETURN(true);
13041#endif
13042break;
13043break;
13044default:
13045break;
13046}
13047break;
13048default:
13049break;
13050}
13051break;
13052default:
13053break;
13054}
13055break;
13056case Opcode::AtomicAnd8:
13057switch (this->args.size()) {
13058case 2:
13059switch (this->args[0].kind()) {
13060case Arg::Imm:
13061switch (this->args[1].kind()) {
13062case Arg::Addr:
13063case Arg::Stack:
13064case Arg::CallArg:
13065#if CPU(X86) || CPU(X86_64)
13066if (!Arg::isValidImmForm(args[0].value()))
13067OPGEN_RETURN(false);
13068if (!Arg::isValidAddrForm(args[1].offset()))
13069OPGEN_RETURN(false);
13070OPGEN_RETURN(true);
13071#endif
13072break;
13073break;
13074case Arg::Index:
13075#if CPU(X86) || CPU(X86_64)
13076if (!Arg::isValidImmForm(args[0].value()))
13077OPGEN_RETURN(false);
13078if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13079OPGEN_RETURN(false);
13080OPGEN_RETURN(true);
13081#endif
13082break;
13083break;
13084default:
13085break;
13086}
13087break;
13088case Arg::Tmp:
13089switch (this->args[1].kind()) {
13090case Arg::Addr:
13091case Arg::Stack:
13092case Arg::CallArg:
13093#if CPU(X86) || CPU(X86_64)
13094if (!args[0].tmp().isGP())
13095OPGEN_RETURN(false);
13096if (!Arg::isValidAddrForm(args[1].offset()))
13097OPGEN_RETURN(false);
13098OPGEN_RETURN(true);
13099#endif
13100break;
13101break;
13102case Arg::Index:
13103#if CPU(X86) || CPU(X86_64)
13104if (!args[0].tmp().isGP())
13105OPGEN_RETURN(false);
13106if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13107OPGEN_RETURN(false);
13108OPGEN_RETURN(true);
13109#endif
13110break;
13111break;
13112default:
13113break;
13114}
13115break;
13116default:
13117break;
13118}
13119break;
13120default:
13121break;
13122}
13123break;
13124case Opcode::AtomicAnd16:
13125switch (this->args.size()) {
13126case 2:
13127switch (this->args[0].kind()) {
13128case Arg::Imm:
13129switch (this->args[1].kind()) {
13130case Arg::Addr:
13131case Arg::Stack:
13132case Arg::CallArg:
13133#if CPU(X86) || CPU(X86_64)
13134if (!Arg::isValidImmForm(args[0].value()))
13135OPGEN_RETURN(false);
13136if (!Arg::isValidAddrForm(args[1].offset()))
13137OPGEN_RETURN(false);
13138OPGEN_RETURN(true);
13139#endif
13140break;
13141break;
13142case Arg::Index:
13143#if CPU(X86) || CPU(X86_64)
13144if (!Arg::isValidImmForm(args[0].value()))
13145OPGEN_RETURN(false);
13146if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13147OPGEN_RETURN(false);
13148OPGEN_RETURN(true);
13149#endif
13150break;
13151break;
13152default:
13153break;
13154}
13155break;
13156case Arg::Tmp:
13157switch (this->args[1].kind()) {
13158case Arg::Addr:
13159case Arg::Stack:
13160case Arg::CallArg:
13161#if CPU(X86) || CPU(X86_64)
13162if (!args[0].tmp().isGP())
13163OPGEN_RETURN(false);
13164if (!Arg::isValidAddrForm(args[1].offset()))
13165OPGEN_RETURN(false);
13166OPGEN_RETURN(true);
13167#endif
13168break;
13169break;
13170case Arg::Index:
13171#if CPU(X86) || CPU(X86_64)
13172if (!args[0].tmp().isGP())
13173OPGEN_RETURN(false);
13174if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13175OPGEN_RETURN(false);
13176OPGEN_RETURN(true);
13177#endif
13178break;
13179break;
13180default:
13181break;
13182}
13183break;
13184default:
13185break;
13186}
13187break;
13188default:
13189break;
13190}
13191break;
13192case Opcode::AtomicAnd32:
13193switch (this->args.size()) {
13194case 2:
13195switch (this->args[0].kind()) {
13196case Arg::Imm:
13197switch (this->args[1].kind()) {
13198case Arg::Addr:
13199case Arg::Stack:
13200case Arg::CallArg:
13201#if CPU(X86) || CPU(X86_64)
13202if (!Arg::isValidImmForm(args[0].value()))
13203OPGEN_RETURN(false);
13204if (!Arg::isValidAddrForm(args[1].offset()))
13205OPGEN_RETURN(false);
13206OPGEN_RETURN(true);
13207#endif
13208break;
13209break;
13210case Arg::Index:
13211#if CPU(X86) || CPU(X86_64)
13212if (!Arg::isValidImmForm(args[0].value()))
13213OPGEN_RETURN(false);
13214if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13215OPGEN_RETURN(false);
13216OPGEN_RETURN(true);
13217#endif
13218break;
13219break;
13220default:
13221break;
13222}
13223break;
13224case Arg::Tmp:
13225switch (this->args[1].kind()) {
13226case Arg::Addr:
13227case Arg::Stack:
13228case Arg::CallArg:
13229#if CPU(X86) || CPU(X86_64)
13230if (!args[0].tmp().isGP())
13231OPGEN_RETURN(false);
13232if (!Arg::isValidAddrForm(args[1].offset()))
13233OPGEN_RETURN(false);
13234OPGEN_RETURN(true);
13235#endif
13236break;
13237break;
13238case Arg::Index:
13239#if CPU(X86) || CPU(X86_64)
13240if (!args[0].tmp().isGP())
13241OPGEN_RETURN(false);
13242if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13243OPGEN_RETURN(false);
13244OPGEN_RETURN(true);
13245#endif
13246break;
13247break;
13248default:
13249break;
13250}
13251break;
13252default:
13253break;
13254}
13255break;
13256default:
13257break;
13258}
13259break;
13260case Opcode::AtomicAnd64:
13261switch (this->args.size()) {
13262case 2:
13263switch (this->args[0].kind()) {
13264case Arg::Imm:
13265switch (this->args[1].kind()) {
13266case Arg::Addr:
13267case Arg::Stack:
13268case Arg::CallArg:
13269#if CPU(X86_64)
13270if (!Arg::isValidImmForm(args[0].value()))
13271OPGEN_RETURN(false);
13272if (!Arg::isValidAddrForm(args[1].offset()))
13273OPGEN_RETURN(false);
13274OPGEN_RETURN(true);
13275#endif
13276break;
13277break;
13278case Arg::Index:
13279#if CPU(X86_64)
13280if (!Arg::isValidImmForm(args[0].value()))
13281OPGEN_RETURN(false);
13282if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13283OPGEN_RETURN(false);
13284OPGEN_RETURN(true);
13285#endif
13286break;
13287break;
13288default:
13289break;
13290}
13291break;
13292case Arg::Tmp:
13293switch (this->args[1].kind()) {
13294case Arg::Addr:
13295case Arg::Stack:
13296case Arg::CallArg:
13297#if CPU(X86_64)
13298if (!args[0].tmp().isGP())
13299OPGEN_RETURN(false);
13300if (!Arg::isValidAddrForm(args[1].offset()))
13301OPGEN_RETURN(false);
13302OPGEN_RETURN(true);
13303#endif
13304break;
13305break;
13306case Arg::Index:
13307#if CPU(X86_64)
13308if (!args[0].tmp().isGP())
13309OPGEN_RETURN(false);
13310if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13311OPGEN_RETURN(false);
13312OPGEN_RETURN(true);
13313#endif
13314break;
13315break;
13316default:
13317break;
13318}
13319break;
13320default:
13321break;
13322}
13323break;
13324default:
13325break;
13326}
13327break;
13328case Opcode::AtomicOr8:
13329switch (this->args.size()) {
13330case 2:
13331switch (this->args[0].kind()) {
13332case Arg::Imm:
13333switch (this->args[1].kind()) {
13334case Arg::Addr:
13335case Arg::Stack:
13336case Arg::CallArg:
13337#if CPU(X86) || CPU(X86_64)
13338if (!Arg::isValidImmForm(args[0].value()))
13339OPGEN_RETURN(false);
13340if (!Arg::isValidAddrForm(args[1].offset()))
13341OPGEN_RETURN(false);
13342OPGEN_RETURN(true);
13343#endif
13344break;
13345break;
13346case Arg::Index:
13347#if CPU(X86) || CPU(X86_64)
13348if (!Arg::isValidImmForm(args[0].value()))
13349OPGEN_RETURN(false);
13350if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13351OPGEN_RETURN(false);
13352OPGEN_RETURN(true);
13353#endif
13354break;
13355break;
13356default:
13357break;
13358}
13359break;
13360case Arg::Tmp:
13361switch (this->args[1].kind()) {
13362case Arg::Addr:
13363case Arg::Stack:
13364case Arg::CallArg:
13365#if CPU(X86) || CPU(X86_64)
13366if (!args[0].tmp().isGP())
13367OPGEN_RETURN(false);
13368if (!Arg::isValidAddrForm(args[1].offset()))
13369OPGEN_RETURN(false);
13370OPGEN_RETURN(true);
13371#endif
13372break;
13373break;
13374case Arg::Index:
13375#if CPU(X86) || CPU(X86_64)
13376if (!args[0].tmp().isGP())
13377OPGEN_RETURN(false);
13378if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13379OPGEN_RETURN(false);
13380OPGEN_RETURN(true);
13381#endif
13382break;
13383break;
13384default:
13385break;
13386}
13387break;
13388default:
13389break;
13390}
13391break;
13392default:
13393break;
13394}
13395break;
13396case Opcode::AtomicOr16:
13397switch (this->args.size()) {
13398case 2:
13399switch (this->args[0].kind()) {
13400case Arg::Imm:
13401switch (this->args[1].kind()) {
13402case Arg::Addr:
13403case Arg::Stack:
13404case Arg::CallArg:
13405#if CPU(X86) || CPU(X86_64)
13406if (!Arg::isValidImmForm(args[0].value()))
13407OPGEN_RETURN(false);
13408if (!Arg::isValidAddrForm(args[1].offset()))
13409OPGEN_RETURN(false);
13410OPGEN_RETURN(true);
13411#endif
13412break;
13413break;
13414case Arg::Index:
13415#if CPU(X86) || CPU(X86_64)
13416if (!Arg::isValidImmForm(args[0].value()))
13417OPGEN_RETURN(false);
13418if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13419OPGEN_RETURN(false);
13420OPGEN_RETURN(true);
13421#endif
13422break;
13423break;
13424default:
13425break;
13426}
13427break;
13428case Arg::Tmp:
13429switch (this->args[1].kind()) {
13430case Arg::Addr:
13431case Arg::Stack:
13432case Arg::CallArg:
13433#if CPU(X86) || CPU(X86_64)
13434if (!args[0].tmp().isGP())
13435OPGEN_RETURN(false);
13436if (!Arg::isValidAddrForm(args[1].offset()))
13437OPGEN_RETURN(false);
13438OPGEN_RETURN(true);
13439#endif
13440break;
13441break;
13442case Arg::Index:
13443#if CPU(X86) || CPU(X86_64)
13444if (!args[0].tmp().isGP())
13445OPGEN_RETURN(false);
13446if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13447OPGEN_RETURN(false);
13448OPGEN_RETURN(true);
13449#endif
13450break;
13451break;
13452default:
13453break;
13454}
13455break;
13456default:
13457break;
13458}
13459break;
13460default:
13461break;
13462}
13463break;
13464case Opcode::AtomicOr32:
13465switch (this->args.size()) {
13466case 2:
13467switch (this->args[0].kind()) {
13468case Arg::Imm:
13469switch (this->args[1].kind()) {
13470case Arg::Addr:
13471case Arg::Stack:
13472case Arg::CallArg:
13473#if CPU(X86) || CPU(X86_64)
13474if (!Arg::isValidImmForm(args[0].value()))
13475OPGEN_RETURN(false);
13476if (!Arg::isValidAddrForm(args[1].offset()))
13477OPGEN_RETURN(false);
13478OPGEN_RETURN(true);
13479#endif
13480break;
13481break;
13482case Arg::Index:
13483#if CPU(X86) || CPU(X86_64)
13484if (!Arg::isValidImmForm(args[0].value()))
13485OPGEN_RETURN(false);
13486if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13487OPGEN_RETURN(false);
13488OPGEN_RETURN(true);
13489#endif
13490break;
13491break;
13492default:
13493break;
13494}
13495break;
13496case Arg::Tmp:
13497switch (this->args[1].kind()) {
13498case Arg::Addr:
13499case Arg::Stack:
13500case Arg::CallArg:
13501#if CPU(X86) || CPU(X86_64)
13502if (!args[0].tmp().isGP())
13503OPGEN_RETURN(false);
13504if (!Arg::isValidAddrForm(args[1].offset()))
13505OPGEN_RETURN(false);
13506OPGEN_RETURN(true);
13507#endif
13508break;
13509break;
13510case Arg::Index:
13511#if CPU(X86) || CPU(X86_64)
13512if (!args[0].tmp().isGP())
13513OPGEN_RETURN(false);
13514if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13515OPGEN_RETURN(false);
13516OPGEN_RETURN(true);
13517#endif
13518break;
13519break;
13520default:
13521break;
13522}
13523break;
13524default:
13525break;
13526}
13527break;
13528default:
13529break;
13530}
13531break;
13532case Opcode::AtomicOr64:
13533switch (this->args.size()) {
13534case 2:
13535switch (this->args[0].kind()) {
13536case Arg::Imm:
13537switch (this->args[1].kind()) {
13538case Arg::Addr:
13539case Arg::Stack:
13540case Arg::CallArg:
13541#if CPU(X86_64)
13542if (!Arg::isValidImmForm(args[0].value()))
13543OPGEN_RETURN(false);
13544if (!Arg::isValidAddrForm(args[1].offset()))
13545OPGEN_RETURN(false);
13546OPGEN_RETURN(true);
13547#endif
13548break;
13549break;
13550case Arg::Index:
13551#if CPU(X86_64)
13552if (!Arg::isValidImmForm(args[0].value()))
13553OPGEN_RETURN(false);
13554if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13555OPGEN_RETURN(false);
13556OPGEN_RETURN(true);
13557#endif
13558break;
13559break;
13560default:
13561break;
13562}
13563break;
13564case Arg::Tmp:
13565switch (this->args[1].kind()) {
13566case Arg::Addr:
13567case Arg::Stack:
13568case Arg::CallArg:
13569#if CPU(X86_64)
13570if (!args[0].tmp().isGP())
13571OPGEN_RETURN(false);
13572if (!Arg::isValidAddrForm(args[1].offset()))
13573OPGEN_RETURN(false);
13574OPGEN_RETURN(true);
13575#endif
13576break;
13577break;
13578case Arg::Index:
13579#if CPU(X86_64)
13580if (!args[0].tmp().isGP())
13581OPGEN_RETURN(false);
13582if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13583OPGEN_RETURN(false);
13584OPGEN_RETURN(true);
13585#endif
13586break;
13587break;
13588default:
13589break;
13590}
13591break;
13592default:
13593break;
13594}
13595break;
13596default:
13597break;
13598}
13599break;
13600case Opcode::AtomicXor8:
13601switch (this->args.size()) {
13602case 2:
13603switch (this->args[0].kind()) {
13604case Arg::Imm:
13605switch (this->args[1].kind()) {
13606case Arg::Addr:
13607case Arg::Stack:
13608case Arg::CallArg:
13609#if CPU(X86) || CPU(X86_64)
13610if (!Arg::isValidImmForm(args[0].value()))
13611OPGEN_RETURN(false);
13612if (!Arg::isValidAddrForm(args[1].offset()))
13613OPGEN_RETURN(false);
13614OPGEN_RETURN(true);
13615#endif
13616break;
13617break;
13618case Arg::Index:
13619#if CPU(X86) || CPU(X86_64)
13620if (!Arg::isValidImmForm(args[0].value()))
13621OPGEN_RETURN(false);
13622if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13623OPGEN_RETURN(false);
13624OPGEN_RETURN(true);
13625#endif
13626break;
13627break;
13628default:
13629break;
13630}
13631break;
13632case Arg::Tmp:
13633switch (this->args[1].kind()) {
13634case Arg::Addr:
13635case Arg::Stack:
13636case Arg::CallArg:
13637#if CPU(X86) || CPU(X86_64)
13638if (!args[0].tmp().isGP())
13639OPGEN_RETURN(false);
13640if (!Arg::isValidAddrForm(args[1].offset()))
13641OPGEN_RETURN(false);
13642OPGEN_RETURN(true);
13643#endif
13644break;
13645break;
13646case Arg::Index:
13647#if CPU(X86) || CPU(X86_64)
13648if (!args[0].tmp().isGP())
13649OPGEN_RETURN(false);
13650if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
13651OPGEN_RETURN(false);
13652OPGEN_RETURN(true);
13653#endif
13654break;
13655break;
13656default:
13657break;
13658}
13659break;
13660default:
13661break;
13662}
13663break;
13664default:
13665break;
13666}
13667break;
13668case Opcode::AtomicXor16:
13669switch (this->args.size()) {
13670case 2:
13671switch (this->args[0].kind()) {
13672case Arg::Imm:
13673switch (this->args[1].kind()) {
13674case Arg::Addr:
13675case Arg::Stack:
13676case Arg::CallArg:
13677#if CPU(X86) || CPU(X86_64)
13678if (!Arg::isValidImmForm(args[0].value()))
13679OPGEN_RETURN(false);
13680if (!Arg::isValidAddrForm(args[1].offset()))
13681OPGEN_RETURN(false);
13682OPGEN_RETURN(true);
13683#endif
13684break;
13685break;
13686case Arg::Index:
13687#if CPU(X86) || CPU(X86_64)
13688if (!Arg::isValidImmForm(args[0].value()))
13689OPGEN_RETURN(false);
13690if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13691OPGEN_RETURN(false);
13692OPGEN_RETURN(true);
13693#endif
13694break;
13695break;
13696default:
13697break;
13698}
13699break;
13700case Arg::Tmp:
13701switch (this->args[1].kind()) {
13702case Arg::Addr:
13703case Arg::Stack:
13704case Arg::CallArg:
13705#if CPU(X86) || CPU(X86_64)
13706if (!args[0].tmp().isGP())
13707OPGEN_RETURN(false);
13708if (!Arg::isValidAddrForm(args[1].offset()))
13709OPGEN_RETURN(false);
13710OPGEN_RETURN(true);
13711#endif
13712break;
13713break;
13714case Arg::Index:
13715#if CPU(X86) || CPU(X86_64)
13716if (!args[0].tmp().isGP())
13717OPGEN_RETURN(false);
13718if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
13719OPGEN_RETURN(false);
13720OPGEN_RETURN(true);
13721#endif
13722break;
13723break;
13724default:
13725break;
13726}
13727break;
13728default:
13729break;
13730}
13731break;
13732default:
13733break;
13734}
13735break;
13736case Opcode::AtomicXor32:
13737switch (this->args.size()) {
13738case 2:
13739switch (this->args[0].kind()) {
13740case Arg::Imm:
13741switch (this->args[1].kind()) {
13742case Arg::Addr:
13743case Arg::Stack:
13744case Arg::CallArg:
13745#if CPU(X86) || CPU(X86_64)
13746if (!Arg::isValidImmForm(args[0].value()))
13747OPGEN_RETURN(false);
13748if (!Arg::isValidAddrForm(args[1].offset()))
13749OPGEN_RETURN(false);
13750OPGEN_RETURN(true);
13751#endif
13752break;
13753break;
13754case Arg::Index:
13755#if CPU(X86) || CPU(X86_64)
13756if (!Arg::isValidImmForm(args[0].value()))
13757OPGEN_RETURN(false);
13758if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13759OPGEN_RETURN(false);
13760OPGEN_RETURN(true);
13761#endif
13762break;
13763break;
13764default:
13765break;
13766}
13767break;
13768case Arg::Tmp:
13769switch (this->args[1].kind()) {
13770case Arg::Addr:
13771case Arg::Stack:
13772case Arg::CallArg:
13773#if CPU(X86) || CPU(X86_64)
13774if (!args[0].tmp().isGP())
13775OPGEN_RETURN(false);
13776if (!Arg::isValidAddrForm(args[1].offset()))
13777OPGEN_RETURN(false);
13778OPGEN_RETURN(true);
13779#endif
13780break;
13781break;
13782case Arg::Index:
13783#if CPU(X86) || CPU(X86_64)
13784if (!args[0].tmp().isGP())
13785OPGEN_RETURN(false);
13786if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
13787OPGEN_RETURN(false);
13788OPGEN_RETURN(true);
13789#endif
13790break;
13791break;
13792default:
13793break;
13794}
13795break;
13796default:
13797break;
13798}
13799break;
13800default:
13801break;
13802}
13803break;
13804case Opcode::AtomicXor64:
13805switch (this->args.size()) {
13806case 2:
13807switch (this->args[0].kind()) {
13808case Arg::Imm:
13809switch (this->args[1].kind()) {
13810case Arg::Addr:
13811case Arg::Stack:
13812case Arg::CallArg:
13813#if CPU(X86_64)
13814if (!Arg::isValidImmForm(args[0].value()))
13815OPGEN_RETURN(false);
13816if (!Arg::isValidAddrForm(args[1].offset()))
13817OPGEN_RETURN(false);
13818OPGEN_RETURN(true);
13819#endif
13820break;
13821break;
13822case Arg::Index:
13823#if CPU(X86_64)
13824if (!Arg::isValidImmForm(args[0].value()))
13825OPGEN_RETURN(false);
13826if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13827OPGEN_RETURN(false);
13828OPGEN_RETURN(true);
13829#endif
13830break;
13831break;
13832default:
13833break;
13834}
13835break;
13836case Arg::Tmp:
13837switch (this->args[1].kind()) {
13838case Arg::Addr:
13839case Arg::Stack:
13840case Arg::CallArg:
13841#if CPU(X86_64)
13842if (!args[0].tmp().isGP())
13843OPGEN_RETURN(false);
13844if (!Arg::isValidAddrForm(args[1].offset()))
13845OPGEN_RETURN(false);
13846OPGEN_RETURN(true);
13847#endif
13848break;
13849break;
13850case Arg::Index:
13851#if CPU(X86_64)
13852if (!args[0].tmp().isGP())
13853OPGEN_RETURN(false);
13854if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
13855OPGEN_RETURN(false);
13856OPGEN_RETURN(true);
13857#endif
13858break;
13859break;
13860default:
13861break;
13862}
13863break;
13864default:
13865break;
13866}
13867break;
13868default:
13869break;
13870}
13871break;
13872case Opcode::AtomicNeg8:
13873switch (this->args.size()) {
13874case 1:
13875switch (this->args[0].kind()) {
13876case Arg::Addr:
13877case Arg::Stack:
13878case Arg::CallArg:
13879#if CPU(X86) || CPU(X86_64)
13880if (!Arg::isValidAddrForm(args[0].offset()))
13881OPGEN_RETURN(false);
13882OPGEN_RETURN(true);
13883#endif
13884break;
13885break;
13886case Arg::Index:
13887#if CPU(X86) || CPU(X86_64)
13888if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
13889OPGEN_RETURN(false);
13890OPGEN_RETURN(true);
13891#endif
13892break;
13893break;
13894default:
13895break;
13896}
13897break;
13898default:
13899break;
13900}
13901break;
13902case Opcode::AtomicNeg16:
13903switch (this->args.size()) {
13904case 1:
13905switch (this->args[0].kind()) {
13906case Arg::Addr:
13907case Arg::Stack:
13908case Arg::CallArg:
13909#if CPU(X86) || CPU(X86_64)
13910if (!Arg::isValidAddrForm(args[0].offset()))
13911OPGEN_RETURN(false);
13912OPGEN_RETURN(true);
13913#endif
13914break;
13915break;
13916case Arg::Index:
13917#if CPU(X86) || CPU(X86_64)
13918if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
13919OPGEN_RETURN(false);
13920OPGEN_RETURN(true);
13921#endif
13922break;
13923break;
13924default:
13925break;
13926}
13927break;
13928default:
13929break;
13930}
13931break;
13932case Opcode::AtomicNeg32:
13933switch (this->args.size()) {
13934case 1:
13935switch (this->args[0].kind()) {
13936case Arg::Addr:
13937case Arg::Stack:
13938case Arg::CallArg:
13939#if CPU(X86) || CPU(X86_64)
13940if (!Arg::isValidAddrForm(args[0].offset()))
13941OPGEN_RETURN(false);
13942OPGEN_RETURN(true);
13943#endif
13944break;
13945break;
13946case Arg::Index:
13947#if CPU(X86) || CPU(X86_64)
13948if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
13949OPGEN_RETURN(false);
13950OPGEN_RETURN(true);
13951#endif
13952break;
13953break;
13954default:
13955break;
13956}
13957break;
13958default:
13959break;
13960}
13961break;
13962case Opcode::AtomicNeg64:
13963switch (this->args.size()) {
13964case 1:
13965switch (this->args[0].kind()) {
13966case Arg::Addr:
13967case Arg::Stack:
13968case Arg::CallArg:
13969#if CPU(X86_64)
13970if (!Arg::isValidAddrForm(args[0].offset()))
13971OPGEN_RETURN(false);
13972OPGEN_RETURN(true);
13973#endif
13974break;
13975break;
13976case Arg::Index:
13977#if CPU(X86_64)
13978if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
13979OPGEN_RETURN(false);
13980OPGEN_RETURN(true);
13981#endif
13982break;
13983break;
13984default:
13985break;
13986}
13987break;
13988default:
13989break;
13990}
13991break;
13992case Opcode::AtomicNot8:
13993switch (this->args.size()) {
13994case 1:
13995switch (this->args[0].kind()) {
13996case Arg::Addr:
13997case Arg::Stack:
13998case Arg::CallArg:
13999#if CPU(X86) || CPU(X86_64)
14000if (!Arg::isValidAddrForm(args[0].offset()))
14001OPGEN_RETURN(false);
14002OPGEN_RETURN(true);
14003#endif
14004break;
14005break;
14006case Arg::Index:
14007#if CPU(X86) || CPU(X86_64)
14008if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width8))
14009OPGEN_RETURN(false);
14010OPGEN_RETURN(true);
14011#endif
14012break;
14013break;
14014default:
14015break;
14016}
14017break;
14018default:
14019break;
14020}
14021break;
14022case Opcode::AtomicNot16:
14023switch (this->args.size()) {
14024case 1:
14025switch (this->args[0].kind()) {
14026case Arg::Addr:
14027case Arg::Stack:
14028case Arg::CallArg:
14029#if CPU(X86) || CPU(X86_64)
14030if (!Arg::isValidAddrForm(args[0].offset()))
14031OPGEN_RETURN(false);
14032OPGEN_RETURN(true);
14033#endif
14034break;
14035break;
14036case Arg::Index:
14037#if CPU(X86) || CPU(X86_64)
14038if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width16))
14039OPGEN_RETURN(false);
14040OPGEN_RETURN(true);
14041#endif
14042break;
14043break;
14044default:
14045break;
14046}
14047break;
14048default:
14049break;
14050}
14051break;
14052case Opcode::AtomicNot32:
14053switch (this->args.size()) {
14054case 1:
14055switch (this->args[0].kind()) {
14056case Arg::Addr:
14057case Arg::Stack:
14058case Arg::CallArg:
14059#if CPU(X86) || CPU(X86_64)
14060if (!Arg::isValidAddrForm(args[0].offset()))
14061OPGEN_RETURN(false);
14062OPGEN_RETURN(true);
14063#endif
14064break;
14065break;
14066case Arg::Index:
14067#if CPU(X86) || CPU(X86_64)
14068if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width32))
14069OPGEN_RETURN(false);
14070OPGEN_RETURN(true);
14071#endif
14072break;
14073break;
14074default:
14075break;
14076}
14077break;
14078default:
14079break;
14080}
14081break;
14082case Opcode::AtomicNot64:
14083switch (this->args.size()) {
14084case 1:
14085switch (this->args[0].kind()) {
14086case Arg::Addr:
14087case Arg::Stack:
14088case Arg::CallArg:
14089#if CPU(X86_64)
14090if (!Arg::isValidAddrForm(args[0].offset()))
14091OPGEN_RETURN(false);
14092OPGEN_RETURN(true);
14093#endif
14094break;
14095break;
14096case Arg::Index:
14097#if CPU(X86_64)
14098if (!Arg::isValidIndexForm(args[0].scale(), args[0].offset(), Width64))
14099OPGEN_RETURN(false);
14100OPGEN_RETURN(true);
14101#endif
14102break;
14103break;
14104default:
14105break;
14106}
14107break;
14108default:
14109break;
14110}
14111break;
14112case Opcode::AtomicXchgAdd8:
14113switch (this->args.size()) {
14114case 2:
14115switch (this->args[0].kind()) {
14116case Arg::Tmp:
14117switch (this->args[1].kind()) {
14118case Arg::Addr:
14119case Arg::Stack:
14120case Arg::CallArg:
14121#if CPU(X86) || CPU(X86_64)
14122if (!args[0].tmp().isGP())
14123OPGEN_RETURN(false);
14124if (!Arg::isValidAddrForm(args[1].offset()))
14125OPGEN_RETURN(false);
14126OPGEN_RETURN(true);
14127#endif
14128break;
14129break;
14130case Arg::Index:
14131#if CPU(X86) || CPU(X86_64)
14132if (!args[0].tmp().isGP())
14133OPGEN_RETURN(false);
14134if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
14135OPGEN_RETURN(false);
14136OPGEN_RETURN(true);
14137#endif
14138break;
14139break;
14140default:
14141break;
14142}
14143break;
14144default:
14145break;
14146}
14147break;
14148default:
14149break;
14150}
14151break;
14152case Opcode::AtomicXchgAdd16:
14153switch (this->args.size()) {
14154case 2:
14155switch (this->args[0].kind()) {
14156case Arg::Tmp:
14157switch (this->args[1].kind()) {
14158case Arg::Addr:
14159case Arg::Stack:
14160case Arg::CallArg:
14161#if CPU(X86) || CPU(X86_64)
14162if (!args[0].tmp().isGP())
14163OPGEN_RETURN(false);
14164if (!Arg::isValidAddrForm(args[1].offset()))
14165OPGEN_RETURN(false);
14166OPGEN_RETURN(true);
14167#endif
14168break;
14169break;
14170case Arg::Index:
14171#if CPU(X86) || CPU(X86_64)
14172if (!args[0].tmp().isGP())
14173OPGEN_RETURN(false);
14174if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
14175OPGEN_RETURN(false);
14176OPGEN_RETURN(true);
14177#endif
14178break;
14179break;
14180default:
14181break;
14182}
14183break;
14184default:
14185break;
14186}
14187break;
14188default:
14189break;
14190}
14191break;
14192case Opcode::AtomicXchgAdd32:
14193switch (this->args.size()) {
14194case 2:
14195switch (this->args[0].kind()) {
14196case Arg::Tmp:
14197switch (this->args[1].kind()) {
14198case Arg::Addr:
14199case Arg::Stack:
14200case Arg::CallArg:
14201#if CPU(X86) || CPU(X86_64)
14202if (!args[0].tmp().isGP())
14203OPGEN_RETURN(false);
14204if (!Arg::isValidAddrForm(args[1].offset()))
14205OPGEN_RETURN(false);
14206OPGEN_RETURN(true);
14207#endif
14208break;
14209break;
14210case Arg::Index:
14211#if CPU(X86) || CPU(X86_64)
14212if (!args[0].tmp().isGP())
14213OPGEN_RETURN(false);
14214if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
14215OPGEN_RETURN(false);
14216OPGEN_RETURN(true);
14217#endif
14218break;
14219break;
14220default:
14221break;
14222}
14223break;
14224default:
14225break;
14226}
14227break;
14228default:
14229break;
14230}
14231break;
14232case Opcode::AtomicXchgAdd64:
14233switch (this->args.size()) {
14234case 2:
14235switch (this->args[0].kind()) {
14236case Arg::Tmp:
14237switch (this->args[1].kind()) {
14238case Arg::Addr:
14239case Arg::Stack:
14240case Arg::CallArg:
14241#if CPU(X86_64)
14242if (!args[0].tmp().isGP())
14243OPGEN_RETURN(false);
14244if (!Arg::isValidAddrForm(args[1].offset()))
14245OPGEN_RETURN(false);
14246OPGEN_RETURN(true);
14247#endif
14248break;
14249break;
14250case Arg::Index:
14251#if CPU(X86_64)
14252if (!args[0].tmp().isGP())
14253OPGEN_RETURN(false);
14254if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
14255OPGEN_RETURN(false);
14256OPGEN_RETURN(true);
14257#endif
14258break;
14259break;
14260default:
14261break;
14262}
14263break;
14264default:
14265break;
14266}
14267break;
14268default:
14269break;
14270}
14271break;
14272case Opcode::AtomicXchg8:
14273switch (this->args.size()) {
14274case 2:
14275switch (this->args[0].kind()) {
14276case Arg::Tmp:
14277switch (this->args[1].kind()) {
14278case Arg::Addr:
14279case Arg::Stack:
14280case Arg::CallArg:
14281#if CPU(X86) || CPU(X86_64)
14282if (!args[0].tmp().isGP())
14283OPGEN_RETURN(false);
14284if (!Arg::isValidAddrForm(args[1].offset()))
14285OPGEN_RETURN(false);
14286OPGEN_RETURN(true);
14287#endif
14288break;
14289break;
14290case Arg::Index:
14291#if CPU(X86) || CPU(X86_64)
14292if (!args[0].tmp().isGP())
14293OPGEN_RETURN(false);
14294if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
14295OPGEN_RETURN(false);
14296OPGEN_RETURN(true);
14297#endif
14298break;
14299break;
14300default:
14301break;
14302}
14303break;
14304default:
14305break;
14306}
14307break;
14308default:
14309break;
14310}
14311break;
14312case Opcode::AtomicXchg16:
14313switch (this->args.size()) {
14314case 2:
14315switch (this->args[0].kind()) {
14316case Arg::Tmp:
14317switch (this->args[1].kind()) {
14318case Arg::Addr:
14319case Arg::Stack:
14320case Arg::CallArg:
14321#if CPU(X86) || CPU(X86_64)
14322if (!args[0].tmp().isGP())
14323OPGEN_RETURN(false);
14324if (!Arg::isValidAddrForm(args[1].offset()))
14325OPGEN_RETURN(false);
14326OPGEN_RETURN(true);
14327#endif
14328break;
14329break;
14330case Arg::Index:
14331#if CPU(X86) || CPU(X86_64)
14332if (!args[0].tmp().isGP())
14333OPGEN_RETURN(false);
14334if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width16))
14335OPGEN_RETURN(false);
14336OPGEN_RETURN(true);
14337#endif
14338break;
14339break;
14340default:
14341break;
14342}
14343break;
14344default:
14345break;
14346}
14347break;
14348default:
14349break;
14350}
14351break;
14352case Opcode::AtomicXchg32:
14353switch (this->args.size()) {
14354case 2:
14355switch (this->args[0].kind()) {
14356case Arg::Tmp:
14357switch (this->args[1].kind()) {
14358case Arg::Addr:
14359case Arg::Stack:
14360case Arg::CallArg:
14361#if CPU(X86) || CPU(X86_64)
14362if (!args[0].tmp().isGP())
14363OPGEN_RETURN(false);
14364if (!Arg::isValidAddrForm(args[1].offset()))
14365OPGEN_RETURN(false);
14366OPGEN_RETURN(true);
14367#endif
14368break;
14369break;
14370case Arg::Index:
14371#if CPU(X86) || CPU(X86_64)
14372if (!args[0].tmp().isGP())
14373OPGEN_RETURN(false);
14374if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
14375OPGEN_RETURN(false);
14376OPGEN_RETURN(true);
14377#endif
14378break;
14379break;
14380default:
14381break;
14382}
14383break;
14384default:
14385break;
14386}
14387break;
14388default:
14389break;
14390}
14391break;
14392case Opcode::AtomicXchg64:
14393switch (this->args.size()) {
14394case 2:
14395switch (this->args[0].kind()) {
14396case Arg::Tmp:
14397switch (this->args[1].kind()) {
14398case Arg::Addr:
14399case Arg::Stack:
14400case Arg::CallArg:
14401#if CPU(X86_64)
14402if (!args[0].tmp().isGP())
14403OPGEN_RETURN(false);
14404if (!Arg::isValidAddrForm(args[1].offset()))
14405OPGEN_RETURN(false);
14406OPGEN_RETURN(true);
14407#endif
14408break;
14409break;
14410case Arg::Index:
14411#if CPU(X86_64)
14412if (!args[0].tmp().isGP())
14413OPGEN_RETURN(false);
14414if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
14415OPGEN_RETURN(false);
14416OPGEN_RETURN(true);
14417#endif
14418break;
14419break;
14420default:
14421break;
14422}
14423break;
14424default:
14425break;
14426}
14427break;
14428default:
14429break;
14430}
14431break;
14432case Opcode::LoadLink8:
14433switch (this->args.size()) {
14434case 2:
14435switch (this->args[0].kind()) {
14436case Arg::SimpleAddr:
14437switch (this->args[1].kind()) {
14438case Arg::Tmp:
14439#if CPU(ARM64)
14440if (!args[0].ptr().isGP())
14441OPGEN_RETURN(false);
14442if (!args[1].tmp().isGP())
14443OPGEN_RETURN(false);
14444OPGEN_RETURN(true);
14445#endif
14446break;
14447break;
14448default:
14449break;
14450}
14451break;
14452default:
14453break;
14454}
14455break;
14456default:
14457break;
14458}
14459break;
14460case Opcode::LoadLinkAcq8:
14461switch (this->args.size()) {
14462case 2:
14463switch (this->args[0].kind()) {
14464case Arg::SimpleAddr:
14465switch (this->args[1].kind()) {
14466case Arg::Tmp:
14467#if CPU(ARM64)
14468if (!args[0].ptr().isGP())
14469OPGEN_RETURN(false);
14470if (!args[1].tmp().isGP())
14471OPGEN_RETURN(false);
14472OPGEN_RETURN(true);
14473#endif
14474break;
14475break;
14476default:
14477break;
14478}
14479break;
14480default:
14481break;
14482}
14483break;
14484default:
14485break;
14486}
14487break;
14488case Opcode::StoreCond8:
14489switch (this->args.size()) {
14490case 3:
14491switch (this->args[0].kind()) {
14492case Arg::Tmp:
14493switch (this->args[1].kind()) {
14494case Arg::SimpleAddr:
14495switch (this->args[2].kind()) {
14496case Arg::Tmp:
14497#if CPU(ARM64)
14498if (!args[0].tmp().isGP())
14499OPGEN_RETURN(false);
14500if (!args[1].ptr().isGP())
14501OPGEN_RETURN(false);
14502if (!args[2].tmp().isGP())
14503OPGEN_RETURN(false);
14504OPGEN_RETURN(true);
14505#endif
14506break;
14507break;
14508default:
14509break;
14510}
14511break;
14512default:
14513break;
14514}
14515break;
14516default:
14517break;
14518}
14519break;
14520default:
14521break;
14522}
14523break;
14524case Opcode::StoreCondRel8:
14525switch (this->args.size()) {
14526case 3:
14527switch (this->args[0].kind()) {
14528case Arg::Tmp:
14529switch (this->args[1].kind()) {
14530case Arg::SimpleAddr:
14531switch (this->args[2].kind()) {
14532case Arg::Tmp:
14533#if CPU(ARM64)
14534if (!args[0].tmp().isGP())
14535OPGEN_RETURN(false);
14536if (!args[1].ptr().isGP())
14537OPGEN_RETURN(false);
14538if (!args[2].tmp().isGP())
14539OPGEN_RETURN(false);
14540OPGEN_RETURN(true);
14541#endif
14542break;
14543break;
14544default:
14545break;
14546}
14547break;
14548default:
14549break;
14550}
14551break;
14552default:
14553break;
14554}
14555break;
14556default:
14557break;
14558}
14559break;
14560case Opcode::LoadLink16:
14561switch (this->args.size()) {
14562case 2:
14563switch (this->args[0].kind()) {
14564case Arg::SimpleAddr:
14565switch (this->args[1].kind()) {
14566case Arg::Tmp:
14567#if CPU(ARM64)
14568if (!args[0].ptr().isGP())
14569OPGEN_RETURN(false);
14570if (!args[1].tmp().isGP())
14571OPGEN_RETURN(false);
14572OPGEN_RETURN(true);
14573#endif
14574break;
14575break;
14576default:
14577break;
14578}
14579break;
14580default:
14581break;
14582}
14583break;
14584default:
14585break;
14586}
14587break;
14588case Opcode::LoadLinkAcq16:
14589switch (this->args.size()) {
14590case 2:
14591switch (this->args[0].kind()) {
14592case Arg::SimpleAddr:
14593switch (this->args[1].kind()) {
14594case Arg::Tmp:
14595#if CPU(ARM64)
14596if (!args[0].ptr().isGP())
14597OPGEN_RETURN(false);
14598if (!args[1].tmp().isGP())
14599OPGEN_RETURN(false);
14600OPGEN_RETURN(true);
14601#endif
14602break;
14603break;
14604default:
14605break;
14606}
14607break;
14608default:
14609break;
14610}
14611break;
14612default:
14613break;
14614}
14615break;
14616case Opcode::StoreCond16:
14617switch (this->args.size()) {
14618case 3:
14619switch (this->args[0].kind()) {
14620case Arg::Tmp:
14621switch (this->args[1].kind()) {
14622case Arg::SimpleAddr:
14623switch (this->args[2].kind()) {
14624case Arg::Tmp:
14625#if CPU(ARM64)
14626if (!args[0].tmp().isGP())
14627OPGEN_RETURN(false);
14628if (!args[1].ptr().isGP())
14629OPGEN_RETURN(false);
14630if (!args[2].tmp().isGP())
14631OPGEN_RETURN(false);
14632OPGEN_RETURN(true);
14633#endif
14634break;
14635break;
14636default:
14637break;
14638}
14639break;
14640default:
14641break;
14642}
14643break;
14644default:
14645break;
14646}
14647break;
14648default:
14649break;
14650}
14651break;
14652case Opcode::StoreCondRel16:
14653switch (this->args.size()) {
14654case 3:
14655switch (this->args[0].kind()) {
14656case Arg::Tmp:
14657switch (this->args[1].kind()) {
14658case Arg::SimpleAddr:
14659switch (this->args[2].kind()) {
14660case Arg::Tmp:
14661#if CPU(ARM64)
14662if (!args[0].tmp().isGP())
14663OPGEN_RETURN(false);
14664if (!args[1].ptr().isGP())
14665OPGEN_RETURN(false);
14666if (!args[2].tmp().isGP())
14667OPGEN_RETURN(false);
14668OPGEN_RETURN(true);
14669#endif
14670break;
14671break;
14672default:
14673break;
14674}
14675break;
14676default:
14677break;
14678}
14679break;
14680default:
14681break;
14682}
14683break;
14684default:
14685break;
14686}
14687break;
14688case Opcode::LoadLink32:
14689switch (this->args.size()) {
14690case 2:
14691switch (this->args[0].kind()) {
14692case Arg::SimpleAddr:
14693switch (this->args[1].kind()) {
14694case Arg::Tmp:
14695#if CPU(ARM64)
14696if (!args[0].ptr().isGP())
14697OPGEN_RETURN(false);
14698if (!args[1].tmp().isGP())
14699OPGEN_RETURN(false);
14700OPGEN_RETURN(true);
14701#endif
14702break;
14703break;
14704default:
14705break;
14706}
14707break;
14708default:
14709break;
14710}
14711break;
14712default:
14713break;
14714}
14715break;
14716case Opcode::LoadLinkAcq32:
14717switch (this->args.size()) {
14718case 2:
14719switch (this->args[0].kind()) {
14720case Arg::SimpleAddr:
14721switch (this->args[1].kind()) {
14722case Arg::Tmp:
14723#if CPU(ARM64)
14724if (!args[0].ptr().isGP())
14725OPGEN_RETURN(false);
14726if (!args[1].tmp().isGP())
14727OPGEN_RETURN(false);
14728OPGEN_RETURN(true);
14729#endif
14730break;
14731break;
14732default:
14733break;
14734}
14735break;
14736default:
14737break;
14738}
14739break;
14740default:
14741break;
14742}
14743break;
14744case Opcode::StoreCond32:
14745switch (this->args.size()) {
14746case 3:
14747switch (this->args[0].kind()) {
14748case Arg::Tmp:
14749switch (this->args[1].kind()) {
14750case Arg::SimpleAddr:
14751switch (this->args[2].kind()) {
14752case Arg::Tmp:
14753#if CPU(ARM64)
14754if (!args[0].tmp().isGP())
14755OPGEN_RETURN(false);
14756if (!args[1].ptr().isGP())
14757OPGEN_RETURN(false);
14758if (!args[2].tmp().isGP())
14759OPGEN_RETURN(false);
14760OPGEN_RETURN(true);
14761#endif
14762break;
14763break;
14764default:
14765break;
14766}
14767break;
14768default:
14769break;
14770}
14771break;
14772default:
14773break;
14774}
14775break;
14776default:
14777break;
14778}
14779break;
14780case Opcode::StoreCondRel32:
14781switch (this->args.size()) {
14782case 3:
14783switch (this->args[0].kind()) {
14784case Arg::Tmp:
14785switch (this->args[1].kind()) {
14786case Arg::SimpleAddr:
14787switch (this->args[2].kind()) {
14788case Arg::Tmp:
14789#if CPU(ARM64)
14790if (!args[0].tmp().isGP())
14791OPGEN_RETURN(false);
14792if (!args[1].ptr().isGP())
14793OPGEN_RETURN(false);
14794if (!args[2].tmp().isGP())
14795OPGEN_RETURN(false);
14796OPGEN_RETURN(true);
14797#endif
14798break;
14799break;
14800default:
14801break;
14802}
14803break;
14804default:
14805break;
14806}
14807break;
14808default:
14809break;
14810}
14811break;
14812default:
14813break;
14814}
14815break;
14816case Opcode::LoadLink64:
14817switch (this->args.size()) {
14818case 2:
14819switch (this->args[0].kind()) {
14820case Arg::SimpleAddr:
14821switch (this->args[1].kind()) {
14822case Arg::Tmp:
14823#if CPU(ARM64)
14824if (!args[0].ptr().isGP())
14825OPGEN_RETURN(false);
14826if (!args[1].tmp().isGP())
14827OPGEN_RETURN(false);
14828OPGEN_RETURN(true);
14829#endif
14830break;
14831break;
14832default:
14833break;
14834}
14835break;
14836default:
14837break;
14838}
14839break;
14840default:
14841break;
14842}
14843break;
14844case Opcode::LoadLinkAcq64:
14845switch (this->args.size()) {
14846case 2:
14847switch (this->args[0].kind()) {
14848case Arg::SimpleAddr:
14849switch (this->args[1].kind()) {
14850case Arg::Tmp:
14851#if CPU(ARM64)
14852if (!args[0].ptr().isGP())
14853OPGEN_RETURN(false);
14854if (!args[1].tmp().isGP())
14855OPGEN_RETURN(false);
14856OPGEN_RETURN(true);
14857#endif
14858break;
14859break;
14860default:
14861break;
14862}
14863break;
14864default:
14865break;
14866}
14867break;
14868default:
14869break;
14870}
14871break;
14872case Opcode::StoreCond64:
14873switch (this->args.size()) {
14874case 3:
14875switch (this->args[0].kind()) {
14876case Arg::Tmp:
14877switch (this->args[1].kind()) {
14878case Arg::SimpleAddr:
14879switch (this->args[2].kind()) {
14880case Arg::Tmp:
14881#if CPU(ARM64)
14882if (!args[0].tmp().isGP())
14883OPGEN_RETURN(false);
14884if (!args[1].ptr().isGP())
14885OPGEN_RETURN(false);
14886if (!args[2].tmp().isGP())
14887OPGEN_RETURN(false);
14888OPGEN_RETURN(true);
14889#endif
14890break;
14891break;
14892default:
14893break;
14894}
14895break;
14896default:
14897break;
14898}
14899break;
14900default:
14901break;
14902}
14903break;
14904default:
14905break;
14906}
14907break;
14908case Opcode::StoreCondRel64:
14909switch (this->args.size()) {
14910case 3:
14911switch (this->args[0].kind()) {
14912case Arg::Tmp:
14913switch (this->args[1].kind()) {
14914case Arg::SimpleAddr:
14915switch (this->args[2].kind()) {
14916case Arg::Tmp:
14917#if CPU(ARM64)
14918if (!args[0].tmp().isGP())
14919OPGEN_RETURN(false);
14920if (!args[1].ptr().isGP())
14921OPGEN_RETURN(false);
14922if (!args[2].tmp().isGP())
14923OPGEN_RETURN(false);
14924OPGEN_RETURN(true);
14925#endif
14926break;
14927break;
14928default:
14929break;
14930}
14931break;
14932default:
14933break;
14934}
14935break;
14936default:
14937break;
14938}
14939break;
14940default:
14941break;
14942}
14943break;
14944case Opcode::Depend32:
14945switch (this->args.size()) {
14946case 2:
14947switch (this->args[0].kind()) {
14948case Arg::Tmp:
14949switch (this->args[1].kind()) {
14950case Arg::Tmp:
14951#if CPU(ARM64)
14952if (!args[0].tmp().isGP())
14953OPGEN_RETURN(false);
14954if (!args[1].tmp().isGP())
14955OPGEN_RETURN(false);
14956OPGEN_RETURN(true);
14957#endif
14958break;
14959break;
14960default:
14961break;
14962}
14963break;
14964default:
14965break;
14966}
14967break;
14968default:
14969break;
14970}
14971break;
14972case Opcode::Depend64:
14973switch (this->args.size()) {
14974case 2:
14975switch (this->args[0].kind()) {
14976case Arg::Tmp:
14977switch (this->args[1].kind()) {
14978case Arg::Tmp:
14979#if CPU(ARM64)
14980if (!args[0].tmp().isGP())
14981OPGEN_RETURN(false);
14982if (!args[1].tmp().isGP())
14983OPGEN_RETURN(false);
14984OPGEN_RETURN(true);
14985#endif
14986break;
14987break;
14988default:
14989break;
14990}
14991break;
14992default:
14993break;
14994}
14995break;
14996default:
14997break;
14998}
14999break;
15000case Opcode::Compare32:
15001switch (this->args.size()) {
15002case 4:
15003switch (this->args[0].kind()) {
15004case Arg::RelCond:
15005switch (this->args[1].kind()) {
15006case Arg::Tmp:
15007switch (this->args[2].kind()) {
15008case Arg::Tmp:
15009switch (this->args[3].kind()) {
15010case Arg::Tmp:
15011if (!args[1].tmp().isGP())
15012OPGEN_RETURN(false);
15013if (!args[2].tmp().isGP())
15014OPGEN_RETURN(false);
15015if (!args[3].tmp().isGP())
15016OPGEN_RETURN(false);
15017OPGEN_RETURN(true);
15018break;
15019break;
15020default:
15021break;
15022}
15023break;
15024case Arg::Imm:
15025switch (this->args[3].kind()) {
15026case Arg::Tmp:
15027if (!args[1].tmp().isGP())
15028OPGEN_RETURN(false);
15029if (!Arg::isValidImmForm(args[2].value()))
15030OPGEN_RETURN(false);
15031if (!args[3].tmp().isGP())
15032OPGEN_RETURN(false);
15033OPGEN_RETURN(true);
15034break;
15035break;
15036default:
15037break;
15038}
15039break;
15040default:
15041break;
15042}
15043break;
15044default:
15045break;
15046}
15047break;
15048default:
15049break;
15050}
15051break;
15052default:
15053break;
15054}
15055break;
15056case Opcode::Compare64:
15057switch (this->args.size()) {
15058case 4:
15059switch (this->args[0].kind()) {
15060case Arg::RelCond:
15061switch (this->args[1].kind()) {
15062case Arg::Tmp:
15063switch (this->args[2].kind()) {
15064case Arg::Tmp:
15065switch (this->args[3].kind()) {
15066case Arg::Tmp:
15067#if CPU(X86_64) || CPU(ARM64)
15068if (!args[1].tmp().isGP())
15069OPGEN_RETURN(false);
15070if (!args[2].tmp().isGP())
15071OPGEN_RETURN(false);
15072if (!args[3].tmp().isGP())
15073OPGEN_RETURN(false);
15074OPGEN_RETURN(true);
15075#endif
15076break;
15077break;
15078default:
15079break;
15080}
15081break;
15082case Arg::Imm:
15083switch (this->args[3].kind()) {
15084case Arg::Tmp:
15085#if CPU(X86_64)
15086if (!args[1].tmp().isGP())
15087OPGEN_RETURN(false);
15088if (!Arg::isValidImmForm(args[2].value()))
15089OPGEN_RETURN(false);
15090if (!args[3].tmp().isGP())
15091OPGEN_RETURN(false);
15092OPGEN_RETURN(true);
15093#endif
15094break;
15095break;
15096default:
15097break;
15098}
15099break;
15100default:
15101break;
15102}
15103break;
15104default:
15105break;
15106}
15107break;
15108default:
15109break;
15110}
15111break;
15112default:
15113break;
15114}
15115break;
15116case Opcode::Test32:
15117switch (this->args.size()) {
15118case 4:
15119switch (this->args[0].kind()) {
15120case Arg::ResCond:
15121switch (this->args[1].kind()) {
15122case Arg::Addr:
15123case Arg::Stack:
15124case Arg::CallArg:
15125switch (this->args[2].kind()) {
15126case Arg::Imm:
15127switch (this->args[3].kind()) {
15128case Arg::Tmp:
15129#if CPU(X86) || CPU(X86_64)
15130if (!Arg::isValidAddrForm(args[1].offset()))
15131OPGEN_RETURN(false);
15132if (!Arg::isValidImmForm(args[2].value()))
15133OPGEN_RETURN(false);
15134if (!args[3].tmp().isGP())
15135OPGEN_RETURN(false);
15136OPGEN_RETURN(true);
15137#endif
15138break;
15139break;
15140default:
15141break;
15142}
15143break;
15144default:
15145break;
15146}
15147break;
15148case Arg::Tmp:
15149switch (this->args[2].kind()) {
15150case Arg::Tmp:
15151switch (this->args[3].kind()) {
15152case Arg::Tmp:
15153if (!args[1].tmp().isGP())
15154OPGEN_RETURN(false);
15155if (!args[2].tmp().isGP())
15156OPGEN_RETURN(false);
15157if (!args[3].tmp().isGP())
15158OPGEN_RETURN(false);
15159OPGEN_RETURN(true);
15160break;
15161break;
15162default:
15163break;
15164}
15165break;
15166case Arg::BitImm:
15167switch (this->args[3].kind()) {
15168case Arg::Tmp:
15169if (!args[1].tmp().isGP())
15170OPGEN_RETURN(false);
15171if (!Arg::isValidBitImmForm(args[2].value()))
15172OPGEN_RETURN(false);
15173if (!args[3].tmp().isGP())
15174OPGEN_RETURN(false);
15175OPGEN_RETURN(true);
15176break;
15177break;
15178default:
15179break;
15180}
15181break;
15182default:
15183break;
15184}
15185break;
15186default:
15187break;
15188}
15189break;
15190default:
15191break;
15192}
15193break;
15194default:
15195break;
15196}
15197break;
15198case Opcode::Test64:
15199switch (this->args.size()) {
15200case 4:
15201switch (this->args[0].kind()) {
15202case Arg::ResCond:
15203switch (this->args[1].kind()) {
15204case Arg::Tmp:
15205switch (this->args[2].kind()) {
15206case Arg::Imm:
15207switch (this->args[3].kind()) {
15208case Arg::Tmp:
15209#if CPU(X86_64)
15210if (!args[1].tmp().isGP())
15211OPGEN_RETURN(false);
15212if (!Arg::isValidImmForm(args[2].value()))
15213OPGEN_RETURN(false);
15214if (!args[3].tmp().isGP())
15215OPGEN_RETURN(false);
15216OPGEN_RETURN(true);
15217#endif
15218break;
15219break;
15220default:
15221break;
15222}
15223break;
15224case Arg::Tmp:
15225switch (this->args[3].kind()) {
15226case Arg::Tmp:
15227#if CPU(X86_64) || CPU(ARM64)
15228if (!args[1].tmp().isGP())
15229OPGEN_RETURN(false);
15230if (!args[2].tmp().isGP())
15231OPGEN_RETURN(false);
15232if (!args[3].tmp().isGP())
15233OPGEN_RETURN(false);
15234OPGEN_RETURN(true);
15235#endif
15236break;
15237break;
15238default:
15239break;
15240}
15241break;
15242default:
15243break;
15244}
15245break;
15246default:
15247break;
15248}
15249break;
15250default:
15251break;
15252}
15253break;
15254default:
15255break;
15256}
15257break;
15258case Opcode::CompareDouble:
15259switch (this->args.size()) {
15260case 4:
15261switch (this->args[0].kind()) {
15262case Arg::DoubleCond:
15263switch (this->args[1].kind()) {
15264case Arg::Tmp:
15265switch (this->args[2].kind()) {
15266case Arg::Tmp:
15267switch (this->args[3].kind()) {
15268case Arg::Tmp:
15269if (!args[1].tmp().isFP())
15270OPGEN_RETURN(false);
15271if (!args[2].tmp().isFP())
15272OPGEN_RETURN(false);
15273if (!args[3].tmp().isGP())
15274OPGEN_RETURN(false);
15275OPGEN_RETURN(true);
15276break;
15277break;
15278default:
15279break;
15280}
15281break;
15282default:
15283break;
15284}
15285break;
15286default:
15287break;
15288}
15289break;
15290default:
15291break;
15292}
15293break;
15294default:
15295break;
15296}
15297break;
15298case Opcode::CompareFloat:
15299switch (this->args.size()) {
15300case 4:
15301switch (this->args[0].kind()) {
15302case Arg::DoubleCond:
15303switch (this->args[1].kind()) {
15304case Arg::Tmp:
15305switch (this->args[2].kind()) {
15306case Arg::Tmp:
15307switch (this->args[3].kind()) {
15308case Arg::Tmp:
15309if (!args[1].tmp().isFP())
15310OPGEN_RETURN(false);
15311if (!args[2].tmp().isFP())
15312OPGEN_RETURN(false);
15313if (!args[3].tmp().isGP())
15314OPGEN_RETURN(false);
15315OPGEN_RETURN(true);
15316break;
15317break;
15318default:
15319break;
15320}
15321break;
15322default:
15323break;
15324}
15325break;
15326default:
15327break;
15328}
15329break;
15330default:
15331break;
15332}
15333break;
15334default:
15335break;
15336}
15337break;
15338case Opcode::Branch8:
15339switch (this->args.size()) {
15340case 3:
15341switch (this->args[0].kind()) {
15342case Arg::RelCond:
15343switch (this->args[1].kind()) {
15344case Arg::Addr:
15345case Arg::Stack:
15346case Arg::CallArg:
15347switch (this->args[2].kind()) {
15348case Arg::Imm:
15349#if CPU(X86) || CPU(X86_64)
15350if (!Arg::isValidAddrForm(args[1].offset()))
15351OPGEN_RETURN(false);
15352if (!Arg::isValidImmForm(args[2].value()))
15353OPGEN_RETURN(false);
15354OPGEN_RETURN(true);
15355#endif
15356break;
15357break;
15358default:
15359break;
15360}
15361break;
15362case Arg::Index:
15363switch (this->args[2].kind()) {
15364case Arg::Imm:
15365#if CPU(X86) || CPU(X86_64)
15366if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
15367OPGEN_RETURN(false);
15368if (!Arg::isValidImmForm(args[2].value()))
15369OPGEN_RETURN(false);
15370OPGEN_RETURN(true);
15371#endif
15372break;
15373break;
15374default:
15375break;
15376}
15377break;
15378default:
15379break;
15380}
15381break;
15382default:
15383break;
15384}
15385break;
15386default:
15387break;
15388}
15389break;
15390case Opcode::Branch32:
15391switch (this->args.size()) {
15392case 3:
15393switch (this->args[0].kind()) {
15394case Arg::RelCond:
15395switch (this->args[1].kind()) {
15396case Arg::Addr:
15397case Arg::Stack:
15398case Arg::CallArg:
15399switch (this->args[2].kind()) {
15400case Arg::Imm:
15401#if CPU(X86) || CPU(X86_64)
15402if (!Arg::isValidAddrForm(args[1].offset()))
15403OPGEN_RETURN(false);
15404if (!Arg::isValidImmForm(args[2].value()))
15405OPGEN_RETURN(false);
15406OPGEN_RETURN(true);
15407#endif
15408break;
15409break;
15410case Arg::Tmp:
15411#if CPU(X86) || CPU(X86_64)
15412if (!Arg::isValidAddrForm(args[1].offset()))
15413OPGEN_RETURN(false);
15414if (!args[2].tmp().isGP())
15415OPGEN_RETURN(false);
15416OPGEN_RETURN(true);
15417#endif
15418break;
15419break;
15420default:
15421break;
15422}
15423break;
15424case Arg::Tmp:
15425switch (this->args[2].kind()) {
15426case Arg::Tmp:
15427if (!args[1].tmp().isGP())
15428OPGEN_RETURN(false);
15429if (!args[2].tmp().isGP())
15430OPGEN_RETURN(false);
15431OPGEN_RETURN(true);
15432break;
15433break;
15434case Arg::Imm:
15435if (!args[1].tmp().isGP())
15436OPGEN_RETURN(false);
15437if (!Arg::isValidImmForm(args[2].value()))
15438OPGEN_RETURN(false);
15439OPGEN_RETURN(true);
15440break;
15441break;
15442case Arg::Addr:
15443case Arg::Stack:
15444case Arg::CallArg:
15445#if CPU(X86) || CPU(X86_64)
15446if (!args[1].tmp().isGP())
15447OPGEN_RETURN(false);
15448if (!Arg::isValidAddrForm(args[2].offset()))
15449OPGEN_RETURN(false);
15450OPGEN_RETURN(true);
15451#endif
15452break;
15453break;
15454default:
15455break;
15456}
15457break;
15458case Arg::Index:
15459switch (this->args[2].kind()) {
15460case Arg::Imm:
15461#if CPU(X86) || CPU(X86_64)
15462if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
15463OPGEN_RETURN(false);
15464if (!Arg::isValidImmForm(args[2].value()))
15465OPGEN_RETURN(false);
15466OPGEN_RETURN(true);
15467#endif
15468break;
15469break;
15470default:
15471break;
15472}
15473break;
15474default:
15475break;
15476}
15477break;
15478default:
15479break;
15480}
15481break;
15482default:
15483break;
15484}
15485break;
15486case Opcode::Branch64:
15487switch (this->args.size()) {
15488case 3:
15489switch (this->args[0].kind()) {
15490case Arg::RelCond:
15491switch (this->args[1].kind()) {
15492case Arg::Tmp:
15493switch (this->args[2].kind()) {
15494case Arg::Tmp:
15495#if CPU(X86_64) || CPU(ARM64)
15496if (!args[1].tmp().isGP())
15497OPGEN_RETURN(false);
15498if (!args[2].tmp().isGP())
15499OPGEN_RETURN(false);
15500OPGEN_RETURN(true);
15501#endif
15502break;
15503break;
15504case Arg::Imm:
15505#if CPU(X86_64) || CPU(ARM64)
15506if (!args[1].tmp().isGP())
15507OPGEN_RETURN(false);
15508if (!Arg::isValidImmForm(args[2].value()))
15509OPGEN_RETURN(false);
15510OPGEN_RETURN(true);
15511#endif
15512break;
15513break;
15514case Arg::Addr:
15515case Arg::Stack:
15516case Arg::CallArg:
15517#if CPU(X86_64)
15518if (!args[1].tmp().isGP())
15519OPGEN_RETURN(false);
15520if (!Arg::isValidAddrForm(args[2].offset()))
15521OPGEN_RETURN(false);
15522OPGEN_RETURN(true);
15523#endif
15524break;
15525break;
15526default:
15527break;
15528}
15529break;
15530case Arg::Addr:
15531case Arg::Stack:
15532case Arg::CallArg:
15533switch (this->args[2].kind()) {
15534case Arg::Tmp:
15535#if CPU(X86_64)
15536if (!Arg::isValidAddrForm(args[1].offset()))
15537OPGEN_RETURN(false);
15538if (!args[2].tmp().isGP())
15539OPGEN_RETURN(false);
15540OPGEN_RETURN(true);
15541#endif
15542break;
15543break;
15544case Arg::Imm:
15545#if CPU(X86_64)
15546if (!Arg::isValidAddrForm(args[1].offset()))
15547OPGEN_RETURN(false);
15548if (!Arg::isValidImmForm(args[2].value()))
15549OPGEN_RETURN(false);
15550OPGEN_RETURN(true);
15551#endif
15552break;
15553break;
15554default:
15555break;
15556}
15557break;
15558case Arg::Index:
15559switch (this->args[2].kind()) {
15560case Arg::Tmp:
15561#if CPU(X86_64)
15562if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
15563OPGEN_RETURN(false);
15564if (!args[2].tmp().isGP())
15565OPGEN_RETURN(false);
15566OPGEN_RETURN(true);
15567#endif
15568break;
15569break;
15570default:
15571break;
15572}
15573break;
15574default:
15575break;
15576}
15577break;
15578default:
15579break;
15580}
15581break;
15582default:
15583break;
15584}
15585break;
15586case Opcode::BranchTest8:
15587switch (this->args.size()) {
15588case 3:
15589switch (this->args[0].kind()) {
15590case Arg::ResCond:
15591switch (this->args[1].kind()) {
15592case Arg::Addr:
15593case Arg::Stack:
15594case Arg::CallArg:
15595switch (this->args[2].kind()) {
15596case Arg::BitImm:
15597#if CPU(X86) || CPU(X86_64)
15598if (!Arg::isValidAddrForm(args[1].offset()))
15599OPGEN_RETURN(false);
15600if (!Arg::isValidBitImmForm(args[2].value()))
15601OPGEN_RETURN(false);
15602OPGEN_RETURN(true);
15603#endif
15604break;
15605break;
15606default:
15607break;
15608}
15609break;
15610case Arg::Index:
15611switch (this->args[2].kind()) {
15612case Arg::BitImm:
15613#if CPU(X86) || CPU(X86_64)
15614if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width8))
15615OPGEN_RETURN(false);
15616if (!Arg::isValidBitImmForm(args[2].value()))
15617OPGEN_RETURN(false);
15618OPGEN_RETURN(true);
15619#endif
15620break;
15621break;
15622default:
15623break;
15624}
15625break;
15626default:
15627break;
15628}
15629break;
15630default:
15631break;
15632}
15633break;
15634default:
15635break;
15636}
15637break;
15638case Opcode::BranchTest32:
15639switch (this->args.size()) {
15640case 3:
15641switch (this->args[0].kind()) {
15642case Arg::ResCond:
15643switch (this->args[1].kind()) {
15644case Arg::Tmp:
15645switch (this->args[2].kind()) {
15646case Arg::Tmp:
15647if (!args[1].tmp().isGP())
15648OPGEN_RETURN(false);
15649if (!args[2].tmp().isGP())
15650OPGEN_RETURN(false);
15651OPGEN_RETURN(true);
15652break;
15653break;
15654case Arg::BitImm:
15655if (!args[1].tmp().isGP())
15656OPGEN_RETURN(false);
15657if (!Arg::isValidBitImmForm(args[2].value()))
15658OPGEN_RETURN(false);
15659OPGEN_RETURN(true);
15660break;
15661break;
15662default:
15663break;
15664}
15665break;
15666case Arg::Addr:
15667case Arg::Stack:
15668case Arg::CallArg:
15669switch (this->args[2].kind()) {
15670case Arg::BitImm:
15671#if CPU(X86) || CPU(X86_64)
15672if (!Arg::isValidAddrForm(args[1].offset()))
15673OPGEN_RETURN(false);
15674if (!Arg::isValidBitImmForm(args[2].value()))
15675OPGEN_RETURN(false);
15676OPGEN_RETURN(true);
15677#endif
15678break;
15679break;
15680default:
15681break;
15682}
15683break;
15684case Arg::Index:
15685switch (this->args[2].kind()) {
15686case Arg::BitImm:
15687#if CPU(X86) || CPU(X86_64)
15688if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
15689OPGEN_RETURN(false);
15690if (!Arg::isValidBitImmForm(args[2].value()))
15691OPGEN_RETURN(false);
15692OPGEN_RETURN(true);
15693#endif
15694break;
15695break;
15696default:
15697break;
15698}
15699break;
15700default:
15701break;
15702}
15703break;
15704default:
15705break;
15706}
15707break;
15708default:
15709break;
15710}
15711break;
15712case Opcode::BranchTest64:
15713switch (this->args.size()) {
15714case 3:
15715switch (this->args[0].kind()) {
15716case Arg::ResCond:
15717switch (this->args[1].kind()) {
15718case Arg::Tmp:
15719switch (this->args[2].kind()) {
15720case Arg::Tmp:
15721#if CPU(X86_64) || CPU(ARM64)
15722if (!args[1].tmp().isGP())
15723OPGEN_RETURN(false);
15724if (!args[2].tmp().isGP())
15725OPGEN_RETURN(false);
15726OPGEN_RETURN(true);
15727#endif
15728break;
15729break;
15730#if USE(JSVALUE64)
15731case Arg::BitImm64:
15732#if CPU(ARM64)
15733if (!args[1].tmp().isGP())
15734OPGEN_RETURN(false);
15735if (!Arg::isValidBitImm64Form(args[2].value()))
15736OPGEN_RETURN(false);
15737OPGEN_RETURN(true);
15738#endif
15739break;
15740break;
15741#endif // USE(JSVALUE64)
15742case Arg::BitImm:
15743#if CPU(X86_64)
15744if (!args[1].tmp().isGP())
15745OPGEN_RETURN(false);
15746if (!Arg::isValidBitImmForm(args[2].value()))
15747OPGEN_RETURN(false);
15748OPGEN_RETURN(true);
15749#endif
15750break;
15751break;
15752default:
15753break;
15754}
15755break;
15756case Arg::Addr:
15757case Arg::Stack:
15758case Arg::CallArg:
15759switch (this->args[2].kind()) {
15760case Arg::BitImm:
15761#if CPU(X86_64)
15762if (!Arg::isValidAddrForm(args[1].offset()))
15763OPGEN_RETURN(false);
15764if (!Arg::isValidBitImmForm(args[2].value()))
15765OPGEN_RETURN(false);
15766OPGEN_RETURN(true);
15767#endif
15768break;
15769break;
15770case Arg::Tmp:
15771#if CPU(X86_64)
15772if (!Arg::isValidAddrForm(args[1].offset()))
15773OPGEN_RETURN(false);
15774if (!args[2].tmp().isGP())
15775OPGEN_RETURN(false);
15776OPGEN_RETURN(true);
15777#endif
15778break;
15779break;
15780default:
15781break;
15782}
15783break;
15784case Arg::Index:
15785switch (this->args[2].kind()) {
15786case Arg::BitImm:
15787#if CPU(X86_64)
15788if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
15789OPGEN_RETURN(false);
15790if (!Arg::isValidBitImmForm(args[2].value()))
15791OPGEN_RETURN(false);
15792OPGEN_RETURN(true);
15793#endif
15794break;
15795break;
15796default:
15797break;
15798}
15799break;
15800default:
15801break;
15802}
15803break;
15804default:
15805break;
15806}
15807break;
15808default:
15809break;
15810}
15811break;
15812case Opcode::BranchDouble:
15813switch (this->args.size()) {
15814case 3:
15815switch (this->args[0].kind()) {
15816case Arg::DoubleCond:
15817switch (this->args[1].kind()) {
15818case Arg::Tmp:
15819switch (this->args[2].kind()) {
15820case Arg::Tmp:
15821if (!args[1].tmp().isFP())
15822OPGEN_RETURN(false);
15823if (!args[2].tmp().isFP())
15824OPGEN_RETURN(false);
15825OPGEN_RETURN(true);
15826break;
15827break;
15828default:
15829break;
15830}
15831break;
15832default:
15833break;
15834}
15835break;
15836default:
15837break;
15838}
15839break;
15840default:
15841break;
15842}
15843break;
15844case Opcode::BranchFloat:
15845switch (this->args.size()) {
15846case 3:
15847switch (this->args[0].kind()) {
15848case Arg::DoubleCond:
15849switch (this->args[1].kind()) {
15850case Arg::Tmp:
15851switch (this->args[2].kind()) {
15852case Arg::Tmp:
15853if (!args[1].tmp().isFP())
15854OPGEN_RETURN(false);
15855if (!args[2].tmp().isFP())
15856OPGEN_RETURN(false);
15857OPGEN_RETURN(true);
15858break;
15859break;
15860default:
15861break;
15862}
15863break;
15864default:
15865break;
15866}
15867break;
15868default:
15869break;
15870}
15871break;
15872default:
15873break;
15874}
15875break;
15876case Opcode::BranchAdd32:
15877switch (this->args.size()) {
15878case 4:
15879switch (this->args[0].kind()) {
15880case Arg::ResCond:
15881switch (this->args[1].kind()) {
15882case Arg::Tmp:
15883switch (this->args[2].kind()) {
15884case Arg::Tmp:
15885switch (this->args[3].kind()) {
15886case Arg::Tmp:
15887if (!args[1].tmp().isGP())
15888OPGEN_RETURN(false);
15889if (!args[2].tmp().isGP())
15890OPGEN_RETURN(false);
15891if (!args[3].tmp().isGP())
15892OPGEN_RETURN(false);
15893OPGEN_RETURN(true);
15894break;
15895break;
15896default:
15897break;
15898}
15899break;
15900case Arg::Addr:
15901case Arg::Stack:
15902case Arg::CallArg:
15903switch (this->args[3].kind()) {
15904case Arg::Tmp:
15905#if CPU(X86) || CPU(X86_64)
15906if (!args[1].tmp().isGP())
15907OPGEN_RETURN(false);
15908if (!Arg::isValidAddrForm(args[2].offset()))
15909OPGEN_RETURN(false);
15910if (!args[3].tmp().isGP())
15911OPGEN_RETURN(false);
15912OPGEN_RETURN(true);
15913#endif
15914break;
15915break;
15916default:
15917break;
15918}
15919break;
15920default:
15921break;
15922}
15923break;
15924case Arg::Addr:
15925case Arg::Stack:
15926case Arg::CallArg:
15927switch (this->args[2].kind()) {
15928case Arg::Tmp:
15929switch (this->args[3].kind()) {
15930case Arg::Tmp:
15931#if CPU(X86) || CPU(X86_64)
15932if (!Arg::isValidAddrForm(args[1].offset()))
15933OPGEN_RETURN(false);
15934if (!args[2].tmp().isGP())
15935OPGEN_RETURN(false);
15936if (!args[3].tmp().isGP())
15937OPGEN_RETURN(false);
15938OPGEN_RETURN(true);
15939#endif
15940break;
15941break;
15942default:
15943break;
15944}
15945break;
15946default:
15947break;
15948}
15949break;
15950default:
15951break;
15952}
15953break;
15954default:
15955break;
15956}
15957break;
15958case 3:
15959switch (this->args[0].kind()) {
15960case Arg::ResCond:
15961switch (this->args[1].kind()) {
15962case Arg::Tmp:
15963switch (this->args[2].kind()) {
15964case Arg::Tmp:
15965if (!args[1].tmp().isGP())
15966OPGEN_RETURN(false);
15967if (!args[2].tmp().isGP())
15968OPGEN_RETURN(false);
15969OPGEN_RETURN(true);
15970break;
15971break;
15972case Arg::Addr:
15973case Arg::Stack:
15974case Arg::CallArg:
15975#if CPU(X86) || CPU(X86_64)
15976if (!args[1].tmp().isGP())
15977OPGEN_RETURN(false);
15978if (!Arg::isValidAddrForm(args[2].offset()))
15979OPGEN_RETURN(false);
15980OPGEN_RETURN(true);
15981#endif
15982break;
15983break;
15984default:
15985break;
15986}
15987break;
15988case Arg::Imm:
15989switch (this->args[2].kind()) {
15990case Arg::Tmp:
15991if (!Arg::isValidImmForm(args[1].value()))
15992OPGEN_RETURN(false);
15993if (!args[2].tmp().isGP())
15994OPGEN_RETURN(false);
15995OPGEN_RETURN(true);
15996break;
15997break;
15998case Arg::Addr:
15999case Arg::Stack:
16000case Arg::CallArg:
16001#if CPU(X86) || CPU(X86_64)
16002if (!Arg::isValidImmForm(args[1].value()))
16003OPGEN_RETURN(false);
16004if (!Arg::isValidAddrForm(args[2].offset()))
16005OPGEN_RETURN(false);
16006OPGEN_RETURN(true);
16007#endif
16008break;
16009break;
16010default:
16011break;
16012}
16013break;
16014case Arg::Addr:
16015case Arg::Stack:
16016case Arg::CallArg:
16017switch (this->args[2].kind()) {
16018case Arg::Tmp:
16019#if CPU(X86) || CPU(X86_64)
16020if (!Arg::isValidAddrForm(args[1].offset()))
16021OPGEN_RETURN(false);
16022if (!args[2].tmp().isGP())
16023OPGEN_RETURN(false);
16024OPGEN_RETURN(true);
16025#endif
16026break;
16027break;
16028default:
16029break;
16030}
16031break;
16032default:
16033break;
16034}
16035break;
16036default:
16037break;
16038}
16039break;
16040default:
16041break;
16042}
16043break;
16044case Opcode::BranchAdd64:
16045switch (this->args.size()) {
16046case 4:
16047switch (this->args[0].kind()) {
16048case Arg::ResCond:
16049switch (this->args[1].kind()) {
16050case Arg::Tmp:
16051switch (this->args[2].kind()) {
16052case Arg::Tmp:
16053switch (this->args[3].kind()) {
16054case Arg::Tmp:
16055if (!args[1].tmp().isGP())
16056OPGEN_RETURN(false);
16057if (!args[2].tmp().isGP())
16058OPGEN_RETURN(false);
16059if (!args[3].tmp().isGP())
16060OPGEN_RETURN(false);
16061OPGEN_RETURN(true);
16062break;
16063break;
16064default:
16065break;
16066}
16067break;
16068case Arg::Addr:
16069case Arg::Stack:
16070case Arg::CallArg:
16071switch (this->args[3].kind()) {
16072case Arg::Tmp:
16073#if CPU(X86) || CPU(X86_64)
16074if (!args[1].tmp().isGP())
16075OPGEN_RETURN(false);
16076if (!Arg::isValidAddrForm(args[2].offset()))
16077OPGEN_RETURN(false);
16078if (!args[3].tmp().isGP())
16079OPGEN_RETURN(false);
16080OPGEN_RETURN(true);
16081#endif
16082break;
16083break;
16084default:
16085break;
16086}
16087break;
16088default:
16089break;
16090}
16091break;
16092case Arg::Addr:
16093case Arg::Stack:
16094case Arg::CallArg:
16095switch (this->args[2].kind()) {
16096case Arg::Tmp:
16097switch (this->args[3].kind()) {
16098case Arg::Tmp:
16099#if CPU(X86) || CPU(X86_64)
16100if (!Arg::isValidAddrForm(args[1].offset()))
16101OPGEN_RETURN(false);
16102if (!args[2].tmp().isGP())
16103OPGEN_RETURN(false);
16104if (!args[3].tmp().isGP())
16105OPGEN_RETURN(false);
16106OPGEN_RETURN(true);
16107#endif
16108break;
16109break;
16110default:
16111break;
16112}
16113break;
16114default:
16115break;
16116}
16117break;
16118default:
16119break;
16120}
16121break;
16122default:
16123break;
16124}
16125break;
16126case 3:
16127switch (this->args[0].kind()) {
16128case Arg::ResCond:
16129switch (this->args[1].kind()) {
16130case Arg::Imm:
16131switch (this->args[2].kind()) {
16132case Arg::Tmp:
16133#if CPU(X86_64) || CPU(ARM64)
16134if (!Arg::isValidImmForm(args[1].value()))
16135OPGEN_RETURN(false);
16136if (!args[2].tmp().isGP())
16137OPGEN_RETURN(false);
16138OPGEN_RETURN(true);
16139#endif
16140break;
16141break;
16142default:
16143break;
16144}
16145break;
16146case Arg::Tmp:
16147switch (this->args[2].kind()) {
16148case Arg::Tmp:
16149#if CPU(X86_64) || CPU(ARM64)
16150if (!args[1].tmp().isGP())
16151OPGEN_RETURN(false);
16152if (!args[2].tmp().isGP())
16153OPGEN_RETURN(false);
16154OPGEN_RETURN(true);
16155#endif
16156break;
16157break;
16158default:
16159break;
16160}
16161break;
16162case Arg::Addr:
16163case Arg::Stack:
16164case Arg::CallArg:
16165switch (this->args[2].kind()) {
16166case Arg::Tmp:
16167#if CPU(X86_64)
16168if (!Arg::isValidAddrForm(args[1].offset()))
16169OPGEN_RETURN(false);
16170if (!args[2].tmp().isGP())
16171OPGEN_RETURN(false);
16172OPGEN_RETURN(true);
16173#endif
16174break;
16175break;
16176default:
16177break;
16178}
16179break;
16180default:
16181break;
16182}
16183break;
16184default:
16185break;
16186}
16187break;
16188default:
16189break;
16190}
16191break;
16192case Opcode::BranchMul32:
16193switch (this->args.size()) {
16194case 3:
16195switch (this->args[0].kind()) {
16196case Arg::ResCond:
16197switch (this->args[1].kind()) {
16198case Arg::Tmp:
16199switch (this->args[2].kind()) {
16200case Arg::Tmp:
16201#if CPU(X86) || CPU(X86_64)
16202if (!args[1].tmp().isGP())
16203OPGEN_RETURN(false);
16204if (!args[2].tmp().isGP())
16205OPGEN_RETURN(false);
16206OPGEN_RETURN(true);
16207#endif
16208break;
16209break;
16210default:
16211break;
16212}
16213break;
16214case Arg::Addr:
16215case Arg::Stack:
16216case Arg::CallArg:
16217switch (this->args[2].kind()) {
16218case Arg::Tmp:
16219#if CPU(X86) || CPU(X86_64)
16220if (!Arg::isValidAddrForm(args[1].offset()))
16221OPGEN_RETURN(false);
16222if (!args[2].tmp().isGP())
16223OPGEN_RETURN(false);
16224OPGEN_RETURN(true);
16225#endif
16226break;
16227break;
16228default:
16229break;
16230}
16231break;
16232default:
16233break;
16234}
16235break;
16236default:
16237break;
16238}
16239break;
16240case 4:
16241switch (this->args[0].kind()) {
16242case Arg::ResCond:
16243switch (this->args[1].kind()) {
16244case Arg::Tmp:
16245switch (this->args[2].kind()) {
16246case Arg::Imm:
16247switch (this->args[3].kind()) {
16248case Arg::Tmp:
16249#if CPU(X86) || CPU(X86_64)
16250if (!args[1].tmp().isGP())
16251OPGEN_RETURN(false);
16252if (!Arg::isValidImmForm(args[2].value()))
16253OPGEN_RETURN(false);
16254if (!args[3].tmp().isGP())
16255OPGEN_RETURN(false);
16256OPGEN_RETURN(true);
16257#endif
16258break;
16259break;
16260default:
16261break;
16262}
16263break;
16264default:
16265break;
16266}
16267break;
16268default:
16269break;
16270}
16271break;
16272default:
16273break;
16274}
16275break;
16276case 6:
16277switch (this->args[0].kind()) {
16278case Arg::ResCond:
16279switch (this->args[1].kind()) {
16280case Arg::Tmp:
16281switch (this->args[2].kind()) {
16282case Arg::Tmp:
16283switch (this->args[3].kind()) {
16284case Arg::Tmp:
16285switch (this->args[4].kind()) {
16286case Arg::Tmp:
16287switch (this->args[5].kind()) {
16288case Arg::Tmp:
16289#if CPU(ARM64)
16290if (!args[1].tmp().isGP())
16291OPGEN_RETURN(false);
16292if (!args[2].tmp().isGP())
16293OPGEN_RETURN(false);
16294if (!args[3].tmp().isGP())
16295OPGEN_RETURN(false);
16296if (!args[4].tmp().isGP())
16297OPGEN_RETURN(false);
16298if (!args[5].tmp().isGP())
16299OPGEN_RETURN(false);
16300OPGEN_RETURN(true);
16301#endif
16302break;
16303break;
16304default:
16305break;
16306}
16307break;
16308default:
16309break;
16310}
16311break;
16312default:
16313break;
16314}
16315break;
16316default:
16317break;
16318}
16319break;
16320default:
16321break;
16322}
16323break;
16324default:
16325break;
16326}
16327break;
16328default:
16329break;
16330}
16331break;
16332case Opcode::BranchMul64:
16333switch (this->args.size()) {
16334case 3:
16335switch (this->args[0].kind()) {
16336case Arg::ResCond:
16337switch (this->args[1].kind()) {
16338case Arg::Tmp:
16339switch (this->args[2].kind()) {
16340case Arg::Tmp:
16341#if CPU(X86_64)
16342if (!args[1].tmp().isGP())
16343OPGEN_RETURN(false);
16344if (!args[2].tmp().isGP())
16345OPGEN_RETURN(false);
16346OPGEN_RETURN(true);
16347#endif
16348break;
16349break;
16350default:
16351break;
16352}
16353break;
16354default:
16355break;
16356}
16357break;
16358default:
16359break;
16360}
16361break;
16362case 6:
16363switch (this->args[0].kind()) {
16364case Arg::ResCond:
16365switch (this->args[1].kind()) {
16366case Arg::Tmp:
16367switch (this->args[2].kind()) {
16368case Arg::Tmp:
16369switch (this->args[3].kind()) {
16370case Arg::Tmp:
16371switch (this->args[4].kind()) {
16372case Arg::Tmp:
16373switch (this->args[5].kind()) {
16374case Arg::Tmp:
16375#if CPU(ARM64)
16376if (!args[1].tmp().isGP())
16377OPGEN_RETURN(false);
16378if (!args[2].tmp().isGP())
16379OPGEN_RETURN(false);
16380if (!args[3].tmp().isGP())
16381OPGEN_RETURN(false);
16382if (!args[4].tmp().isGP())
16383OPGEN_RETURN(false);
16384if (!args[5].tmp().isGP())
16385OPGEN_RETURN(false);
16386OPGEN_RETURN(true);
16387#endif
16388break;
16389break;
16390default:
16391break;
16392}
16393break;
16394default:
16395break;
16396}
16397break;
16398default:
16399break;
16400}
16401break;
16402default:
16403break;
16404}
16405break;
16406default:
16407break;
16408}
16409break;
16410default:
16411break;
16412}
16413break;
16414default:
16415break;
16416}
16417break;
16418case Opcode::BranchSub32:
16419switch (this->args.size()) {
16420case 3:
16421switch (this->args[0].kind()) {
16422case Arg::ResCond:
16423switch (this->args[1].kind()) {
16424case Arg::Tmp:
16425switch (this->args[2].kind()) {
16426case Arg::Tmp:
16427if (!args[1].tmp().isGP())
16428OPGEN_RETURN(false);
16429if (!args[2].tmp().isGP())
16430OPGEN_RETURN(false);
16431OPGEN_RETURN(true);
16432break;
16433break;
16434case Arg::Addr:
16435case Arg::Stack:
16436case Arg::CallArg:
16437#if CPU(X86) || CPU(X86_64)
16438if (!args[1].tmp().isGP())
16439OPGEN_RETURN(false);
16440if (!Arg::isValidAddrForm(args[2].offset()))
16441OPGEN_RETURN(false);
16442OPGEN_RETURN(true);
16443#endif
16444break;
16445break;
16446default:
16447break;
16448}
16449break;
16450case Arg::Imm:
16451switch (this->args[2].kind()) {
16452case Arg::Tmp:
16453if (!Arg::isValidImmForm(args[1].value()))
16454OPGEN_RETURN(false);
16455if (!args[2].tmp().isGP())
16456OPGEN_RETURN(false);
16457OPGEN_RETURN(true);
16458break;
16459break;
16460case Arg::Addr:
16461case Arg::Stack:
16462case Arg::CallArg:
16463#if CPU(X86) || CPU(X86_64)
16464if (!Arg::isValidImmForm(args[1].value()))
16465OPGEN_RETURN(false);
16466if (!Arg::isValidAddrForm(args[2].offset()))
16467OPGEN_RETURN(false);
16468OPGEN_RETURN(true);
16469#endif
16470break;
16471break;
16472default:
16473break;
16474}
16475break;
16476case Arg::Addr:
16477case Arg::Stack:
16478case Arg::CallArg:
16479switch (this->args[2].kind()) {
16480case Arg::Tmp:
16481#if CPU(X86) || CPU(X86_64)
16482if (!Arg::isValidAddrForm(args[1].offset()))
16483OPGEN_RETURN(false);
16484if (!args[2].tmp().isGP())
16485OPGEN_RETURN(false);
16486OPGEN_RETURN(true);
16487#endif
16488break;
16489break;
16490default:
16491break;
16492}
16493break;
16494default:
16495break;
16496}
16497break;
16498default:
16499break;
16500}
16501break;
16502default:
16503break;
16504}
16505break;
16506case Opcode::BranchSub64:
16507switch (this->args.size()) {
16508case 3:
16509switch (this->args[0].kind()) {
16510case Arg::ResCond:
16511switch (this->args[1].kind()) {
16512case Arg::Imm:
16513switch (this->args[2].kind()) {
16514case Arg::Tmp:
16515#if CPU(X86_64) || CPU(ARM64)
16516if (!Arg::isValidImmForm(args[1].value()))
16517OPGEN_RETURN(false);
16518if (!args[2].tmp().isGP())
16519OPGEN_RETURN(false);
16520OPGEN_RETURN(true);
16521#endif
16522break;
16523break;
16524default:
16525break;
16526}
16527break;
16528case Arg::Tmp:
16529switch (this->args[2].kind()) {
16530case Arg::Tmp:
16531#if CPU(X86_64) || CPU(ARM64)
16532if (!args[1].tmp().isGP())
16533OPGEN_RETURN(false);
16534if (!args[2].tmp().isGP())
16535OPGEN_RETURN(false);
16536OPGEN_RETURN(true);
16537#endif
16538break;
16539break;
16540default:
16541break;
16542}
16543break;
16544default:
16545break;
16546}
16547break;
16548default:
16549break;
16550}
16551break;
16552default:
16553break;
16554}
16555break;
16556case Opcode::BranchNeg32:
16557switch (this->args.size()) {
16558case 2:
16559switch (this->args[0].kind()) {
16560case Arg::ResCond:
16561switch (this->args[1].kind()) {
16562case Arg::Tmp:
16563if (!args[1].tmp().isGP())
16564OPGEN_RETURN(false);
16565OPGEN_RETURN(true);
16566break;
16567break;
16568default:
16569break;
16570}
16571break;
16572default:
16573break;
16574}
16575break;
16576default:
16577break;
16578}
16579break;
16580case Opcode::BranchNeg64:
16581switch (this->args.size()) {
16582case 2:
16583switch (this->args[0].kind()) {
16584case Arg::ResCond:
16585switch (this->args[1].kind()) {
16586case Arg::Tmp:
16587#if CPU(X86_64) || CPU(ARM64)
16588if (!args[1].tmp().isGP())
16589OPGEN_RETURN(false);
16590OPGEN_RETURN(true);
16591#endif
16592break;
16593break;
16594default:
16595break;
16596}
16597break;
16598default:
16599break;
16600}
16601break;
16602default:
16603break;
16604}
16605break;
16606case Opcode::MoveConditionally32:
16607switch (this->args.size()) {
16608case 5:
16609switch (this->args[0].kind()) {
16610case Arg::RelCond:
16611switch (this->args[1].kind()) {
16612case Arg::Tmp:
16613switch (this->args[2].kind()) {
16614case Arg::Tmp:
16615switch (this->args[3].kind()) {
16616case Arg::Tmp:
16617switch (this->args[4].kind()) {
16618case Arg::Tmp:
16619if (!args[1].tmp().isGP())
16620OPGEN_RETURN(false);
16621if (!args[2].tmp().isGP())
16622OPGEN_RETURN(false);
16623if (!args[3].tmp().isGP())
16624OPGEN_RETURN(false);
16625if (!args[4].tmp().isGP())
16626OPGEN_RETURN(false);
16627OPGEN_RETURN(true);
16628break;
16629break;
16630default:
16631break;
16632}
16633break;
16634default:
16635break;
16636}
16637break;
16638default:
16639break;
16640}
16641break;
16642default:
16643break;
16644}
16645break;
16646default:
16647break;
16648}
16649break;
16650case 6:
16651switch (this->args[0].kind()) {
16652case Arg::RelCond:
16653switch (this->args[1].kind()) {
16654case Arg::Tmp:
16655switch (this->args[2].kind()) {
16656case Arg::Tmp:
16657switch (this->args[3].kind()) {
16658case Arg::Tmp:
16659switch (this->args[4].kind()) {
16660case Arg::Tmp:
16661switch (this->args[5].kind()) {
16662case Arg::Tmp:
16663if (!args[1].tmp().isGP())
16664OPGEN_RETURN(false);
16665if (!args[2].tmp().isGP())
16666OPGEN_RETURN(false);
16667if (!args[3].tmp().isGP())
16668OPGEN_RETURN(false);
16669if (!args[4].tmp().isGP())
16670OPGEN_RETURN(false);
16671if (!args[5].tmp().isGP())
16672OPGEN_RETURN(false);
16673OPGEN_RETURN(true);
16674break;
16675break;
16676default:
16677break;
16678}
16679break;
16680default:
16681break;
16682}
16683break;
16684default:
16685break;
16686}
16687break;
16688case Arg::Imm:
16689switch (this->args[3].kind()) {
16690case Arg::Tmp:
16691switch (this->args[4].kind()) {
16692case Arg::Tmp:
16693switch (this->args[5].kind()) {
16694case Arg::Tmp:
16695if (!args[1].tmp().isGP())
16696OPGEN_RETURN(false);
16697if (!Arg::isValidImmForm(args[2].value()))
16698OPGEN_RETURN(false);
16699if (!args[3].tmp().isGP())
16700OPGEN_RETURN(false);
16701if (!args[4].tmp().isGP())
16702OPGEN_RETURN(false);
16703if (!args[5].tmp().isGP())
16704OPGEN_RETURN(false);
16705OPGEN_RETURN(true);
16706break;
16707break;
16708default:
16709break;
16710}
16711break;
16712default:
16713break;
16714}
16715break;
16716default:
16717break;
16718}
16719break;
16720default:
16721break;
16722}
16723break;
16724default:
16725break;
16726}
16727break;
16728default:
16729break;
16730}
16731break;
16732default:
16733break;
16734}
16735break;
16736case Opcode::MoveConditionally64:
16737switch (this->args.size()) {
16738case 5:
16739switch (this->args[0].kind()) {
16740case Arg::RelCond:
16741switch (this->args[1].kind()) {
16742case Arg::Tmp:
16743switch (this->args[2].kind()) {
16744case Arg::Tmp:
16745switch (this->args[3].kind()) {
16746case Arg::Tmp:
16747switch (this->args[4].kind()) {
16748case Arg::Tmp:
16749#if CPU(X86_64) || CPU(ARM64)
16750if (!args[1].tmp().isGP())
16751OPGEN_RETURN(false);
16752if (!args[2].tmp().isGP())
16753OPGEN_RETURN(false);
16754if (!args[3].tmp().isGP())
16755OPGEN_RETURN(false);
16756if (!args[4].tmp().isGP())
16757OPGEN_RETURN(false);
16758OPGEN_RETURN(true);
16759#endif
16760break;
16761break;
16762default:
16763break;
16764}
16765break;
16766default:
16767break;
16768}
16769break;
16770default:
16771break;
16772}
16773break;
16774default:
16775break;
16776}
16777break;
16778default:
16779break;
16780}
16781break;
16782case 6:
16783switch (this->args[0].kind()) {
16784case Arg::RelCond:
16785switch (this->args[1].kind()) {
16786case Arg::Tmp:
16787switch (this->args[2].kind()) {
16788case Arg::Tmp:
16789switch (this->args[3].kind()) {
16790case Arg::Tmp:
16791switch (this->args[4].kind()) {
16792case Arg::Tmp:
16793switch (this->args[5].kind()) {
16794case Arg::Tmp:
16795#if CPU(X86_64) || CPU(ARM64)
16796if (!args[1].tmp().isGP())
16797OPGEN_RETURN(false);
16798if (!args[2].tmp().isGP())
16799OPGEN_RETURN(false);
16800if (!args[3].tmp().isGP())
16801OPGEN_RETURN(false);
16802if (!args[4].tmp().isGP())
16803OPGEN_RETURN(false);
16804if (!args[5].tmp().isGP())
16805OPGEN_RETURN(false);
16806OPGEN_RETURN(true);
16807#endif
16808break;
16809break;
16810default:
16811break;
16812}
16813break;
16814default:
16815break;
16816}
16817break;
16818default:
16819break;
16820}
16821break;
16822case Arg::Imm:
16823switch (this->args[3].kind()) {
16824case Arg::Tmp:
16825switch (this->args[4].kind()) {
16826case Arg::Tmp:
16827switch (this->args[5].kind()) {
16828case Arg::Tmp:
16829#if CPU(X86_64) || CPU(ARM64)
16830if (!args[1].tmp().isGP())
16831OPGEN_RETURN(false);
16832if (!Arg::isValidImmForm(args[2].value()))
16833OPGEN_RETURN(false);
16834if (!args[3].tmp().isGP())
16835OPGEN_RETURN(false);
16836if (!args[4].tmp().isGP())
16837OPGEN_RETURN(false);
16838if (!args[5].tmp().isGP())
16839OPGEN_RETURN(false);
16840OPGEN_RETURN(true);
16841#endif
16842break;
16843break;
16844default:
16845break;
16846}
16847break;
16848default:
16849break;
16850}
16851break;
16852default:
16853break;
16854}
16855break;
16856default:
16857break;
16858}
16859break;
16860default:
16861break;
16862}
16863break;
16864default:
16865break;
16866}
16867break;
16868default:
16869break;
16870}
16871break;
16872case Opcode::MoveConditionallyTest32:
16873switch (this->args.size()) {
16874case 5:
16875switch (this->args[0].kind()) {
16876case Arg::ResCond:
16877switch (this->args[1].kind()) {
16878case Arg::Tmp:
16879switch (this->args[2].kind()) {
16880case Arg::Tmp:
16881switch (this->args[3].kind()) {
16882case Arg::Tmp:
16883switch (this->args[4].kind()) {
16884case Arg::Tmp:
16885if (!args[1].tmp().isGP())
16886OPGEN_RETURN(false);
16887if (!args[2].tmp().isGP())
16888OPGEN_RETURN(false);
16889if (!args[3].tmp().isGP())
16890OPGEN_RETURN(false);
16891if (!args[4].tmp().isGP())
16892OPGEN_RETURN(false);
16893OPGEN_RETURN(true);
16894break;
16895break;
16896default:
16897break;
16898}
16899break;
16900default:
16901break;
16902}
16903break;
16904case Arg::Imm:
16905switch (this->args[3].kind()) {
16906case Arg::Tmp:
16907switch (this->args[4].kind()) {
16908case Arg::Tmp:
16909#if CPU(X86) || CPU(X86_64)
16910if (!args[1].tmp().isGP())
16911OPGEN_RETURN(false);
16912if (!Arg::isValidImmForm(args[2].value()))
16913OPGEN_RETURN(false);
16914if (!args[3].tmp().isGP())
16915OPGEN_RETURN(false);
16916if (!args[4].tmp().isGP())
16917OPGEN_RETURN(false);
16918OPGEN_RETURN(true);
16919#endif
16920break;
16921break;
16922default:
16923break;
16924}
16925break;
16926default:
16927break;
16928}
16929break;
16930default:
16931break;
16932}
16933break;
16934default:
16935break;
16936}
16937break;
16938default:
16939break;
16940}
16941break;
16942case 6:
16943switch (this->args[0].kind()) {
16944case Arg::ResCond:
16945switch (this->args[1].kind()) {
16946case Arg::Tmp:
16947switch (this->args[2].kind()) {
16948case Arg::Tmp:
16949switch (this->args[3].kind()) {
16950case Arg::Tmp:
16951switch (this->args[4].kind()) {
16952case Arg::Tmp:
16953switch (this->args[5].kind()) {
16954case Arg::Tmp:
16955if (!args[1].tmp().isGP())
16956OPGEN_RETURN(false);
16957if (!args[2].tmp().isGP())
16958OPGEN_RETURN(false);
16959if (!args[3].tmp().isGP())
16960OPGEN_RETURN(false);
16961if (!args[4].tmp().isGP())
16962OPGEN_RETURN(false);
16963if (!args[5].tmp().isGP())
16964OPGEN_RETURN(false);
16965OPGEN_RETURN(true);
16966break;
16967break;
16968default:
16969break;
16970}
16971break;
16972default:
16973break;
16974}
16975break;
16976default:
16977break;
16978}
16979break;
16980case Arg::BitImm:
16981switch (this->args[3].kind()) {
16982case Arg::Tmp:
16983switch (this->args[4].kind()) {
16984case Arg::Tmp:
16985switch (this->args[5].kind()) {
16986case Arg::Tmp:
16987if (!args[1].tmp().isGP())
16988OPGEN_RETURN(false);
16989if (!Arg::isValidBitImmForm(args[2].value()))
16990OPGEN_RETURN(false);
16991if (!args[3].tmp().isGP())
16992OPGEN_RETURN(false);
16993if (!args[4].tmp().isGP())
16994OPGEN_RETURN(false);
16995if (!args[5].tmp().isGP())
16996OPGEN_RETURN(false);
16997OPGEN_RETURN(true);
16998break;
16999break;
17000default:
17001break;
17002}
17003break;
17004default:
17005break;
17006}
17007break;
17008default:
17009break;
17010}
17011break;
17012default:
17013break;
17014}
17015break;
17016default:
17017break;
17018}
17019break;
17020default:
17021break;
17022}
17023break;
17024default:
17025break;
17026}
17027break;
17028case Opcode::MoveConditionallyTest64:
17029switch (this->args.size()) {
17030case 5:
17031switch (this->args[0].kind()) {
17032case Arg::ResCond:
17033switch (this->args[1].kind()) {
17034case Arg::Tmp:
17035switch (this->args[2].kind()) {
17036case Arg::Tmp:
17037switch (this->args[3].kind()) {
17038case Arg::Tmp:
17039switch (this->args[4].kind()) {
17040case Arg::Tmp:
17041#if CPU(X86_64) || CPU(ARM64)
17042if (!args[1].tmp().isGP())
17043OPGEN_RETURN(false);
17044if (!args[2].tmp().isGP())
17045OPGEN_RETURN(false);
17046if (!args[3].tmp().isGP())
17047OPGEN_RETURN(false);
17048if (!args[4].tmp().isGP())
17049OPGEN_RETURN(false);
17050OPGEN_RETURN(true);
17051#endif
17052break;
17053break;
17054default:
17055break;
17056}
17057break;
17058default:
17059break;
17060}
17061break;
17062case Arg::Imm:
17063switch (this->args[3].kind()) {
17064case Arg::Tmp:
17065switch (this->args[4].kind()) {
17066case Arg::Tmp:
17067#if CPU(X86_64)
17068if (!args[1].tmp().isGP())
17069OPGEN_RETURN(false);
17070if (!Arg::isValidImmForm(args[2].value()))
17071OPGEN_RETURN(false);
17072if (!args[3].tmp().isGP())
17073OPGEN_RETURN(false);
17074if (!args[4].tmp().isGP())
17075OPGEN_RETURN(false);
17076OPGEN_RETURN(true);
17077#endif
17078break;
17079break;
17080default:
17081break;
17082}
17083break;
17084default:
17085break;
17086}
17087break;
17088default:
17089break;
17090}
17091break;
17092default:
17093break;
17094}
17095break;
17096default:
17097break;
17098}
17099break;
17100case 6:
17101switch (this->args[0].kind()) {
17102case Arg::ResCond:
17103switch (this->args[1].kind()) {
17104case Arg::Tmp:
17105switch (this->args[2].kind()) {
17106case Arg::Tmp:
17107switch (this->args[3].kind()) {
17108case Arg::Tmp:
17109switch (this->args[4].kind()) {
17110case Arg::Tmp:
17111switch (this->args[5].kind()) {
17112case Arg::Tmp:
17113#if CPU(X86_64) || CPU(ARM64)
17114if (!args[1].tmp().isGP())
17115OPGEN_RETURN(false);
17116if (!args[2].tmp().isGP())
17117OPGEN_RETURN(false);
17118if (!args[3].tmp().isGP())
17119OPGEN_RETURN(false);
17120if (!args[4].tmp().isGP())
17121OPGEN_RETURN(false);
17122if (!args[5].tmp().isGP())
17123OPGEN_RETURN(false);
17124OPGEN_RETURN(true);
17125#endif
17126break;
17127break;
17128default:
17129break;
17130}
17131break;
17132default:
17133break;
17134}
17135break;
17136default:
17137break;
17138}
17139break;
17140case Arg::Imm:
17141switch (this->args[3].kind()) {
17142case Arg::Tmp:
17143switch (this->args[4].kind()) {
17144case Arg::Tmp:
17145switch (this->args[5].kind()) {
17146case Arg::Tmp:
17147#if CPU(X86_64)
17148if (!args[1].tmp().isGP())
17149OPGEN_RETURN(false);
17150if (!Arg::isValidImmForm(args[2].value()))
17151OPGEN_RETURN(false);
17152if (!args[3].tmp().isGP())
17153OPGEN_RETURN(false);
17154if (!args[4].tmp().isGP())
17155OPGEN_RETURN(false);
17156if (!args[5].tmp().isGP())
17157OPGEN_RETURN(false);
17158OPGEN_RETURN(true);
17159#endif
17160break;
17161break;
17162default:
17163break;
17164}
17165break;
17166default:
17167break;
17168}
17169break;
17170default:
17171break;
17172}
17173break;
17174default:
17175break;
17176}
17177break;
17178default:
17179break;
17180}
17181break;
17182default:
17183break;
17184}
17185break;
17186default:
17187break;
17188}
17189break;
17190case Opcode::MoveConditionallyDouble:
17191switch (this->args.size()) {
17192case 6:
17193switch (this->args[0].kind()) {
17194case Arg::DoubleCond:
17195switch (this->args[1].kind()) {
17196case Arg::Tmp:
17197switch (this->args[2].kind()) {
17198case Arg::Tmp:
17199switch (this->args[3].kind()) {
17200case Arg::Tmp:
17201switch (this->args[4].kind()) {
17202case Arg::Tmp:
17203switch (this->args[5].kind()) {
17204case Arg::Tmp:
17205if (!args[1].tmp().isFP())
17206OPGEN_RETURN(false);
17207if (!args[2].tmp().isFP())
17208OPGEN_RETURN(false);
17209if (!args[3].tmp().isGP())
17210OPGEN_RETURN(false);
17211if (!args[4].tmp().isGP())
17212OPGEN_RETURN(false);
17213if (!args[5].tmp().isGP())
17214OPGEN_RETURN(false);
17215OPGEN_RETURN(true);
17216break;
17217break;
17218default:
17219break;
17220}
17221break;
17222default:
17223break;
17224}
17225break;
17226default:
17227break;
17228}
17229break;
17230default:
17231break;
17232}
17233break;
17234default:
17235break;
17236}
17237break;
17238default:
17239break;
17240}
17241break;
17242case 5:
17243switch (this->args[0].kind()) {
17244case Arg::DoubleCond:
17245switch (this->args[1].kind()) {
17246case Arg::Tmp:
17247switch (this->args[2].kind()) {
17248case Arg::Tmp:
17249switch (this->args[3].kind()) {
17250case Arg::Tmp:
17251switch (this->args[4].kind()) {
17252case Arg::Tmp:
17253if (!args[1].tmp().isFP())
17254OPGEN_RETURN(false);
17255if (!args[2].tmp().isFP())
17256OPGEN_RETURN(false);
17257if (!args[3].tmp().isGP())
17258OPGEN_RETURN(false);
17259if (!args[4].tmp().isGP())
17260OPGEN_RETURN(false);
17261OPGEN_RETURN(true);
17262break;
17263break;
17264default:
17265break;
17266}
17267break;
17268default:
17269break;
17270}
17271break;
17272default:
17273break;
17274}
17275break;
17276default:
17277break;
17278}
17279break;
17280default:
17281break;
17282}
17283break;
17284default:
17285break;
17286}
17287break;
17288case Opcode::MoveConditionallyFloat:
17289switch (this->args.size()) {
17290case 6:
17291switch (this->args[0].kind()) {
17292case Arg::DoubleCond:
17293switch (this->args[1].kind()) {
17294case Arg::Tmp:
17295switch (this->args[2].kind()) {
17296case Arg::Tmp:
17297switch (this->args[3].kind()) {
17298case Arg::Tmp:
17299switch (this->args[4].kind()) {
17300case Arg::Tmp:
17301switch (this->args[5].kind()) {
17302case Arg::Tmp:
17303if (!args[1].tmp().isFP())
17304OPGEN_RETURN(false);
17305if (!args[2].tmp().isFP())
17306OPGEN_RETURN(false);
17307if (!args[3].tmp().isGP())
17308OPGEN_RETURN(false);
17309if (!args[4].tmp().isGP())
17310OPGEN_RETURN(false);
17311if (!args[5].tmp().isGP())
17312OPGEN_RETURN(false);
17313OPGEN_RETURN(true);
17314break;
17315break;
17316default:
17317break;
17318}
17319break;
17320default:
17321break;
17322}
17323break;
17324default:
17325break;
17326}
17327break;
17328default:
17329break;
17330}
17331break;
17332default:
17333break;
17334}
17335break;
17336default:
17337break;
17338}
17339break;
17340case 5:
17341switch (this->args[0].kind()) {
17342case Arg::DoubleCond:
17343switch (this->args[1].kind()) {
17344case Arg::Tmp:
17345switch (this->args[2].kind()) {
17346case Arg::Tmp:
17347switch (this->args[3].kind()) {
17348case Arg::Tmp:
17349switch (this->args[4].kind()) {
17350case Arg::Tmp:
17351if (!args[1].tmp().isFP())
17352OPGEN_RETURN(false);
17353if (!args[2].tmp().isFP())
17354OPGEN_RETURN(false);
17355if (!args[3].tmp().isGP())
17356OPGEN_RETURN(false);
17357if (!args[4].tmp().isGP())
17358OPGEN_RETURN(false);
17359OPGEN_RETURN(true);
17360break;
17361break;
17362default:
17363break;
17364}
17365break;
17366default:
17367break;
17368}
17369break;
17370default:
17371break;
17372}
17373break;
17374default:
17375break;
17376}
17377break;
17378default:
17379break;
17380}
17381break;
17382default:
17383break;
17384}
17385break;
17386case Opcode::MoveDoubleConditionally32:
17387switch (this->args.size()) {
17388case 6:
17389switch (this->args[0].kind()) {
17390case Arg::RelCond:
17391switch (this->args[1].kind()) {
17392case Arg::Tmp:
17393switch (this->args[2].kind()) {
17394case Arg::Tmp:
17395switch (this->args[3].kind()) {
17396case Arg::Tmp:
17397switch (this->args[4].kind()) {
17398case Arg::Tmp:
17399switch (this->args[5].kind()) {
17400case Arg::Tmp:
17401if (!args[1].tmp().isGP())
17402OPGEN_RETURN(false);
17403if (!args[2].tmp().isGP())
17404OPGEN_RETURN(false);
17405if (!args[3].tmp().isFP())
17406OPGEN_RETURN(false);
17407if (!args[4].tmp().isFP())
17408OPGEN_RETURN(false);
17409if (!args[5].tmp().isFP())
17410OPGEN_RETURN(false);
17411OPGEN_RETURN(true);
17412break;
17413break;
17414default:
17415break;
17416}
17417break;
17418default:
17419break;
17420}
17421break;
17422default:
17423break;
17424}
17425break;
17426case Arg::Imm:
17427switch (this->args[3].kind()) {
17428case Arg::Tmp:
17429switch (this->args[4].kind()) {
17430case Arg::Tmp:
17431switch (this->args[5].kind()) {
17432case Arg::Tmp:
17433if (!args[1].tmp().isGP())
17434OPGEN_RETURN(false);
17435if (!Arg::isValidImmForm(args[2].value()))
17436OPGEN_RETURN(false);
17437if (!args[3].tmp().isFP())
17438OPGEN_RETURN(false);
17439if (!args[4].tmp().isFP())
17440OPGEN_RETURN(false);
17441if (!args[5].tmp().isFP())
17442OPGEN_RETURN(false);
17443OPGEN_RETURN(true);
17444break;
17445break;
17446default:
17447break;
17448}
17449break;
17450default:
17451break;
17452}
17453break;
17454default:
17455break;
17456}
17457break;
17458case Arg::Addr:
17459case Arg::Stack:
17460case Arg::CallArg:
17461switch (this->args[3].kind()) {
17462case Arg::Tmp:
17463switch (this->args[4].kind()) {
17464case Arg::Tmp:
17465switch (this->args[5].kind()) {
17466case Arg::Tmp:
17467#if CPU(X86) || CPU(X86_64)
17468if (!args[1].tmp().isGP())
17469OPGEN_RETURN(false);
17470if (!Arg::isValidAddrForm(args[2].offset()))
17471OPGEN_RETURN(false);
17472if (!args[3].tmp().isFP())
17473OPGEN_RETURN(false);
17474if (!args[4].tmp().isFP())
17475OPGEN_RETURN(false);
17476if (!args[5].tmp().isFP())
17477OPGEN_RETURN(false);
17478OPGEN_RETURN(true);
17479#endif
17480break;
17481break;
17482default:
17483break;
17484}
17485break;
17486default:
17487break;
17488}
17489break;
17490default:
17491break;
17492}
17493break;
17494default:
17495break;
17496}
17497break;
17498case Arg::Addr:
17499case Arg::Stack:
17500case Arg::CallArg:
17501switch (this->args[2].kind()) {
17502case Arg::Imm:
17503switch (this->args[3].kind()) {
17504case Arg::Tmp:
17505switch (this->args[4].kind()) {
17506case Arg::Tmp:
17507switch (this->args[5].kind()) {
17508case Arg::Tmp:
17509#if CPU(X86) || CPU(X86_64)
17510if (!Arg::isValidAddrForm(args[1].offset()))
17511OPGEN_RETURN(false);
17512if (!Arg::isValidImmForm(args[2].value()))
17513OPGEN_RETURN(false);
17514if (!args[3].tmp().isFP())
17515OPGEN_RETURN(false);
17516if (!args[4].tmp().isFP())
17517OPGEN_RETURN(false);
17518if (!args[5].tmp().isFP())
17519OPGEN_RETURN(false);
17520OPGEN_RETURN(true);
17521#endif
17522break;
17523break;
17524default:
17525break;
17526}
17527break;
17528default:
17529break;
17530}
17531break;
17532default:
17533break;
17534}
17535break;
17536case Arg::Tmp:
17537switch (this->args[3].kind()) {
17538case Arg::Tmp:
17539switch (this->args[4].kind()) {
17540case Arg::Tmp:
17541switch (this->args[5].kind()) {
17542case Arg::Tmp:
17543#if CPU(X86) || CPU(X86_64)
17544if (!Arg::isValidAddrForm(args[1].offset()))
17545OPGEN_RETURN(false);
17546if (!args[2].tmp().isGP())
17547OPGEN_RETURN(false);
17548if (!args[3].tmp().isFP())
17549OPGEN_RETURN(false);
17550if (!args[4].tmp().isFP())
17551OPGEN_RETURN(false);
17552if (!args[5].tmp().isFP())
17553OPGEN_RETURN(false);
17554OPGEN_RETURN(true);
17555#endif
17556break;
17557break;
17558default:
17559break;
17560}
17561break;
17562default:
17563break;
17564}
17565break;
17566default:
17567break;
17568}
17569break;
17570default:
17571break;
17572}
17573break;
17574case Arg::Index:
17575switch (this->args[2].kind()) {
17576case Arg::Imm:
17577switch (this->args[3].kind()) {
17578case Arg::Tmp:
17579switch (this->args[4].kind()) {
17580case Arg::Tmp:
17581switch (this->args[5].kind()) {
17582case Arg::Tmp:
17583#if CPU(X86) || CPU(X86_64)
17584if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
17585OPGEN_RETURN(false);
17586if (!Arg::isValidImmForm(args[2].value()))
17587OPGEN_RETURN(false);
17588if (!args[3].tmp().isFP())
17589OPGEN_RETURN(false);
17590if (!args[4].tmp().isFP())
17591OPGEN_RETURN(false);
17592if (!args[5].tmp().isFP())
17593OPGEN_RETURN(false);
17594OPGEN_RETURN(true);
17595#endif
17596break;
17597break;
17598default:
17599break;
17600}
17601break;
17602default:
17603break;
17604}
17605break;
17606default:
17607break;
17608}
17609break;
17610default:
17611break;
17612}
17613break;
17614default:
17615break;
17616}
17617break;
17618default:
17619break;
17620}
17621break;
17622default:
17623break;
17624}
17625break;
17626case Opcode::MoveDoubleConditionally64:
17627switch (this->args.size()) {
17628case 6:
17629switch (this->args[0].kind()) {
17630case Arg::RelCond:
17631switch (this->args[1].kind()) {
17632case Arg::Tmp:
17633switch (this->args[2].kind()) {
17634case Arg::Tmp:
17635switch (this->args[3].kind()) {
17636case Arg::Tmp:
17637switch (this->args[4].kind()) {
17638case Arg::Tmp:
17639switch (this->args[5].kind()) {
17640case Arg::Tmp:
17641#if CPU(X86_64) || CPU(ARM64)
17642if (!args[1].tmp().isGP())
17643OPGEN_RETURN(false);
17644if (!args[2].tmp().isGP())
17645OPGEN_RETURN(false);
17646if (!args[3].tmp().isFP())
17647OPGEN_RETURN(false);
17648if (!args[4].tmp().isFP())
17649OPGEN_RETURN(false);
17650if (!args[5].tmp().isFP())
17651OPGEN_RETURN(false);
17652OPGEN_RETURN(true);
17653#endif
17654break;
17655break;
17656default:
17657break;
17658}
17659break;
17660default:
17661break;
17662}
17663break;
17664default:
17665break;
17666}
17667break;
17668case Arg::Imm:
17669switch (this->args[3].kind()) {
17670case Arg::Tmp:
17671switch (this->args[4].kind()) {
17672case Arg::Tmp:
17673switch (this->args[5].kind()) {
17674case Arg::Tmp:
17675#if CPU(X86_64) || CPU(ARM64)
17676if (!args[1].tmp().isGP())
17677OPGEN_RETURN(false);
17678if (!Arg::isValidImmForm(args[2].value()))
17679OPGEN_RETURN(false);
17680if (!args[3].tmp().isFP())
17681OPGEN_RETURN(false);
17682if (!args[4].tmp().isFP())
17683OPGEN_RETURN(false);
17684if (!args[5].tmp().isFP())
17685OPGEN_RETURN(false);
17686OPGEN_RETURN(true);
17687#endif
17688break;
17689break;
17690default:
17691break;
17692}
17693break;
17694default:
17695break;
17696}
17697break;
17698default:
17699break;
17700}
17701break;
17702case Arg::Addr:
17703case Arg::Stack:
17704case Arg::CallArg:
17705switch (this->args[3].kind()) {
17706case Arg::Tmp:
17707switch (this->args[4].kind()) {
17708case Arg::Tmp:
17709switch (this->args[5].kind()) {
17710case Arg::Tmp:
17711#if CPU(X86_64)
17712if (!args[1].tmp().isGP())
17713OPGEN_RETURN(false);
17714if (!Arg::isValidAddrForm(args[2].offset()))
17715OPGEN_RETURN(false);
17716if (!args[3].tmp().isFP())
17717OPGEN_RETURN(false);
17718if (!args[4].tmp().isFP())
17719OPGEN_RETURN(false);
17720if (!args[5].tmp().isFP())
17721OPGEN_RETURN(false);
17722OPGEN_RETURN(true);
17723#endif
17724break;
17725break;
17726default:
17727break;
17728}
17729break;
17730default:
17731break;
17732}
17733break;
17734default:
17735break;
17736}
17737break;
17738default:
17739break;
17740}
17741break;
17742case Arg::Addr:
17743case Arg::Stack:
17744case Arg::CallArg:
17745switch (this->args[2].kind()) {
17746case Arg::Tmp:
17747switch (this->args[3].kind()) {
17748case Arg::Tmp:
17749switch (this->args[4].kind()) {
17750case Arg::Tmp:
17751switch (this->args[5].kind()) {
17752case Arg::Tmp:
17753#if CPU(X86_64)
17754if (!Arg::isValidAddrForm(args[1].offset()))
17755OPGEN_RETURN(false);
17756if (!args[2].tmp().isGP())
17757OPGEN_RETURN(false);
17758if (!args[3].tmp().isFP())
17759OPGEN_RETURN(false);
17760if (!args[4].tmp().isFP())
17761OPGEN_RETURN(false);
17762if (!args[5].tmp().isFP())
17763OPGEN_RETURN(false);
17764OPGEN_RETURN(true);
17765#endif
17766break;
17767break;
17768default:
17769break;
17770}
17771break;
17772default:
17773break;
17774}
17775break;
17776default:
17777break;
17778}
17779break;
17780case Arg::Imm:
17781switch (this->args[3].kind()) {
17782case Arg::Tmp:
17783switch (this->args[4].kind()) {
17784case Arg::Tmp:
17785switch (this->args[5].kind()) {
17786case Arg::Tmp:
17787#if CPU(X86_64)
17788if (!Arg::isValidAddrForm(args[1].offset()))
17789OPGEN_RETURN(false);
17790if (!Arg::isValidImmForm(args[2].value()))
17791OPGEN_RETURN(false);
17792if (!args[3].tmp().isFP())
17793OPGEN_RETURN(false);
17794if (!args[4].tmp().isFP())
17795OPGEN_RETURN(false);
17796if (!args[5].tmp().isFP())
17797OPGEN_RETURN(false);
17798OPGEN_RETURN(true);
17799#endif
17800break;
17801break;
17802default:
17803break;
17804}
17805break;
17806default:
17807break;
17808}
17809break;
17810default:
17811break;
17812}
17813break;
17814default:
17815break;
17816}
17817break;
17818case Arg::Index:
17819switch (this->args[2].kind()) {
17820case Arg::Tmp:
17821switch (this->args[3].kind()) {
17822case Arg::Tmp:
17823switch (this->args[4].kind()) {
17824case Arg::Tmp:
17825switch (this->args[5].kind()) {
17826case Arg::Tmp:
17827#if CPU(X86_64)
17828if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
17829OPGEN_RETURN(false);
17830if (!args[2].tmp().isGP())
17831OPGEN_RETURN(false);
17832if (!args[3].tmp().isFP())
17833OPGEN_RETURN(false);
17834if (!args[4].tmp().isFP())
17835OPGEN_RETURN(false);
17836if (!args[5].tmp().isFP())
17837OPGEN_RETURN(false);
17838OPGEN_RETURN(true);
17839#endif
17840break;
17841break;
17842default:
17843break;
17844}
17845break;
17846default:
17847break;
17848}
17849break;
17850default:
17851break;
17852}
17853break;
17854default:
17855break;
17856}
17857break;
17858default:
17859break;
17860}
17861break;
17862default:
17863break;
17864}
17865break;
17866default:
17867break;
17868}
17869break;
17870case Opcode::MoveDoubleConditionallyTest32:
17871switch (this->args.size()) {
17872case 6:
17873switch (this->args[0].kind()) {
17874case Arg::ResCond:
17875switch (this->args[1].kind()) {
17876case Arg::Tmp:
17877switch (this->args[2].kind()) {
17878case Arg::Tmp:
17879switch (this->args[3].kind()) {
17880case Arg::Tmp:
17881switch (this->args[4].kind()) {
17882case Arg::Tmp:
17883switch (this->args[5].kind()) {
17884case Arg::Tmp:
17885if (!args[1].tmp().isGP())
17886OPGEN_RETURN(false);
17887if (!args[2].tmp().isGP())
17888OPGEN_RETURN(false);
17889if (!args[3].tmp().isFP())
17890OPGEN_RETURN(false);
17891if (!args[4].tmp().isFP())
17892OPGEN_RETURN(false);
17893if (!args[5].tmp().isFP())
17894OPGEN_RETURN(false);
17895OPGEN_RETURN(true);
17896break;
17897break;
17898default:
17899break;
17900}
17901break;
17902default:
17903break;
17904}
17905break;
17906default:
17907break;
17908}
17909break;
17910case Arg::BitImm:
17911switch (this->args[3].kind()) {
17912case Arg::Tmp:
17913switch (this->args[4].kind()) {
17914case Arg::Tmp:
17915switch (this->args[5].kind()) {
17916case Arg::Tmp:
17917if (!args[1].tmp().isGP())
17918OPGEN_RETURN(false);
17919if (!Arg::isValidBitImmForm(args[2].value()))
17920OPGEN_RETURN(false);
17921if (!args[3].tmp().isFP())
17922OPGEN_RETURN(false);
17923if (!args[4].tmp().isFP())
17924OPGEN_RETURN(false);
17925if (!args[5].tmp().isFP())
17926OPGEN_RETURN(false);
17927OPGEN_RETURN(true);
17928break;
17929break;
17930default:
17931break;
17932}
17933break;
17934default:
17935break;
17936}
17937break;
17938default:
17939break;
17940}
17941break;
17942default:
17943break;
17944}
17945break;
17946case Arg::Addr:
17947case Arg::Stack:
17948case Arg::CallArg:
17949switch (this->args[2].kind()) {
17950case Arg::Imm:
17951switch (this->args[3].kind()) {
17952case Arg::Tmp:
17953switch (this->args[4].kind()) {
17954case Arg::Tmp:
17955switch (this->args[5].kind()) {
17956case Arg::Tmp:
17957#if CPU(X86) || CPU(X86_64)
17958if (!Arg::isValidAddrForm(args[1].offset()))
17959OPGEN_RETURN(false);
17960if (!Arg::isValidImmForm(args[2].value()))
17961OPGEN_RETURN(false);
17962if (!args[3].tmp().isFP())
17963OPGEN_RETURN(false);
17964if (!args[4].tmp().isFP())
17965OPGEN_RETURN(false);
17966if (!args[5].tmp().isFP())
17967OPGEN_RETURN(false);
17968OPGEN_RETURN(true);
17969#endif
17970break;
17971break;
17972default:
17973break;
17974}
17975break;
17976default:
17977break;
17978}
17979break;
17980default:
17981break;
17982}
17983break;
17984default:
17985break;
17986}
17987break;
17988case Arg::Index:
17989switch (this->args[2].kind()) {
17990case Arg::Imm:
17991switch (this->args[3].kind()) {
17992case Arg::Tmp:
17993switch (this->args[4].kind()) {
17994case Arg::Tmp:
17995switch (this->args[5].kind()) {
17996case Arg::Tmp:
17997#if CPU(X86) || CPU(X86_64)
17998if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width32))
17999OPGEN_RETURN(false);
18000if (!Arg::isValidImmForm(args[2].value()))
18001OPGEN_RETURN(false);
18002if (!args[3].tmp().isFP())
18003OPGEN_RETURN(false);
18004if (!args[4].tmp().isFP())
18005OPGEN_RETURN(false);
18006if (!args[5].tmp().isFP())
18007OPGEN_RETURN(false);
18008OPGEN_RETURN(true);
18009#endif
18010break;
18011break;
18012default:
18013break;
18014}
18015break;
18016default:
18017break;
18018}
18019break;
18020default:
18021break;
18022}
18023break;
18024default:
18025break;
18026}
18027break;
18028default:
18029break;
18030}
18031break;
18032default:
18033break;
18034}
18035break;
18036default:
18037break;
18038}
18039break;
18040case Opcode::MoveDoubleConditionallyTest64:
18041switch (this->args.size()) {
18042case 6:
18043switch (this->args[0].kind()) {
18044case Arg::ResCond:
18045switch (this->args[1].kind()) {
18046case Arg::Tmp:
18047switch (this->args[2].kind()) {
18048case Arg::Tmp:
18049switch (this->args[3].kind()) {
18050case Arg::Tmp:
18051switch (this->args[4].kind()) {
18052case Arg::Tmp:
18053switch (this->args[5].kind()) {
18054case Arg::Tmp:
18055#if CPU(X86_64) || CPU(ARM64)
18056if (!args[1].tmp().isGP())
18057OPGEN_RETURN(false);
18058if (!args[2].tmp().isGP())
18059OPGEN_RETURN(false);
18060if (!args[3].tmp().isFP())
18061OPGEN_RETURN(false);
18062if (!args[4].tmp().isFP())
18063OPGEN_RETURN(false);
18064if (!args[5].tmp().isFP())
18065OPGEN_RETURN(false);
18066OPGEN_RETURN(true);
18067#endif
18068break;
18069break;
18070default:
18071break;
18072}
18073break;
18074default:
18075break;
18076}
18077break;
18078default:
18079break;
18080}
18081break;
18082case Arg::Imm:
18083switch (this->args[3].kind()) {
18084case Arg::Tmp:
18085switch (this->args[4].kind()) {
18086case Arg::Tmp:
18087switch (this->args[5].kind()) {
18088case Arg::Tmp:
18089#if CPU(X86_64)
18090if (!args[1].tmp().isGP())
18091OPGEN_RETURN(false);
18092if (!Arg::isValidImmForm(args[2].value()))
18093OPGEN_RETURN(false);
18094if (!args[3].tmp().isFP())
18095OPGEN_RETURN(false);
18096if (!args[4].tmp().isFP())
18097OPGEN_RETURN(false);
18098if (!args[5].tmp().isFP())
18099OPGEN_RETURN(false);
18100OPGEN_RETURN(true);
18101#endif
18102break;
18103break;
18104default:
18105break;
18106}
18107break;
18108default:
18109break;
18110}
18111break;
18112default:
18113break;
18114}
18115break;
18116default:
18117break;
18118}
18119break;
18120case Arg::Addr:
18121case Arg::Stack:
18122case Arg::CallArg:
18123switch (this->args[2].kind()) {
18124case Arg::Imm:
18125switch (this->args[3].kind()) {
18126case Arg::Tmp:
18127switch (this->args[4].kind()) {
18128case Arg::Tmp:
18129switch (this->args[5].kind()) {
18130case Arg::Tmp:
18131#if CPU(X86_64)
18132if (!Arg::isValidAddrForm(args[1].offset()))
18133OPGEN_RETURN(false);
18134if (!Arg::isValidImmForm(args[2].value()))
18135OPGEN_RETURN(false);
18136if (!args[3].tmp().isFP())
18137OPGEN_RETURN(false);
18138if (!args[4].tmp().isFP())
18139OPGEN_RETURN(false);
18140if (!args[5].tmp().isFP())
18141OPGEN_RETURN(false);
18142OPGEN_RETURN(true);
18143#endif
18144break;
18145break;
18146default:
18147break;
18148}
18149break;
18150default:
18151break;
18152}
18153break;
18154default:
18155break;
18156}
18157break;
18158case Arg::Tmp:
18159switch (this->args[3].kind()) {
18160case Arg::Tmp:
18161switch (this->args[4].kind()) {
18162case Arg::Tmp:
18163switch (this->args[5].kind()) {
18164case Arg::Tmp:
18165#if CPU(X86_64)
18166if (!Arg::isValidAddrForm(args[1].offset()))
18167OPGEN_RETURN(false);
18168if (!args[2].tmp().isGP())
18169OPGEN_RETURN(false);
18170if (!args[3].tmp().isFP())
18171OPGEN_RETURN(false);
18172if (!args[4].tmp().isFP())
18173OPGEN_RETURN(false);
18174if (!args[5].tmp().isFP())
18175OPGEN_RETURN(false);
18176OPGEN_RETURN(true);
18177#endif
18178break;
18179break;
18180default:
18181break;
18182}
18183break;
18184default:
18185break;
18186}
18187break;
18188default:
18189break;
18190}
18191break;
18192default:
18193break;
18194}
18195break;
18196case Arg::Index:
18197switch (this->args[2].kind()) {
18198case Arg::Imm:
18199switch (this->args[3].kind()) {
18200case Arg::Tmp:
18201switch (this->args[4].kind()) {
18202case Arg::Tmp:
18203switch (this->args[5].kind()) {
18204case Arg::Tmp:
18205#if CPU(X86_64)
18206if (!Arg::isValidIndexForm(args[1].scale(), args[1].offset(), Width64))
18207OPGEN_RETURN(false);
18208if (!Arg::isValidImmForm(args[2].value()))
18209OPGEN_RETURN(false);
18210if (!args[3].tmp().isFP())
18211OPGEN_RETURN(false);
18212if (!args[4].tmp().isFP())
18213OPGEN_RETURN(false);
18214if (!args[5].tmp().isFP())
18215OPGEN_RETURN(false);
18216OPGEN_RETURN(true);
18217#endif
18218break;
18219break;
18220default:
18221break;
18222}
18223break;
18224default:
18225break;
18226}
18227break;
18228default:
18229break;
18230}
18231break;
18232default:
18233break;
18234}
18235break;
18236default:
18237break;
18238}
18239break;
18240default:
18241break;
18242}
18243break;
18244default:
18245break;
18246}
18247break;
18248case Opcode::MoveDoubleConditionallyDouble:
18249switch (this->args.size()) {
18250case 6:
18251switch (this->args[0].kind()) {
18252case Arg::DoubleCond:
18253switch (this->args[1].kind()) {
18254case Arg::Tmp:
18255switch (this->args[2].kind()) {
18256case Arg::Tmp:
18257switch (this->args[3].kind()) {
18258case Arg::Tmp:
18259switch (this->args[4].kind()) {
18260case Arg::Tmp:
18261switch (this->args[5].kind()) {
18262case Arg::Tmp:
18263if (!args[1].tmp().isFP())
18264OPGEN_RETURN(false);
18265if (!args[2].tmp().isFP())
18266OPGEN_RETURN(false);
18267if (!args[3].tmp().isFP())
18268OPGEN_RETURN(false);
18269if (!args[4].tmp().isFP())
18270OPGEN_RETURN(false);
18271if (!args[5].tmp().isFP())
18272OPGEN_RETURN(false);
18273OPGEN_RETURN(true);
18274break;
18275break;
18276default:
18277break;
18278}
18279break;
18280default:
18281break;
18282}
18283break;
18284default:
18285break;
18286}
18287break;
18288default:
18289break;
18290}
18291break;
18292default:
18293break;
18294}
18295break;
18296default:
18297break;
18298}
18299break;
18300default:
18301break;
18302}
18303break;
18304case Opcode::MoveDoubleConditionallyFloat:
18305switch (this->args.size()) {
18306case 6:
18307switch (this->args[0].kind()) {
18308case Arg::DoubleCond:
18309switch (this->args[1].kind()) {
18310case Arg::Tmp:
18311switch (this->args[2].kind()) {
18312case Arg::Tmp:
18313switch (this->args[3].kind()) {
18314case Arg::Tmp:
18315switch (this->args[4].kind()) {
18316case Arg::Tmp:
18317switch (this->args[5].kind()) {
18318case Arg::Tmp:
18319if (!args[1].tmp().isFP())
18320OPGEN_RETURN(false);
18321if (!args[2].tmp().isFP())
18322OPGEN_RETURN(false);
18323if (!args[3].tmp().isFP())
18324OPGEN_RETURN(false);
18325if (!args[4].tmp().isFP())
18326OPGEN_RETURN(false);
18327if (!args[5].tmp().isFP())
18328OPGEN_RETURN(false);
18329OPGEN_RETURN(true);
18330break;
18331break;
18332default:
18333break;
18334}
18335break;
18336default:
18337break;
18338}
18339break;
18340default:
18341break;
18342}
18343break;
18344default:
18345break;
18346}
18347break;
18348default:
18349break;
18350}
18351break;
18352default:
18353break;
18354}
18355break;
18356default:
18357break;
18358}
18359break;
18360case Opcode::MemoryFence:
18361switch (this->args.size()) {
18362case 0:
18363OPGEN_RETURN(true);
18364break;
18365break;
18366default:
18367break;
18368}
18369break;
18370case Opcode::StoreFence:
18371switch (this->args.size()) {
18372case 0:
18373OPGEN_RETURN(true);
18374break;
18375break;
18376default:
18377break;
18378}
18379break;
18380case Opcode::LoadFence:
18381switch (this->args.size()) {
18382case 0:
18383OPGEN_RETURN(true);
18384break;
18385break;
18386default:
18387break;
18388}
18389break;
18390case Opcode::Jump:
18391switch (this->args.size()) {
18392case 0:
18393OPGEN_RETURN(true);
18394break;
18395break;
18396default:
18397break;
18398}
18399break;
18400case Opcode::RetVoid:
18401switch (this->args.size()) {
18402case 0:
18403OPGEN_RETURN(true);
18404break;
18405break;
18406default:
18407break;
18408}
18409break;
18410case Opcode::Ret32:
18411switch (this->args.size()) {
18412case 1:
18413switch (this->args[0].kind()) {
18414case Arg::Tmp:
18415if (!args[0].tmp().isGP())
18416OPGEN_RETURN(false);
18417OPGEN_RETURN(true);
18418break;
18419break;
18420default:
18421break;
18422}
18423break;
18424default:
18425break;
18426}
18427break;
18428case Opcode::Ret64:
18429switch (this->args.size()) {
18430case 1:
18431switch (this->args[0].kind()) {
18432case Arg::Tmp:
18433#if CPU(X86_64) || CPU(ARM64)
18434if (!args[0].tmp().isGP())
18435OPGEN_RETURN(false);
18436OPGEN_RETURN(true);
18437#endif
18438break;
18439break;
18440default:
18441break;
18442}
18443break;
18444default:
18445break;
18446}
18447break;
18448case Opcode::RetFloat:
18449switch (this->args.size()) {
18450case 1:
18451switch (this->args[0].kind()) {
18452case Arg::Tmp:
18453if (!args[0].tmp().isFP())
18454OPGEN_RETURN(false);
18455OPGEN_RETURN(true);
18456break;
18457break;
18458default:
18459break;
18460}
18461break;
18462default:
18463break;
18464}
18465break;
18466case Opcode::RetDouble:
18467switch (this->args.size()) {
18468case 1:
18469switch (this->args[0].kind()) {
18470case Arg::Tmp:
18471if (!args[0].tmp().isFP())
18472OPGEN_RETURN(false);
18473OPGEN_RETURN(true);
18474break;
18475break;
18476default:
18477break;
18478}
18479break;
18480default:
18481break;
18482}
18483break;
18484case Opcode::Oops:
18485switch (this->args.size()) {
18486case 0:
18487OPGEN_RETURN(true);
18488break;
18489break;
18490default:
18491break;
18492}
18493break;
18494case Opcode::EntrySwitch:
18495OPGEN_RETURN(EntrySwitchCustom::isValidForm(*this));
18496break;
18497case Opcode::Shuffle:
18498OPGEN_RETURN(ShuffleCustom::isValidForm(*this));
18499break;
18500case Opcode::Patch:
18501OPGEN_RETURN(PatchCustom::isValidForm(*this));
18502break;
18503case Opcode::CCall:
18504OPGEN_RETURN(CCallCustom::isValidForm(*this));
18505break;
18506case Opcode::ColdCCall:
18507OPGEN_RETURN(ColdCCallCustom::isValidForm(*this));
18508break;
18509case Opcode::WasmBoundsCheck:
18510OPGEN_RETURN(WasmBoundsCheckCustom::isValidForm(*this));
18511break;
18512default:
18513break;
18514}
18515return false;
18516}
18517bool Inst::admitsStack(unsigned argIndex)
18518{
18519switch (kind.opcode) {
18520case Opcode::Nop:
18521switch (argIndex) {
18522default:
18523break;
18524}
18525break;
18526case Opcode::Add32:
18527switch (argIndex) {
18528case 0:
18529switch (args.size()) {
18530case 2:
18531switch (Arg::Addr) {
18532case Arg::Tmp:
18533break;
18534case Arg::Imm:
18535break;
18536case Arg::Addr:
18537case Arg::Stack:
18538case Arg::CallArg:
18539switch (args[1].kind()) {
18540case Arg::Tmp:
18541#if CPU(X86) || CPU(X86_64)
18542OPGEN_RETURN(true);
18543#endif
18544break;
18545break;
18546default:
18547break;
18548}
18549break;
18550case Arg::Index:
18551break;
18552default:
18553break;
18554}
18555break;
18556default:
18557break;
18558}
18559break;
18560case 1:
18561switch (args.size()) {
18562case 2:
18563switch (args[0].kind()) {
18564case Arg::Tmp:
18565switch (Arg::Addr) {
18566case Arg::Tmp:
18567break;
18568case Arg::Addr:
18569case Arg::Stack:
18570case Arg::CallArg:
18571#if CPU(X86) || CPU(X86_64)
18572OPGEN_RETURN(true);
18573#endif
18574break;
18575break;
18576case Arg::Index:
18577break;
18578default:
18579break;
18580}
18581break;
18582case Arg::Imm:
18583switch (Arg::Addr) {
18584case Arg::Addr:
18585case Arg::Stack:
18586case Arg::CallArg:
18587#if CPU(X86) || CPU(X86_64)
18588OPGEN_RETURN(true);
18589#endif
18590break;
18591break;
18592case Arg::Index:
18593break;
18594case Arg::Tmp:
18595break;
18596default:
18597break;
18598}
18599break;
18600case Arg::Addr:
18601case Arg::Stack:
18602case Arg::CallArg:
18603break;
18604case Arg::Index:
18605break;
18606default:
18607break;
18608}
18609break;
18610default:
18611break;
18612}
18613break;
18614case 2:
18615OPGEN_RETURN(false);
18616break;
18617default:
18618break;
18619}
18620break;
18621case Opcode::Add8:
18622switch (argIndex) {
18623case 0:
18624OPGEN_RETURN(false);
18625break;
18626case 1:
18627switch (args[0].kind()) {
18628case Arg::Imm:
18629switch (Arg::Addr) {
18630case Arg::Addr:
18631case Arg::Stack:
18632case Arg::CallArg:
18633#if CPU(X86) || CPU(X86_64)
18634OPGEN_RETURN(true);
18635#endif
18636break;
18637break;
18638case Arg::Index:
18639break;
18640default:
18641break;
18642}
18643break;
18644case Arg::Tmp:
18645switch (Arg::Addr) {
18646case Arg::Addr:
18647case Arg::Stack:
18648case Arg::CallArg:
18649#if CPU(X86) || CPU(X86_64)
18650OPGEN_RETURN(true);
18651#endif
18652break;
18653break;
18654case Arg::Index:
18655break;
18656default:
18657break;
18658}
18659break;
18660default:
18661break;
18662}
18663break;
18664default:
18665break;
18666}
18667break;
18668case Opcode::Add16:
18669switch (argIndex) {
18670case 0:
18671OPGEN_RETURN(false);
18672break;
18673case 1:
18674switch (args[0].kind()) {
18675case Arg::Imm:
18676switch (Arg::Addr) {
18677case Arg::Addr:
18678case Arg::Stack:
18679case Arg::CallArg:
18680#if CPU(X86) || CPU(X86_64)
18681OPGEN_RETURN(true);
18682#endif
18683break;
18684break;
18685case Arg::Index:
18686break;
18687default:
18688break;
18689}
18690break;
18691case Arg::Tmp:
18692switch (Arg::Addr) {
18693case Arg::Addr:
18694case Arg::Stack:
18695case Arg::CallArg:
18696#if CPU(X86) || CPU(X86_64)
18697OPGEN_RETURN(true);
18698#endif
18699break;
18700break;
18701case Arg::Index:
18702break;
18703default:
18704break;
18705}
18706break;
18707default:
18708break;
18709}
18710break;
18711default:
18712break;
18713}
18714break;
18715case Opcode::Add64:
18716switch (argIndex) {
18717case 0:
18718switch (args.size()) {
18719case 2:
18720switch (Arg::Addr) {
18721case Arg::Tmp:
18722break;
18723case Arg::Imm:
18724break;
18725case Arg::Addr:
18726case Arg::Stack:
18727case Arg::CallArg:
18728switch (args[1].kind()) {
18729case Arg::Tmp:
18730#if CPU(X86_64)
18731OPGEN_RETURN(true);
18732#endif
18733break;
18734break;
18735default:
18736break;
18737}
18738break;
18739case Arg::Index:
18740break;
18741default:
18742break;
18743}
18744break;
18745default:
18746break;
18747}
18748break;
18749case 1:
18750switch (args.size()) {
18751case 2:
18752switch (args[0].kind()) {
18753case Arg::Tmp:
18754switch (Arg::Addr) {
18755case Arg::Tmp:
18756break;
18757case Arg::Addr:
18758case Arg::Stack:
18759case Arg::CallArg:
18760#if CPU(X86_64)
18761OPGEN_RETURN(true);
18762#endif
18763break;
18764break;
18765case Arg::Index:
18766break;
18767default:
18768break;
18769}
18770break;
18771case Arg::Imm:
18772switch (Arg::Addr) {
18773case Arg::Addr:
18774case Arg::Stack:
18775case Arg::CallArg:
18776#if CPU(X86_64)
18777OPGEN_RETURN(true);
18778#endif
18779break;
18780break;
18781case Arg::Index:
18782break;
18783case Arg::Tmp:
18784break;
18785default:
18786break;
18787}
18788break;
18789case Arg::Addr:
18790case Arg::Stack:
18791case Arg::CallArg:
18792break;
18793case Arg::Index:
18794break;
18795default:
18796break;
18797}
18798break;
18799default:
18800break;
18801}
18802break;
18803case 2:
18804OPGEN_RETURN(false);
18805break;
18806default:
18807break;
18808}
18809break;
18810case Opcode::AddDouble:
18811switch (argIndex) {
18812case 0:
18813switch (args.size()) {
18814case 3:
18815switch (Arg::Addr) {
18816case Arg::Tmp:
18817break;
18818case Arg::Addr:
18819case Arg::Stack:
18820case Arg::CallArg:
18821switch (args[1].kind()) {
18822case Arg::Tmp:
18823switch (args[2].kind()) {
18824case Arg::Tmp:
18825#if CPU(X86) || CPU(X86_64)
18826OPGEN_RETURN(true);
18827#endif
18828break;
18829break;
18830default:
18831break;
18832}
18833break;
18834default:
18835break;
18836}
18837break;
18838case Arg::Index:
18839break;
18840default:
18841break;
18842}
18843break;
18844case 2:
18845switch (Arg::Addr) {
18846case Arg::Tmp:
18847break;
18848case Arg::Addr:
18849case Arg::Stack:
18850case Arg::CallArg:
18851switch (args[1].kind()) {
18852case Arg::Tmp:
18853#if CPU(X86) || CPU(X86_64)
18854OPGEN_RETURN(true);
18855#endif
18856break;
18857break;
18858default:
18859break;
18860}
18861break;
18862default:
18863break;
18864}
18865break;
18866default:
18867break;
18868}
18869break;
18870case 1:
18871switch (args.size()) {
18872case 3:
18873switch (args[0].kind()) {
18874case Arg::Tmp:
18875switch (Arg::Addr) {
18876case Arg::Tmp:
18877break;
18878case Arg::Addr:
18879case Arg::Stack:
18880case Arg::CallArg:
18881switch (args[2].kind()) {
18882case Arg::Tmp:
18883#if CPU(X86) || CPU(X86_64)
18884OPGEN_RETURN(true);
18885#endif
18886break;
18887break;
18888default:
18889break;
18890}
18891break;
18892default:
18893break;
18894}
18895break;
18896case Arg::Addr:
18897case Arg::Stack:
18898case Arg::CallArg:
18899break;
18900case Arg::Index:
18901break;
18902default:
18903break;
18904}
18905break;
18906default:
18907break;
18908}
18909break;
18910case 2:
18911OPGEN_RETURN(false);
18912break;
18913default:
18914break;
18915}
18916break;
18917case Opcode::AddFloat:
18918switch (argIndex) {
18919case 0:
18920switch (args.size()) {
18921case 3:
18922switch (Arg::Addr) {
18923case Arg::Tmp:
18924break;
18925case Arg::Addr:
18926case Arg::Stack:
18927case Arg::CallArg:
18928switch (args[1].kind()) {
18929case Arg::Tmp:
18930switch (args[2].kind()) {
18931case Arg::Tmp:
18932#if CPU(X86) || CPU(X86_64)
18933OPGEN_RETURN(true);
18934#endif
18935break;
18936break;
18937default:
18938break;
18939}
18940break;
18941default:
18942break;
18943}
18944break;
18945case Arg::Index:
18946break;
18947default:
18948break;
18949}
18950break;
18951case 2:
18952switch (Arg::Addr) {
18953case Arg::Tmp:
18954break;
18955case Arg::Addr:
18956case Arg::Stack:
18957case Arg::CallArg:
18958switch (args[1].kind()) {
18959case Arg::Tmp:
18960#if CPU(X86) || CPU(X86_64)
18961OPGEN_RETURN(true);
18962#endif
18963break;
18964break;
18965default:
18966break;
18967}
18968break;
18969default:
18970break;
18971}
18972break;
18973default:
18974break;
18975}
18976break;
18977case 1:
18978switch (args.size()) {
18979case 3:
18980switch (args[0].kind()) {
18981case Arg::Tmp:
18982switch (Arg::Addr) {
18983case Arg::Tmp:
18984break;
18985case Arg::Addr:
18986case Arg::Stack:
18987case Arg::CallArg:
18988switch (args[2].kind()) {
18989case Arg::Tmp:
18990#if CPU(X86) || CPU(X86_64)
18991OPGEN_RETURN(true);
18992#endif
18993break;
18994break;
18995default:
18996break;
18997}
18998break;
18999default:
19000break;
19001}
19002break;
19003case Arg::Addr:
19004case Arg::Stack:
19005case Arg::CallArg:
19006break;
19007case Arg::Index:
19008break;
19009default:
19010break;
19011}
19012break;
19013default:
19014break;
19015}
19016break;
19017case 2:
19018OPGEN_RETURN(false);
19019break;
19020default:
19021break;
19022}
19023break;
19024case Opcode::Sub32:
19025switch (argIndex) {
19026case 0:
19027switch (args.size()) {
19028case 2:
19029switch (Arg::Addr) {
19030case Arg::Tmp:
19031break;
19032case Arg::Imm:
19033break;
19034case Arg::Addr:
19035case Arg::Stack:
19036case Arg::CallArg:
19037switch (args[1].kind()) {
19038case Arg::Tmp:
19039#if CPU(X86) || CPU(X86_64)
19040OPGEN_RETURN(true);
19041#endif
19042break;
19043break;
19044default:
19045break;
19046}
19047break;
19048case Arg::Index:
19049break;
19050default:
19051break;
19052}
19053break;
19054default:
19055break;
19056}
19057break;
19058case 1:
19059switch (args.size()) {
19060case 2:
19061switch (args[0].kind()) {
19062case Arg::Tmp:
19063switch (Arg::Addr) {
19064case Arg::Tmp:
19065break;
19066case Arg::Addr:
19067case Arg::Stack:
19068case Arg::CallArg:
19069#if CPU(X86) || CPU(X86_64)
19070OPGEN_RETURN(true);
19071#endif
19072break;
19073break;
19074case Arg::Index:
19075break;
19076default:
19077break;
19078}
19079break;
19080case Arg::Imm:
19081switch (Arg::Addr) {
19082case Arg::Addr:
19083case Arg::Stack:
19084case Arg::CallArg:
19085#if CPU(X86) || CPU(X86_64)
19086OPGEN_RETURN(true);
19087#endif
19088break;
19089break;
19090case Arg::Index:
19091break;
19092case Arg::Tmp:
19093break;
19094default:
19095break;
19096}
19097break;
19098case Arg::Addr:
19099case Arg::Stack:
19100case Arg::CallArg:
19101break;
19102case Arg::Index:
19103break;
19104default:
19105break;
19106}
19107break;
19108default:
19109break;
19110}
19111break;
19112case 2:
19113OPGEN_RETURN(false);
19114break;
19115default:
19116break;
19117}
19118break;
19119case Opcode::Sub64:
19120switch (argIndex) {
19121case 0:
19122switch (args.size()) {
19123case 2:
19124switch (Arg::Addr) {
19125case Arg::Tmp:
19126break;
19127case Arg::Imm:
19128break;
19129case Arg::Addr:
19130case Arg::Stack:
19131case Arg::CallArg:
19132switch (args[1].kind()) {
19133case Arg::Tmp:
19134#if CPU(X86_64)
19135OPGEN_RETURN(true);
19136#endif
19137break;
19138break;
19139default:
19140break;
19141}
19142break;
19143case Arg::Index:
19144break;
19145default:
19146break;
19147}
19148break;
19149default:
19150break;
19151}
19152break;
19153case 1:
19154switch (args.size()) {
19155case 2:
19156switch (args[0].kind()) {
19157case Arg::Tmp:
19158switch (Arg::Addr) {
19159case Arg::Tmp:
19160break;
19161case Arg::Addr:
19162case Arg::Stack:
19163case Arg::CallArg:
19164#if CPU(X86_64)
19165OPGEN_RETURN(true);
19166#endif
19167break;
19168break;
19169case Arg::Index:
19170break;
19171default:
19172break;
19173}
19174break;
19175case Arg::Imm:
19176switch (Arg::Addr) {
19177case Arg::Addr:
19178case Arg::Stack:
19179case Arg::CallArg:
19180#if CPU(X86_64)
19181OPGEN_RETURN(true);
19182#endif
19183break;
19184break;
19185case Arg::Index:
19186break;
19187case Arg::Tmp:
19188break;
19189default:
19190break;
19191}
19192break;
19193case Arg::Addr:
19194case Arg::Stack:
19195case Arg::CallArg:
19196break;
19197case Arg::Index:
19198break;
19199default:
19200break;
19201}
19202break;
19203default:
19204break;
19205}
19206break;
19207case 2:
19208OPGEN_RETURN(false);
19209break;
19210default:
19211break;
19212}
19213break;
19214case Opcode::SubDouble:
19215switch (argIndex) {
19216case 0:
19217switch (args.size()) {
19218case 2:
19219switch (Arg::Addr) {
19220case Arg::Tmp:
19221break;
19222case Arg::Addr:
19223case Arg::Stack:
19224case Arg::CallArg:
19225switch (args[1].kind()) {
19226case Arg::Tmp:
19227#if CPU(X86) || CPU(X86_64)
19228OPGEN_RETURN(true);
19229#endif
19230break;
19231break;
19232default:
19233break;
19234}
19235break;
19236default:
19237break;
19238}
19239break;
19240default:
19241break;
19242}
19243break;
19244case 1:
19245switch (args.size()) {
19246case 3:
19247switch (args[0].kind()) {
19248case Arg::Tmp:
19249switch (Arg::Addr) {
19250case Arg::Tmp:
19251break;
19252case Arg::Addr:
19253case Arg::Stack:
19254case Arg::CallArg:
19255switch (args[2].kind()) {
19256case Arg::Tmp:
19257#if CPU(X86) || CPU(X86_64)
19258OPGEN_RETURN(true);
19259#endif
19260break;
19261break;
19262default:
19263break;
19264}
19265break;
19266case Arg::Index:
19267break;
19268default:
19269break;
19270}
19271break;
19272default:
19273break;
19274}
19275break;
19276default:
19277break;
19278}
19279break;
19280case 2:
19281OPGEN_RETURN(false);
19282break;
19283default:
19284break;
19285}
19286break;
19287case Opcode::SubFloat:
19288switch (argIndex) {
19289case 0:
19290switch (args.size()) {
19291case 2:
19292switch (Arg::Addr) {
19293case Arg::Tmp:
19294break;
19295case Arg::Addr:
19296case Arg::Stack:
19297case Arg::CallArg:
19298switch (args[1].kind()) {
19299case Arg::Tmp:
19300#if CPU(X86) || CPU(X86_64)
19301OPGEN_RETURN(true);
19302#endif
19303break;
19304break;
19305default:
19306break;
19307}
19308break;
19309default:
19310break;
19311}
19312break;
19313default:
19314break;
19315}
19316break;
19317case 1:
19318switch (args.size()) {
19319case 3:
19320switch (args[0].kind()) {
19321case Arg::Tmp:
19322switch (Arg::Addr) {
19323case Arg::Tmp:
19324break;
19325case Arg::Addr:
19326case Arg::Stack:
19327case Arg::CallArg:
19328switch (args[2].kind()) {
19329case Arg::Tmp:
19330#if CPU(X86) || CPU(X86_64)
19331OPGEN_RETURN(true);
19332#endif
19333break;
19334break;
19335default:
19336break;
19337}
19338break;
19339case Arg::Index:
19340break;
19341default:
19342break;
19343}
19344break;
19345default:
19346break;
19347}
19348break;
19349default:
19350break;
19351}
19352break;
19353case 2:
19354OPGEN_RETURN(false);
19355break;
19356default:
19357break;
19358}
19359break;
19360case Opcode::Neg32:
19361switch (argIndex) {
19362case 0:
19363switch (Arg::Addr) {
19364case Arg::Tmp:
19365break;
19366case Arg::Addr:
19367case Arg::Stack:
19368case Arg::CallArg:
19369#if CPU(X86) || CPU(X86_64)
19370OPGEN_RETURN(true);
19371#endif
19372break;
19373break;
19374case Arg::Index:
19375break;
19376default:
19377break;
19378}
19379break;
19380default:
19381break;
19382}
19383break;
19384case Opcode::Neg64:
19385switch (argIndex) {
19386case 0:
19387switch (Arg::Addr) {
19388case Arg::Tmp:
19389break;
19390case Arg::Addr:
19391case Arg::Stack:
19392case Arg::CallArg:
19393#if CPU(X86_64)
19394OPGEN_RETURN(true);
19395#endif
19396break;
19397break;
19398case Arg::Index:
19399break;
19400default:
19401break;
19402}
19403break;
19404default:
19405break;
19406}
19407break;
19408case Opcode::NegateDouble:
19409switch (argIndex) {
19410case 0:
19411OPGEN_RETURN(false);
19412break;
19413case 1:
19414OPGEN_RETURN(false);
19415break;
19416default:
19417break;
19418}
19419break;
19420case Opcode::NegateFloat:
19421switch (argIndex) {
19422case 0:
19423OPGEN_RETURN(false);
19424break;
19425case 1:
19426OPGEN_RETURN(false);
19427break;
19428default:
19429break;
19430}
19431break;
19432case Opcode::Mul32:
19433switch (argIndex) {
19434case 0:
19435switch (args.size()) {
19436case 2:
19437switch (Arg::Addr) {
19438case Arg::Tmp:
19439break;
19440case Arg::Addr:
19441case Arg::Stack:
19442case Arg::CallArg:
19443switch (args[1].kind()) {
19444case Arg::Tmp:
19445#if CPU(X86) || CPU(X86_64)
19446OPGEN_RETURN(true);
19447#endif
19448break;
19449break;
19450default:
19451break;
19452}
19453break;
19454default:
19455break;
19456}
19457break;
19458case 3:
19459switch (Arg::Addr) {
19460case Arg::Tmp:
19461break;
19462case Arg::Addr:
19463case Arg::Stack:
19464case Arg::CallArg:
19465switch (args[1].kind()) {
19466case Arg::Tmp:
19467switch (args[2].kind()) {
19468case Arg::Tmp:
19469#if CPU(X86) || CPU(X86_64)
19470OPGEN_RETURN(true);
19471#endif
19472break;
19473break;
19474default:
19475break;
19476}
19477break;
19478default:
19479break;
19480}
19481break;
19482case Arg::Imm:
19483break;
19484default:
19485break;
19486}
19487break;
19488default:
19489break;
19490}
19491break;
19492case 1:
19493switch (args.size()) {
19494case 3:
19495switch (args[0].kind()) {
19496case Arg::Tmp:
19497switch (Arg::Addr) {
19498case Arg::Tmp:
19499break;
19500case Arg::Addr:
19501case Arg::Stack:
19502case Arg::CallArg:
19503switch (args[2].kind()) {
19504case Arg::Tmp:
19505#if CPU(X86) || CPU(X86_64)
19506OPGEN_RETURN(true);
19507#endif
19508break;
19509break;
19510default:
19511break;
19512}
19513break;
19514default:
19515break;
19516}
19517break;
19518case Arg::Addr:
19519case Arg::Stack:
19520case Arg::CallArg:
19521break;
19522case Arg::Imm:
19523break;
19524default:
19525break;
19526}
19527break;
19528default:
19529break;
19530}
19531break;
19532case 2:
19533OPGEN_RETURN(false);
19534break;
19535default:
19536break;
19537}
19538break;
19539case Opcode::Mul64:
19540switch (argIndex) {
19541case 0:
19542OPGEN_RETURN(false);
19543break;
19544case 1:
19545OPGEN_RETURN(false);
19546break;
19547case 2:
19548OPGEN_RETURN(false);
19549break;
19550default:
19551break;
19552}
19553break;
19554case Opcode::MultiplyAdd32:
19555switch (argIndex) {
19556case 0:
19557OPGEN_RETURN(false);
19558break;
19559case 1:
19560OPGEN_RETURN(false);
19561break;
19562case 2:
19563OPGEN_RETURN(false);
19564break;
19565case 3:
19566OPGEN_RETURN(false);
19567break;
19568default:
19569break;
19570}
19571break;
19572case Opcode::MultiplyAdd64:
19573switch (argIndex) {
19574case 0:
19575OPGEN_RETURN(false);
19576break;
19577case 1:
19578OPGEN_RETURN(false);
19579break;
19580case 2:
19581OPGEN_RETURN(false);
19582break;
19583case 3:
19584OPGEN_RETURN(false);
19585break;
19586default:
19587break;
19588}
19589break;
19590case Opcode::MultiplySub32:
19591switch (argIndex) {
19592case 0:
19593OPGEN_RETURN(false);
19594break;
19595case 1:
19596OPGEN_RETURN(false);
19597break;
19598case 2:
19599OPGEN_RETURN(false);
19600break;
19601case 3:
19602OPGEN_RETURN(false);
19603break;
19604default:
19605break;
19606}
19607break;
19608case Opcode::MultiplySub64:
19609switch (argIndex) {
19610case 0:
19611OPGEN_RETURN(false);
19612break;
19613case 1:
19614OPGEN_RETURN(false);
19615break;
19616case 2:
19617OPGEN_RETURN(false);
19618break;
19619case 3:
19620OPGEN_RETURN(false);
19621break;
19622default:
19623break;
19624}
19625break;
19626case Opcode::MultiplyNeg32:
19627switch (argIndex) {
19628case 0:
19629OPGEN_RETURN(false);
19630break;
19631case 1:
19632OPGEN_RETURN(false);
19633break;
19634case 2:
19635OPGEN_RETURN(false);
19636break;
19637default:
19638break;
19639}
19640break;
19641case Opcode::MultiplyNeg64:
19642switch (argIndex) {
19643case 0:
19644OPGEN_RETURN(false);
19645break;
19646case 1:
19647OPGEN_RETURN(false);
19648break;
19649case 2:
19650OPGEN_RETURN(false);
19651break;
19652default:
19653break;
19654}
19655break;
19656case Opcode::Div32:
19657switch (argIndex) {
19658case 0:
19659OPGEN_RETURN(false);
19660break;
19661case 1:
19662OPGEN_RETURN(false);
19663break;
19664case 2:
19665OPGEN_RETURN(false);
19666break;
19667default:
19668break;
19669}
19670break;
19671case Opcode::UDiv32:
19672switch (argIndex) {
19673case 0:
19674OPGEN_RETURN(false);
19675break;
19676case 1:
19677OPGEN_RETURN(false);
19678break;
19679case 2:
19680OPGEN_RETURN(false);
19681break;
19682default:
19683break;
19684}
19685break;
19686case Opcode::Div64:
19687switch (argIndex) {
19688case 0:
19689OPGEN_RETURN(false);
19690break;
19691case 1:
19692OPGEN_RETURN(false);
19693break;
19694case 2:
19695OPGEN_RETURN(false);
19696break;
19697default:
19698break;
19699}
19700break;
19701case Opcode::UDiv64:
19702switch (argIndex) {
19703case 0:
19704OPGEN_RETURN(false);
19705break;
19706case 1:
19707OPGEN_RETURN(false);
19708break;
19709case 2:
19710OPGEN_RETURN(false);
19711break;
19712default:
19713break;
19714}
19715break;
19716case Opcode::MulDouble:
19717switch (argIndex) {
19718case 0:
19719switch (args.size()) {
19720case 3:
19721switch (Arg::Addr) {
19722case Arg::Tmp:
19723break;
19724case Arg::Addr:
19725case Arg::Stack:
19726case Arg::CallArg:
19727switch (args[1].kind()) {
19728case Arg::Tmp:
19729switch (args[2].kind()) {
19730case Arg::Tmp:
19731#if CPU(X86) || CPU(X86_64)
19732OPGEN_RETURN(true);
19733#endif
19734break;
19735break;
19736default:
19737break;
19738}
19739break;
19740default:
19741break;
19742}
19743break;
19744case Arg::Index:
19745break;
19746default:
19747break;
19748}
19749break;
19750case 2:
19751switch (Arg::Addr) {
19752case Arg::Tmp:
19753break;
19754case Arg::Addr:
19755case Arg::Stack:
19756case Arg::CallArg:
19757switch (args[1].kind()) {
19758case Arg::Tmp:
19759#if CPU(X86) || CPU(X86_64)
19760OPGEN_RETURN(true);
19761#endif
19762break;
19763break;
19764default:
19765break;
19766}
19767break;
19768default:
19769break;
19770}
19771break;
19772default:
19773break;
19774}
19775break;
19776case 1:
19777switch (args.size()) {
19778case 3:
19779switch (args[0].kind()) {
19780case Arg::Tmp:
19781switch (Arg::Addr) {
19782case Arg::Tmp:
19783break;
19784case Arg::Addr:
19785case Arg::Stack:
19786case Arg::CallArg:
19787switch (args[2].kind()) {
19788case Arg::Tmp:
19789#if CPU(X86) || CPU(X86_64)
19790OPGEN_RETURN(true);
19791#endif
19792break;
19793break;
19794default:
19795break;
19796}
19797break;
19798default:
19799break;
19800}
19801break;
19802case Arg::Addr:
19803case Arg::Stack:
19804case Arg::CallArg:
19805break;
19806case Arg::Index:
19807break;
19808default:
19809break;
19810}
19811break;
19812default:
19813break;
19814}
19815break;
19816case 2:
19817OPGEN_RETURN(false);
19818break;
19819default:
19820break;
19821}
19822break;
19823case Opcode::MulFloat:
19824switch (argIndex) {
19825case 0:
19826switch (args.size()) {
19827case 3:
19828switch (Arg::Addr) {
19829case Arg::Tmp:
19830break;
19831case Arg::Addr:
19832case Arg::Stack:
19833case Arg::CallArg:
19834switch (args[1].kind()) {
19835case Arg::Tmp:
19836switch (args[2].kind()) {
19837case Arg::Tmp:
19838#if CPU(X86) || CPU(X86_64)
19839OPGEN_RETURN(true);
19840#endif
19841break;
19842break;
19843default:
19844break;
19845}
19846break;
19847default:
19848break;
19849}
19850break;
19851case Arg::Index:
19852break;
19853default:
19854break;
19855}
19856break;
19857case 2:
19858switch (Arg::Addr) {
19859case Arg::Tmp:
19860break;
19861case Arg::Addr:
19862case Arg::Stack:
19863case Arg::CallArg:
19864switch (args[1].kind()) {
19865case Arg::Tmp:
19866#if CPU(X86) || CPU(X86_64)
19867OPGEN_RETURN(true);
19868#endif
19869break;
19870break;
19871default:
19872break;
19873}
19874break;
19875default:
19876break;
19877}
19878break;
19879default:
19880break;
19881}
19882break;
19883case 1:
19884switch (args.size()) {
19885case 3:
19886switch (args[0].kind()) {
19887case Arg::Tmp:
19888switch (Arg::Addr) {
19889case Arg::Tmp:
19890break;
19891case Arg::Addr:
19892case Arg::Stack:
19893case Arg::CallArg:
19894switch (args[2].kind()) {
19895case Arg::Tmp:
19896#if CPU(X86) || CPU(X86_64)
19897OPGEN_RETURN(true);
19898#endif
19899break;
19900break;
19901default:
19902break;
19903}
19904break;
19905default:
19906break;
19907}
19908break;
19909case Arg::Addr:
19910case Arg::Stack:
19911case Arg::CallArg:
19912break;
19913case Arg::Index:
19914break;
19915default:
19916break;
19917}
19918break;
19919default:
19920break;
19921}
19922break;
19923case 2:
19924OPGEN_RETURN(false);
19925break;
19926default:
19927break;
19928}
19929break;
19930case Opcode::DivDouble:
19931switch (argIndex) {
19932case 0:
19933switch (args.size()) {
19934case 2:
19935switch (Arg::Addr) {
19936case Arg::Tmp:
19937break;
19938case Arg::Addr:
19939case Arg::Stack:
19940case Arg::CallArg:
19941switch (args[1].kind()) {
19942case Arg::Tmp:
19943#if CPU(X86) || CPU(X86_64)
19944OPGEN_RETURN(true);
19945#endif
19946break;
19947break;
19948default:
19949break;
19950}
19951break;
19952default:
19953break;
19954}
19955break;
19956default:
19957break;
19958}
19959break;
19960case 1:
19961OPGEN_RETURN(false);
19962break;
19963case 2:
19964OPGEN_RETURN(false);
19965break;
19966default:
19967break;
19968}
19969break;
19970case Opcode::DivFloat:
19971switch (argIndex) {
19972case 0:
19973switch (args.size()) {
19974case 2:
19975switch (Arg::Addr) {
19976case Arg::Tmp:
19977break;
19978case Arg::Addr:
19979case Arg::Stack:
19980case Arg::CallArg:
19981switch (args[1].kind()) {
19982case Arg::Tmp:
19983#if CPU(X86) || CPU(X86_64)
19984OPGEN_RETURN(true);
19985#endif
19986break;
19987break;
19988default:
19989break;
19990}
19991break;
19992default:
19993break;
19994}
19995break;
19996default:
19997break;
19998}
19999break;
20000case 1:
20001OPGEN_RETURN(false);
20002break;
20003case 2:
20004OPGEN_RETURN(false);
20005break;
20006default:
20007break;
20008}
20009break;
20010case Opcode::X86ConvertToDoubleWord32:
20011switch (argIndex) {
20012case 0:
20013OPGEN_RETURN(false);
20014break;
20015case 1:
20016OPGEN_RETURN(false);
20017break;
20018default:
20019break;
20020}
20021break;
20022case Opcode::X86ConvertToQuadWord64:
20023switch (argIndex) {
20024case 0:
20025OPGEN_RETURN(false);
20026break;
20027case 1:
20028OPGEN_RETURN(false);
20029break;
20030default:
20031break;
20032}
20033break;
20034case Opcode::X86Div32:
20035switch (argIndex) {
20036case 0:
20037OPGEN_RETURN(false);
20038break;
20039case 1:
20040OPGEN_RETURN(false);
20041break;
20042case 2:
20043OPGEN_RETURN(false);
20044break;
20045default:
20046break;
20047}
20048break;
20049case Opcode::X86UDiv32:
20050switch (argIndex) {
20051case 0:
20052OPGEN_RETURN(false);
20053break;
20054case 1:
20055OPGEN_RETURN(false);
20056break;
20057case 2:
20058OPGEN_RETURN(false);
20059break;
20060default:
20061break;
20062}
20063break;
20064case Opcode::X86Div64:
20065switch (argIndex) {
20066case 0:
20067OPGEN_RETURN(false);
20068break;
20069case 1:
20070OPGEN_RETURN(false);
20071break;
20072case 2:
20073OPGEN_RETURN(false);
20074break;
20075default:
20076break;
20077}
20078break;
20079case Opcode::X86UDiv64:
20080switch (argIndex) {
20081case 0:
20082OPGEN_RETURN(false);
20083break;
20084case 1:
20085OPGEN_RETURN(false);
20086break;
20087case 2:
20088OPGEN_RETURN(false);
20089break;
20090default:
20091break;
20092}
20093break;
20094case Opcode::Lea32:
20095switch (argIndex) {
20096case 0:
20097OPGEN_RETURN(false);
20098break;
20099case 1:
20100OPGEN_RETURN(false);
20101break;
20102default:
20103break;
20104}
20105break;
20106case Opcode::Lea64:
20107switch (argIndex) {
20108case 0:
20109OPGEN_RETURN(false);
20110break;
20111case 1:
20112OPGEN_RETURN(false);
20113break;
20114default:
20115break;
20116}
20117break;
20118case Opcode::And32:
20119switch (argIndex) {
20120case 0:
20121switch (args.size()) {
20122case 3:
20123switch (Arg::Addr) {
20124case Arg::Tmp:
20125break;
20126case Arg::BitImm:
20127break;
20128case Arg::Addr:
20129case Arg::Stack:
20130case Arg::CallArg:
20131switch (args[1].kind()) {
20132case Arg::Tmp:
20133switch (args[2].kind()) {
20134case Arg::Tmp:
20135#if CPU(X86) || CPU(X86_64)
20136OPGEN_RETURN(true);
20137#endif
20138break;
20139break;
20140default:
20141break;
20142}
20143break;
20144default:
20145break;
20146}
20147break;
20148default:
20149break;
20150}
20151break;
20152case 2:
20153switch (Arg::Addr) {
20154case Arg::Tmp:
20155break;
20156case Arg::Imm:
20157break;
20158case Arg::Addr:
20159case Arg::Stack:
20160case Arg::CallArg:
20161switch (args[1].kind()) {
20162case Arg::Tmp:
20163#if CPU(X86) || CPU(X86_64)
20164OPGEN_RETURN(true);
20165#endif
20166break;
20167break;
20168default:
20169break;
20170}
20171break;
20172case Arg::Index:
20173break;
20174default:
20175break;
20176}
20177break;
20178default:
20179break;
20180}
20181break;
20182case 1:
20183switch (args.size()) {
20184case 3:
20185switch (args[0].kind()) {
20186case Arg::Tmp:
20187switch (Arg::Addr) {
20188case Arg::Tmp:
20189break;
20190case Arg::Addr:
20191case Arg::Stack:
20192case Arg::CallArg:
20193switch (args[2].kind()) {
20194case Arg::Tmp:
20195#if CPU(X86) || CPU(X86_64)
20196OPGEN_RETURN(true);
20197#endif
20198break;
20199break;
20200default:
20201break;
20202}
20203break;
20204default:
20205break;
20206}
20207break;
20208case Arg::BitImm:
20209break;
20210case Arg::Addr:
20211case Arg::Stack:
20212case Arg::CallArg:
20213break;
20214default:
20215break;
20216}
20217break;
20218case 2:
20219switch (args[0].kind()) {
20220case Arg::Tmp:
20221switch (Arg::Addr) {
20222case Arg::Tmp:
20223break;
20224case Arg::Addr:
20225case Arg::Stack:
20226case Arg::CallArg:
20227#if CPU(X86) || CPU(X86_64)
20228OPGEN_RETURN(true);
20229#endif
20230break;
20231break;
20232case Arg::Index:
20233break;
20234default:
20235break;
20236}
20237break;
20238case Arg::Imm:
20239switch (Arg::Addr) {
20240case Arg::Tmp:
20241break;
20242case Arg::Addr:
20243case Arg::Stack:
20244case Arg::CallArg:
20245#if CPU(X86) || CPU(X86_64)
20246OPGEN_RETURN(true);
20247#endif
20248break;
20249break;
20250case Arg::Index:
20251break;
20252default:
20253break;
20254}
20255break;
20256case Arg::Addr:
20257case Arg::Stack:
20258case Arg::CallArg:
20259break;
20260case Arg::Index:
20261break;
20262default:
20263break;
20264}
20265break;
20266default:
20267break;
20268}
20269break;
20270case 2:
20271OPGEN_RETURN(false);
20272break;
20273default:
20274break;
20275}
20276break;
20277case Opcode::And64:
20278switch (argIndex) {
20279case 0:
20280switch (args.size()) {
20281case 2:
20282switch (Arg::Addr) {
20283case Arg::Tmp:
20284break;
20285case Arg::Imm:
20286break;
20287case Arg::Addr:
20288case Arg::Stack:
20289case Arg::CallArg:
20290switch (args[1].kind()) {
20291case Arg::Tmp:
20292#if CPU(X86_64)
20293OPGEN_RETURN(true);
20294#endif
20295break;
20296break;
20297default:
20298break;
20299}
20300break;
20301case Arg::Index:
20302break;
20303default:
20304break;
20305}
20306break;
20307default:
20308break;
20309}
20310break;
20311case 1:
20312switch (args.size()) {
20313case 2:
20314switch (args[0].kind()) {
20315case Arg::Tmp:
20316switch (Arg::Addr) {
20317case Arg::Tmp:
20318break;
20319case Arg::Addr:
20320case Arg::Stack:
20321case Arg::CallArg:
20322#if CPU(X86_64)
20323OPGEN_RETURN(true);
20324#endif
20325break;
20326break;
20327case Arg::Index:
20328break;
20329default:
20330break;
20331}
20332break;
20333case Arg::Imm:
20334switch (Arg::Addr) {
20335case Arg::Tmp:
20336break;
20337case Arg::Addr:
20338case Arg::Stack:
20339case Arg::CallArg:
20340#if CPU(X86_64)
20341OPGEN_RETURN(true);
20342#endif
20343break;
20344break;
20345case Arg::Index:
20346break;
20347default:
20348break;
20349}
20350break;
20351case Arg::Addr:
20352case Arg::Stack:
20353case Arg::CallArg:
20354break;
20355case Arg::Index:
20356break;
20357default:
20358break;
20359}
20360break;
20361default:
20362break;
20363}
20364break;
20365case 2:
20366OPGEN_RETURN(false);
20367break;
20368default:
20369break;
20370}
20371break;
20372case Opcode::AndDouble:
20373switch (argIndex) {
20374case 0:
20375OPGEN_RETURN(false);
20376break;
20377case 1:
20378OPGEN_RETURN(false);
20379break;
20380case 2:
20381OPGEN_RETURN(false);
20382break;
20383default:
20384break;
20385}
20386break;
20387case Opcode::AndFloat:
20388switch (argIndex) {
20389case 0:
20390OPGEN_RETURN(false);
20391break;
20392case 1:
20393OPGEN_RETURN(false);
20394break;
20395case 2:
20396OPGEN_RETURN(false);
20397break;
20398default:
20399break;
20400}
20401break;
20402case Opcode::OrDouble:
20403switch (argIndex) {
20404case 0:
20405OPGEN_RETURN(false);
20406break;
20407case 1:
20408OPGEN_RETURN(false);
20409break;
20410case 2:
20411OPGEN_RETURN(false);
20412break;
20413default:
20414break;
20415}
20416break;
20417case Opcode::OrFloat:
20418switch (argIndex) {
20419case 0:
20420OPGEN_RETURN(false);
20421break;
20422case 1:
20423OPGEN_RETURN(false);
20424break;
20425case 2:
20426OPGEN_RETURN(false);
20427break;
20428default:
20429break;
20430}
20431break;
20432case Opcode::XorDouble:
20433switch (argIndex) {
20434case 0:
20435OPGEN_RETURN(false);
20436break;
20437case 1:
20438OPGEN_RETURN(false);
20439break;
20440case 2:
20441OPGEN_RETURN(false);
20442break;
20443default:
20444break;
20445}
20446break;
20447case Opcode::XorFloat:
20448switch (argIndex) {
20449case 0:
20450OPGEN_RETURN(false);
20451break;
20452case 1:
20453OPGEN_RETURN(false);
20454break;
20455case 2:
20456OPGEN_RETURN(false);
20457break;
20458default:
20459break;
20460}
20461break;
20462case Opcode::Lshift32:
20463switch (argIndex) {
20464case 0:
20465OPGEN_RETURN(false);
20466break;
20467case 1:
20468OPGEN_RETURN(false);
20469break;
20470case 2:
20471OPGEN_RETURN(false);
20472break;
20473default:
20474break;
20475}
20476break;
20477case Opcode::Lshift64:
20478switch (argIndex) {
20479case 0:
20480OPGEN_RETURN(false);
20481break;
20482case 1:
20483OPGEN_RETURN(false);
20484break;
20485case 2:
20486OPGEN_RETURN(false);
20487break;
20488default:
20489break;
20490}
20491break;
20492case Opcode::Rshift32:
20493switch (argIndex) {
20494case 0:
20495OPGEN_RETURN(false);
20496break;
20497case 1:
20498OPGEN_RETURN(false);
20499break;
20500case 2:
20501OPGEN_RETURN(false);
20502break;
20503default:
20504break;
20505}
20506break;
20507case Opcode::Rshift64:
20508switch (argIndex) {
20509case 0:
20510OPGEN_RETURN(false);
20511break;
20512case 1:
20513OPGEN_RETURN(false);
20514break;
20515case 2:
20516OPGEN_RETURN(false);
20517break;
20518default:
20519break;
20520}
20521break;
20522case Opcode::Urshift32:
20523switch (argIndex) {
20524case 0:
20525OPGEN_RETURN(false);
20526break;
20527case 1:
20528OPGEN_RETURN(false);
20529break;
20530case 2:
20531OPGEN_RETURN(false);
20532break;
20533default:
20534break;
20535}
20536break;
20537case Opcode::Urshift64:
20538switch (argIndex) {
20539case 0:
20540OPGEN_RETURN(false);
20541break;
20542case 1:
20543OPGEN_RETURN(false);
20544break;
20545case 2:
20546OPGEN_RETURN(false);
20547break;
20548default:
20549break;
20550}
20551break;
20552case Opcode::RotateRight32:
20553switch (argIndex) {
20554case 0:
20555OPGEN_RETURN(false);
20556break;
20557case 1:
20558OPGEN_RETURN(false);
20559break;
20560case 2:
20561OPGEN_RETURN(false);
20562break;
20563default:
20564break;
20565}
20566break;
20567case Opcode::RotateRight64:
20568switch (argIndex) {
20569case 0:
20570OPGEN_RETURN(false);
20571break;
20572case 1:
20573OPGEN_RETURN(false);
20574break;
20575case 2:
20576OPGEN_RETURN(false);
20577break;
20578default:
20579break;
20580}
20581break;
20582case Opcode::RotateLeft32:
20583switch (argIndex) {
20584case 0:
20585OPGEN_RETURN(false);
20586break;
20587case 1:
20588OPGEN_RETURN(false);
20589break;
20590default:
20591break;
20592}
20593break;
20594case Opcode::RotateLeft64:
20595switch (argIndex) {
20596case 0:
20597OPGEN_RETURN(false);
20598break;
20599case 1:
20600OPGEN_RETURN(false);
20601break;
20602default:
20603break;
20604}
20605break;
20606case Opcode::Or32:
20607switch (argIndex) {
20608case 0:
20609switch (args.size()) {
20610case 3:
20611switch (Arg::Addr) {
20612case Arg::Tmp:
20613break;
20614case Arg::BitImm:
20615break;
20616case Arg::Addr:
20617case Arg::Stack:
20618case Arg::CallArg:
20619switch (args[1].kind()) {
20620case Arg::Tmp:
20621switch (args[2].kind()) {
20622case Arg::Tmp:
20623#if CPU(X86) || CPU(X86_64)
20624OPGEN_RETURN(true);
20625#endif
20626break;
20627break;
20628default:
20629break;
20630}
20631break;
20632default:
20633break;
20634}
20635break;
20636default:
20637break;
20638}
20639break;
20640case 2:
20641switch (Arg::Addr) {
20642case Arg::Tmp:
20643break;
20644case Arg::Imm:
20645break;
20646case Arg::Addr:
20647case Arg::Stack:
20648case Arg::CallArg:
20649switch (args[1].kind()) {
20650case Arg::Tmp:
20651#if CPU(X86) || CPU(X86_64)
20652OPGEN_RETURN(true);
20653#endif
20654break;
20655break;
20656default:
20657break;
20658}
20659break;
20660case Arg::Index:
20661break;
20662default:
20663break;
20664}
20665break;
20666default:
20667break;
20668}
20669break;
20670case 1:
20671switch (args.size()) {
20672case 3:
20673switch (args[0].kind()) {
20674case Arg::Tmp:
20675switch (Arg::Addr) {
20676case Arg::Tmp:
20677break;
20678case Arg::Addr:
20679case Arg::Stack:
20680case Arg::CallArg:
20681switch (args[2].kind()) {
20682case Arg::Tmp:
20683#if CPU(X86) || CPU(X86_64)
20684OPGEN_RETURN(true);
20685#endif
20686break;
20687break;
20688default:
20689break;
20690}
20691break;
20692default:
20693break;
20694}
20695break;
20696case Arg::BitImm:
20697break;
20698case Arg::Addr:
20699case Arg::Stack:
20700case Arg::CallArg:
20701break;
20702default:
20703break;
20704}
20705break;
20706case 2:
20707switch (args[0].kind()) {
20708case Arg::Tmp:
20709switch (Arg::Addr) {
20710case Arg::Tmp:
20711break;
20712case Arg::Addr:
20713case Arg::Stack:
20714case Arg::CallArg:
20715#if CPU(X86) || CPU(X86_64)
20716OPGEN_RETURN(true);
20717#endif
20718break;
20719break;
20720case Arg::Index:
20721break;
20722default:
20723break;
20724}
20725break;
20726case Arg::Imm:
20727switch (Arg::Addr) {
20728case Arg::Tmp:
20729break;
20730case Arg::Addr:
20731case Arg::Stack:
20732case Arg::CallArg:
20733#if CPU(X86) || CPU(X86_64)
20734OPGEN_RETURN(true);
20735#endif
20736break;
20737break;
20738case Arg::Index:
20739break;
20740default:
20741break;
20742}
20743break;
20744case Arg::Addr:
20745case Arg::Stack:
20746case Arg::CallArg:
20747break;
20748case Arg::Index:
20749break;
20750default:
20751break;
20752}
20753break;
20754default:
20755break;
20756}
20757break;
20758case 2:
20759OPGEN_RETURN(false);
20760break;
20761default:
20762break;
20763}
20764break;
20765case Opcode::Or64:
20766switch (argIndex) {
20767case 0:
20768switch (args.size()) {
20769case 2:
20770switch (Arg::Addr) {
20771case Arg::Tmp:
20772break;
20773case Arg::Imm:
20774break;
20775case Arg::Addr:
20776case Arg::Stack:
20777case Arg::CallArg:
20778switch (args[1].kind()) {
20779case Arg::Tmp:
20780#if CPU(X86_64)
20781OPGEN_RETURN(true);
20782#endif
20783break;
20784break;
20785default:
20786break;
20787}
20788break;
20789case Arg::Index:
20790break;
20791default:
20792break;
20793}
20794break;
20795default:
20796break;
20797}
20798break;
20799case 1:
20800switch (args.size()) {
20801case 2:
20802switch (args[0].kind()) {
20803case Arg::Tmp:
20804switch (Arg::Addr) {
20805case Arg::Tmp:
20806break;
20807case Arg::Addr:
20808case Arg::Stack:
20809case Arg::CallArg:
20810#if CPU(X86_64)
20811OPGEN_RETURN(true);
20812#endif
20813break;
20814break;
20815case Arg::Index:
20816break;
20817default:
20818break;
20819}
20820break;
20821case Arg::Imm:
20822switch (Arg::Addr) {
20823case Arg::Tmp:
20824break;
20825case Arg::Addr:
20826case Arg::Stack:
20827case Arg::CallArg:
20828#if CPU(X86_64)
20829OPGEN_RETURN(true);
20830#endif
20831break;
20832break;
20833case Arg::Index:
20834break;
20835default:
20836break;
20837}
20838break;
20839case Arg::Addr:
20840case Arg::Stack:
20841case Arg::CallArg:
20842break;
20843case Arg::Index:
20844break;
20845default:
20846break;
20847}
20848break;
20849default:
20850break;
20851}
20852break;
20853case 2:
20854OPGEN_RETURN(false);
20855break;
20856default:
20857break;
20858}
20859break;
20860case Opcode::Xor32:
20861switch (argIndex) {
20862case 0:
20863switch (args.size()) {
20864case 3:
20865switch (Arg::Addr) {
20866case Arg::Tmp:
20867break;
20868case Arg::BitImm:
20869break;
20870case Arg::Addr:
20871case Arg::Stack:
20872case Arg::CallArg:
20873switch (args[1].kind()) {
20874case Arg::Tmp:
20875switch (args[2].kind()) {
20876case Arg::Tmp:
20877#if CPU(X86) || CPU(X86_64)
20878OPGEN_RETURN(true);
20879#endif
20880break;
20881break;
20882default:
20883break;
20884}
20885break;
20886default:
20887break;
20888}
20889break;
20890default:
20891break;
20892}
20893break;
20894case 2:
20895switch (Arg::Addr) {
20896case Arg::Tmp:
20897break;
20898case Arg::Imm:
20899break;
20900case Arg::Addr:
20901case Arg::Stack:
20902case Arg::CallArg:
20903switch (args[1].kind()) {
20904case Arg::Tmp:
20905#if CPU(X86) || CPU(X86_64)
20906OPGEN_RETURN(true);
20907#endif
20908break;
20909break;
20910default:
20911break;
20912}
20913break;
20914case Arg::Index:
20915break;
20916default:
20917break;
20918}
20919break;
20920default:
20921break;
20922}
20923break;
20924case 1:
20925switch (args.size()) {
20926case 3:
20927switch (args[0].kind()) {
20928case Arg::Tmp:
20929switch (Arg::Addr) {
20930case Arg::Tmp:
20931break;
20932case Arg::Addr:
20933case Arg::Stack:
20934case Arg::CallArg:
20935switch (args[2].kind()) {
20936case Arg::Tmp:
20937#if CPU(X86) || CPU(X86_64)
20938OPGEN_RETURN(true);
20939#endif
20940break;
20941break;
20942default:
20943break;
20944}
20945break;
20946default:
20947break;
20948}
20949break;
20950case Arg::BitImm:
20951break;
20952case Arg::Addr:
20953case Arg::Stack:
20954case Arg::CallArg:
20955break;
20956default:
20957break;
20958}
20959break;
20960case 2:
20961switch (args[0].kind()) {
20962case Arg::Tmp:
20963switch (Arg::Addr) {
20964case Arg::Tmp:
20965break;
20966case Arg::Addr:
20967case Arg::Stack:
20968case Arg::CallArg:
20969#if CPU(X86) || CPU(X86_64)
20970OPGEN_RETURN(true);
20971#endif
20972break;
20973break;
20974case Arg::Index:
20975break;
20976default:
20977break;
20978}
20979break;
20980case Arg::Imm:
20981switch (Arg::Addr) {
20982case Arg::Tmp:
20983break;
20984case Arg::Addr:
20985case Arg::Stack:
20986case Arg::CallArg:
20987#if CPU(X86) || CPU(X86_64)
20988OPGEN_RETURN(true);
20989#endif
20990break;
20991break;
20992case Arg::Index:
20993break;
20994default:
20995break;
20996}
20997break;
20998case Arg::Addr:
20999case Arg::Stack:
21000case Arg::CallArg:
21001break;
21002case Arg::Index:
21003break;
21004default:
21005break;
21006}
21007break;
21008default:
21009break;
21010}
21011break;
21012case 2:
21013OPGEN_RETURN(false);
21014break;
21015default:
21016break;
21017}
21018break;
21019case Opcode::Xor64:
21020switch (argIndex) {
21021case 0:
21022switch (args.size()) {
21023case 2:
21024switch (Arg::Addr) {
21025case Arg::Tmp:
21026break;
21027case Arg::Addr:
21028case Arg::Stack:
21029case Arg::CallArg:
21030switch (args[1].kind()) {
21031case Arg::Tmp:
21032#if CPU(X86_64)
21033OPGEN_RETURN(true);
21034#endif
21035break;
21036break;
21037default:
21038break;
21039}
21040break;
21041case Arg::Index:
21042break;
21043case Arg::Imm:
21044break;
21045default:
21046break;
21047}
21048break;
21049default:
21050break;
21051}
21052break;
21053case 1:
21054switch (args.size()) {
21055case 2:
21056switch (args[0].kind()) {
21057case Arg::Tmp:
21058switch (Arg::Addr) {
21059case Arg::Tmp:
21060break;
21061case Arg::Addr:
21062case Arg::Stack:
21063case Arg::CallArg:
21064#if CPU(X86_64)
21065OPGEN_RETURN(true);
21066#endif
21067break;
21068break;
21069case Arg::Index:
21070break;
21071default:
21072break;
21073}
21074break;
21075case Arg::Addr:
21076case Arg::Stack:
21077case Arg::CallArg:
21078break;
21079case Arg::Index:
21080break;
21081case Arg::Imm:
21082switch (Arg::Addr) {
21083case Arg::Addr:
21084case Arg::Stack:
21085case Arg::CallArg:
21086#if CPU(X86_64)
21087OPGEN_RETURN(true);
21088#endif
21089break;
21090break;
21091case Arg::Index:
21092break;
21093case Arg::Tmp:
21094break;
21095default:
21096break;
21097}
21098break;
21099default:
21100break;
21101}
21102break;
21103default:
21104break;
21105}
21106break;
21107case 2:
21108OPGEN_RETURN(false);
21109break;
21110default:
21111break;
21112}
21113break;
21114case Opcode::Not32:
21115switch (argIndex) {
21116case 0:
21117switch (args.size()) {
21118case 1:
21119switch (Arg::Addr) {
21120case Arg::Tmp:
21121break;
21122case Arg::Addr:
21123case Arg::Stack:
21124case Arg::CallArg:
21125#if CPU(X86) || CPU(X86_64)
21126OPGEN_RETURN(true);
21127#endif
21128break;
21129break;
21130case Arg::Index:
21131break;
21132default:
21133break;
21134}
21135break;
21136default:
21137break;
21138}
21139break;
21140case 1:
21141OPGEN_RETURN(false);
21142break;
21143default:
21144break;
21145}
21146break;
21147case Opcode::Not64:
21148switch (argIndex) {
21149case 0:
21150switch (args.size()) {
21151case 1:
21152switch (Arg::Addr) {
21153case Arg::Tmp:
21154break;
21155case Arg::Addr:
21156case Arg::Stack:
21157case Arg::CallArg:
21158#if CPU(X86_64)
21159OPGEN_RETURN(true);
21160#endif
21161break;
21162break;
21163case Arg::Index:
21164break;
21165default:
21166break;
21167}
21168break;
21169default:
21170break;
21171}
21172break;
21173case 1:
21174OPGEN_RETURN(false);
21175break;
21176default:
21177break;
21178}
21179break;
21180case Opcode::AbsDouble:
21181switch (argIndex) {
21182case 0:
21183OPGEN_RETURN(false);
21184break;
21185case 1:
21186OPGEN_RETURN(false);
21187break;
21188default:
21189break;
21190}
21191break;
21192case Opcode::AbsFloat:
21193switch (argIndex) {
21194case 0:
21195OPGEN_RETURN(false);
21196break;
21197case 1:
21198OPGEN_RETURN(false);
21199break;
21200default:
21201break;
21202}
21203break;
21204case Opcode::CeilDouble:
21205switch (argIndex) {
21206case 0:
21207switch (Arg::Addr) {
21208case Arg::Tmp:
21209break;
21210case Arg::Addr:
21211case Arg::Stack:
21212case Arg::CallArg:
21213switch (args[1].kind()) {
21214case Arg::Tmp:
21215#if CPU(X86) || CPU(X86_64)
21216OPGEN_RETURN(true);
21217#endif
21218break;
21219break;
21220default:
21221break;
21222}
21223break;
21224default:
21225break;
21226}
21227break;
21228case 1:
21229OPGEN_RETURN(false);
21230break;
21231default:
21232break;
21233}
21234break;
21235case Opcode::CeilFloat:
21236switch (argIndex) {
21237case 0:
21238switch (Arg::Addr) {
21239case Arg::Tmp:
21240break;
21241case Arg::Addr:
21242case Arg::Stack:
21243case Arg::CallArg:
21244switch (args[1].kind()) {
21245case Arg::Tmp:
21246#if CPU(X86) || CPU(X86_64)
21247OPGEN_RETURN(true);
21248#endif
21249break;
21250break;
21251default:
21252break;
21253}
21254break;
21255default:
21256break;
21257}
21258break;
21259case 1:
21260OPGEN_RETURN(false);
21261break;
21262default:
21263break;
21264}
21265break;
21266case Opcode::FloorDouble:
21267switch (argIndex) {
21268case 0:
21269switch (Arg::Addr) {
21270case Arg::Tmp:
21271break;
21272case Arg::Addr:
21273case Arg::Stack:
21274case Arg::CallArg:
21275switch (args[1].kind()) {
21276case Arg::Tmp:
21277#if CPU(X86) || CPU(X86_64)
21278OPGEN_RETURN(true);
21279#endif
21280break;
21281break;
21282default:
21283break;
21284}
21285break;
21286default:
21287break;
21288}
21289break;
21290case 1:
21291OPGEN_RETURN(false);
21292break;
21293default:
21294break;
21295}
21296break;
21297case Opcode::FloorFloat:
21298switch (argIndex) {
21299case 0:
21300switch (Arg::Addr) {
21301case Arg::Tmp:
21302break;
21303case Arg::Addr:
21304case Arg::Stack:
21305case Arg::CallArg:
21306switch (args[1].kind()) {
21307case Arg::Tmp:
21308#if CPU(X86) || CPU(X86_64)
21309OPGEN_RETURN(true);
21310#endif
21311break;
21312break;
21313default:
21314break;
21315}
21316break;
21317default:
21318break;
21319}
21320break;
21321case 1:
21322OPGEN_RETURN(false);
21323break;
21324default:
21325break;
21326}
21327break;
21328case Opcode::SqrtDouble:
21329switch (argIndex) {
21330case 0:
21331switch (Arg::Addr) {
21332case Arg::Tmp:
21333break;
21334case Arg::Addr:
21335case Arg::Stack:
21336case Arg::CallArg:
21337switch (args[1].kind()) {
21338case Arg::Tmp:
21339#if CPU(X86) || CPU(X86_64)
21340OPGEN_RETURN(true);
21341#endif
21342break;
21343break;
21344default:
21345break;
21346}
21347break;
21348default:
21349break;
21350}
21351break;
21352case 1:
21353OPGEN_RETURN(false);
21354break;
21355default:
21356break;
21357}
21358break;
21359case Opcode::SqrtFloat:
21360switch (argIndex) {
21361case 0:
21362switch (Arg::Addr) {
21363case Arg::Tmp:
21364break;
21365case Arg::Addr:
21366case Arg::Stack:
21367case Arg::CallArg:
21368switch (args[1].kind()) {
21369case Arg::Tmp:
21370#if CPU(X86) || CPU(X86_64)
21371OPGEN_RETURN(true);
21372#endif
21373break;
21374break;
21375default:
21376break;
21377}
21378break;
21379default:
21380break;
21381}
21382break;
21383case 1:
21384OPGEN_RETURN(false);
21385break;
21386default:
21387break;
21388}
21389break;
21390case Opcode::ConvertInt32ToDouble:
21391switch (argIndex) {
21392case 0:
21393switch (Arg::Addr) {
21394case Arg::Tmp:
21395break;
21396case Arg::Addr:
21397case Arg::Stack:
21398case Arg::CallArg:
21399switch (args[1].kind()) {
21400case Arg::Tmp:
21401#if CPU(X86) || CPU(X86_64)
21402OPGEN_RETURN(true);
21403#endif
21404break;
21405break;
21406default:
21407break;
21408}
21409break;
21410default:
21411break;
21412}
21413break;
21414case 1:
21415OPGEN_RETURN(false);
21416break;
21417default:
21418break;
21419}
21420break;
21421case Opcode::ConvertInt64ToDouble:
21422switch (argIndex) {
21423case 0:
21424switch (Arg::Addr) {
21425case Arg::Tmp:
21426break;
21427case Arg::Addr:
21428case Arg::Stack:
21429case Arg::CallArg:
21430switch (args[1].kind()) {
21431case Arg::Tmp:
21432#if CPU(X86_64)
21433OPGEN_RETURN(true);
21434#endif
21435break;
21436break;
21437default:
21438break;
21439}
21440break;
21441default:
21442break;
21443}
21444break;
21445case 1:
21446OPGEN_RETURN(false);
21447break;
21448default:
21449break;
21450}
21451break;
21452case Opcode::ConvertInt32ToFloat:
21453switch (argIndex) {
21454case 0:
21455switch (Arg::Addr) {
21456case Arg::Tmp:
21457break;
21458case Arg::Addr:
21459case Arg::Stack:
21460case Arg::CallArg:
21461switch (args[1].kind()) {
21462case Arg::Tmp:
21463#if CPU(X86) || CPU(X86_64)
21464OPGEN_RETURN(true);
21465#endif
21466break;
21467break;
21468default:
21469break;
21470}
21471break;
21472default:
21473break;
21474}
21475break;
21476case 1:
21477OPGEN_RETURN(false);
21478break;
21479default:
21480break;
21481}
21482break;
21483case Opcode::ConvertInt64ToFloat:
21484switch (argIndex) {
21485case 0:
21486switch (Arg::Addr) {
21487case Arg::Tmp:
21488break;
21489case Arg::Addr:
21490case Arg::Stack:
21491case Arg::CallArg:
21492switch (args[1].kind()) {
21493case Arg::Tmp:
21494#if CPU(X86_64)
21495OPGEN_RETURN(true);
21496#endif
21497break;
21498break;
21499default:
21500break;
21501}
21502break;
21503default:
21504break;
21505}
21506break;
21507case 1:
21508OPGEN_RETURN(false);
21509break;
21510default:
21511break;
21512}
21513break;
21514case Opcode::CountLeadingZeros32:
21515switch (argIndex) {
21516case 0:
21517switch (Arg::Addr) {
21518case Arg::Tmp:
21519break;
21520case Arg::Addr:
21521case Arg::Stack:
21522case Arg::CallArg:
21523switch (args[1].kind()) {
21524case Arg::Tmp:
21525#if CPU(X86) || CPU(X86_64)
21526OPGEN_RETURN(true);
21527#endif
21528break;
21529break;
21530default:
21531break;
21532}
21533break;
21534default:
21535break;
21536}
21537break;
21538case 1:
21539OPGEN_RETURN(false);
21540break;
21541default:
21542break;
21543}
21544break;
21545case Opcode::CountLeadingZeros64:
21546switch (argIndex) {
21547case 0:
21548switch (Arg::Addr) {
21549case Arg::Tmp:
21550break;
21551case Arg::Addr:
21552case Arg::Stack:
21553case Arg::CallArg:
21554switch (args[1].kind()) {
21555case Arg::Tmp:
21556#if CPU(X86_64)
21557OPGEN_RETURN(true);
21558#endif
21559break;
21560break;
21561default:
21562break;
21563}
21564break;
21565default:
21566break;
21567}
21568break;
21569case 1:
21570OPGEN_RETURN(false);
21571break;
21572default:
21573break;
21574}
21575break;
21576case Opcode::ConvertDoubleToFloat:
21577switch (argIndex) {
21578case 0:
21579switch (Arg::Addr) {
21580case Arg::Tmp:
21581break;
21582case Arg::Addr:
21583case Arg::Stack:
21584case Arg::CallArg:
21585switch (args[1].kind()) {
21586case Arg::Tmp:
21587#if CPU(X86) || CPU(X86_64)
21588OPGEN_RETURN(true);
21589#endif
21590break;
21591break;
21592default:
21593break;
21594}
21595break;
21596default:
21597break;
21598}
21599break;
21600case 1:
21601OPGEN_RETURN(false);
21602break;
21603default:
21604break;
21605}
21606break;
21607case Opcode::ConvertFloatToDouble:
21608switch (argIndex) {
21609case 0:
21610switch (Arg::Addr) {
21611case Arg::Tmp:
21612break;
21613case Arg::Addr:
21614case Arg::Stack:
21615case Arg::CallArg:
21616switch (args[1].kind()) {
21617case Arg::Tmp:
21618#if CPU(X86) || CPU(X86_64)
21619OPGEN_RETURN(true);
21620#endif
21621break;
21622break;
21623default:
21624break;
21625}
21626break;
21627default:
21628break;
21629}
21630break;
21631case 1:
21632OPGEN_RETURN(false);
21633break;
21634default:
21635break;
21636}
21637break;
21638case Opcode::Move:
21639switch (argIndex) {
21640case 0:
21641switch (args.size()) {
21642case 2:
21643switch (Arg::Addr) {
21644case Arg::Tmp:
21645break;
21646case Arg::Imm:
21647break;
21648#if USE(JSVALUE64)
21649case Arg::BigImm:
21650break;
21651#endif // USE(JSVALUE64)
21652case Arg::Addr:
21653case Arg::Stack:
21654case Arg::CallArg:
21655switch (args[1].kind()) {
21656case Arg::Tmp:
21657OPGEN_RETURN(true);
21658break;
21659break;
21660default:
21661break;
21662}
21663break;
21664case Arg::Index:
21665break;
21666default:
21667break;
21668}
21669break;
21670case 3:
21671OPGEN_RETURN(true);
21672break;
21673default:
21674break;
21675}
21676break;
21677case 1:
21678switch (args.size()) {
21679case 2:
21680switch (args[0].kind()) {
21681case Arg::Tmp:
21682switch (Arg::Addr) {
21683case Arg::Tmp:
21684break;
21685case Arg::Addr:
21686case Arg::Stack:
21687case Arg::CallArg:
21688OPGEN_RETURN(true);
21689break;
21690break;
21691case Arg::Index:
21692break;
21693default:
21694break;
21695}
21696break;
21697case Arg::Imm:
21698switch (Arg::Addr) {
21699case Arg::Tmp:
21700break;
21701case Arg::Addr:
21702case Arg::Stack:
21703case Arg::CallArg:
21704#if CPU(X86) || CPU(X86_64)
21705OPGEN_RETURN(true);
21706#endif
21707break;
21708break;
21709default:
21710break;
21711}
21712break;
21713#if USE(JSVALUE64)
21714case Arg::BigImm:
21715break;
21716#endif // USE(JSVALUE64)
21717case Arg::Addr:
21718case Arg::Stack:
21719case Arg::CallArg:
21720break;
21721case Arg::Index:
21722break;
21723default:
21724break;
21725}
21726break;
21727case 3:
21728OPGEN_RETURN(true);
21729break;
21730default:
21731break;
21732}
21733break;
21734case 2:
21735OPGEN_RETURN(false);
21736break;
21737default:
21738break;
21739}
21740break;
21741case Opcode::Swap32:
21742switch (argIndex) {
21743case 0:
21744OPGEN_RETURN(false);
21745break;
21746case 1:
21747switch (args[0].kind()) {
21748case Arg::Tmp:
21749switch (Arg::Addr) {
21750case Arg::Tmp:
21751break;
21752case Arg::Addr:
21753case Arg::Stack:
21754case Arg::CallArg:
21755#if CPU(X86) || CPU(X86_64)
21756OPGEN_RETURN(true);
21757#endif
21758break;
21759break;
21760default:
21761break;
21762}
21763break;
21764default:
21765break;
21766}
21767break;
21768default:
21769break;
21770}
21771break;
21772case Opcode::Swap64:
21773switch (argIndex) {
21774case 0:
21775OPGEN_RETURN(false);
21776break;
21777case 1:
21778switch (args[0].kind()) {
21779case Arg::Tmp:
21780switch (Arg::Addr) {
21781case Arg::Tmp:
21782break;
21783case Arg::Addr:
21784case Arg::Stack:
21785case Arg::CallArg:
21786#if CPU(X86_64)
21787OPGEN_RETURN(true);
21788#endif
21789break;
21790break;
21791default:
21792break;
21793}
21794break;
21795default:
21796break;
21797}
21798break;
21799default:
21800break;
21801}
21802break;
21803case Opcode::Move32:
21804switch (argIndex) {
21805case 0:
21806switch (args.size()) {
21807case 2:
21808switch (Arg::Addr) {
21809case Arg::Tmp:
21810break;
21811case Arg::Addr:
21812case Arg::Stack:
21813case Arg::CallArg:
21814switch (args[1].kind()) {
21815case Arg::Tmp:
21816OPGEN_RETURN(true);
21817break;
21818break;
21819default:
21820break;
21821}
21822break;
21823case Arg::Index:
21824break;
21825case Arg::Imm:
21826break;
21827default:
21828break;
21829}
21830break;
21831case 3:
21832OPGEN_RETURN(true);
21833break;
21834default:
21835break;
21836}
21837break;
21838case 1:
21839switch (args.size()) {
21840case 2:
21841switch (args[0].kind()) {
21842case Arg::Tmp:
21843switch (Arg::Addr) {
21844case Arg::Tmp:
21845break;
21846case Arg::Addr:
21847case Arg::Stack:
21848case Arg::CallArg:
21849OPGEN_RETURN(true);
21850break;
21851break;
21852case Arg::Index:
21853break;
21854default:
21855break;
21856}
21857break;
21858case Arg::Addr:
21859case Arg::Stack:
21860case Arg::CallArg:
21861break;
21862case Arg::Index:
21863break;
21864case Arg::Imm:
21865switch (Arg::Addr) {
21866case Arg::Tmp:
21867break;
21868case Arg::Addr:
21869case Arg::Stack:
21870case Arg::CallArg:
21871#if CPU(X86) || CPU(X86_64)
21872OPGEN_RETURN(true);
21873#endif
21874break;
21875break;
21876case Arg::Index:
21877break;
21878default:
21879break;
21880}
21881break;
21882default:
21883break;
21884}
21885break;
21886case 3:
21887OPGEN_RETURN(true);
21888break;
21889default:
21890break;
21891}
21892break;
21893case 2:
21894OPGEN_RETURN(false);
21895break;
21896default:
21897break;
21898}
21899break;
21900case Opcode::StoreZero32:
21901switch (argIndex) {
21902case 0:
21903switch (Arg::Addr) {
21904case Arg::Addr:
21905case Arg::Stack:
21906case Arg::CallArg:
21907OPGEN_RETURN(true);
21908break;
21909break;
21910case Arg::Index:
21911break;
21912default:
21913break;
21914}
21915break;
21916default:
21917break;
21918}
21919break;
21920case Opcode::StoreZero64:
21921switch (argIndex) {
21922case 0:
21923switch (Arg::Addr) {
21924case Arg::Addr:
21925case Arg::Stack:
21926case Arg::CallArg:
21927#if CPU(X86_64) || CPU(ARM64)
21928OPGEN_RETURN(true);
21929#endif
21930break;
21931break;
21932case Arg::Index:
21933break;
21934default:
21935break;
21936}
21937break;
21938default:
21939break;
21940}
21941break;
21942case Opcode::SignExtend32ToPtr:
21943switch (argIndex) {
21944case 0:
21945OPGEN_RETURN(false);
21946break;
21947case 1:
21948OPGEN_RETURN(false);
21949break;
21950default:
21951break;
21952}
21953break;
21954case Opcode::ZeroExtend8To32:
21955switch (argIndex) {
21956case 0:
21957switch (Arg::Addr) {
21958case Arg::Tmp:
21959break;
21960case Arg::Addr:
21961case Arg::Stack:
21962case Arg::CallArg:
21963switch (args[1].kind()) {
21964case Arg::Tmp:
21965#if CPU(X86) || CPU(X86_64)
21966OPGEN_RETURN(true);
21967#endif
21968break;
21969break;
21970default:
21971break;
21972}
21973break;
21974case Arg::Index:
21975break;
21976default:
21977break;
21978}
21979break;
21980case 1:
21981OPGEN_RETURN(false);
21982break;
21983default:
21984break;
21985}
21986break;
21987case Opcode::SignExtend8To32:
21988switch (argIndex) {
21989case 0:
21990switch (Arg::Addr) {
21991case Arg::Tmp:
21992break;
21993case Arg::Addr:
21994case Arg::Stack:
21995case Arg::CallArg:
21996switch (args[1].kind()) {
21997case Arg::Tmp:
21998#if CPU(X86) || CPU(X86_64)
21999OPGEN_RETURN(true);
22000#endif
22001break;
22002break;
22003default:
22004break;
22005}
22006break;
22007case Arg::Index:
22008break;
22009default:
22010break;
22011}
22012break;
22013case 1:
22014OPGEN_RETURN(false);
22015break;
22016default:
22017break;
22018}
22019break;
22020case Opcode::ZeroExtend16To32:
22021switch (argIndex) {
22022case 0:
22023switch (Arg::Addr) {
22024case Arg::Tmp:
22025break;
22026case Arg::Addr:
22027case Arg::Stack:
22028case Arg::CallArg:
22029switch (args[1].kind()) {
22030case Arg::Tmp:
22031#if CPU(X86) || CPU(X86_64)
22032OPGEN_RETURN(true);
22033#endif
22034break;
22035break;
22036default:
22037break;
22038}
22039break;
22040case Arg::Index:
22041break;
22042default:
22043break;
22044}
22045break;
22046case 1:
22047OPGEN_RETURN(false);
22048break;
22049default:
22050break;
22051}
22052break;
22053case Opcode::SignExtend16To32:
22054switch (argIndex) {
22055case 0:
22056switch (Arg::Addr) {
22057case Arg::Tmp:
22058break;
22059case Arg::Addr:
22060case Arg::Stack:
22061case Arg::CallArg:
22062switch (args[1].kind()) {
22063case Arg::Tmp:
22064#if CPU(X86) || CPU(X86_64)
22065OPGEN_RETURN(true);
22066#endif
22067break;
22068break;
22069default:
22070break;
22071}
22072break;
22073case Arg::Index:
22074break;
22075default:
22076break;
22077}
22078break;
22079case 1:
22080OPGEN_RETURN(false);
22081break;
22082default:
22083break;
22084}
22085break;
22086case Opcode::MoveFloat:
22087switch (argIndex) {
22088case 0:
22089switch (args.size()) {
22090case 2:
22091switch (Arg::Addr) {
22092case Arg::Tmp:
22093break;
22094case Arg::Addr:
22095case Arg::Stack:
22096case Arg::CallArg:
22097switch (args[1].kind()) {
22098case Arg::Tmp:
22099OPGEN_RETURN(true);
22100break;
22101break;
22102default:
22103break;
22104}
22105break;
22106case Arg::Index:
22107break;
22108default:
22109break;
22110}
22111break;
22112case 3:
22113OPGEN_RETURN(true);
22114break;
22115default:
22116break;
22117}
22118break;
22119case 1:
22120switch (args.size()) {
22121case 2:
22122switch (args[0].kind()) {
22123case Arg::Tmp:
22124switch (Arg::Addr) {
22125case Arg::Tmp:
22126break;
22127case Arg::Addr:
22128case Arg::Stack:
22129case Arg::CallArg:
22130OPGEN_RETURN(true);
22131break;
22132break;
22133case Arg::Index:
22134break;
22135default:
22136break;
22137}
22138break;
22139case Arg::Addr:
22140case Arg::Stack:
22141case Arg::CallArg:
22142break;
22143case Arg::Index:
22144break;
22145default:
22146break;
22147}
22148break;
22149case 3:
22150OPGEN_RETURN(true);
22151break;
22152default:
22153break;
22154}
22155break;
22156case 2:
22157OPGEN_RETURN(false);
22158break;
22159default:
22160break;
22161}
22162break;
22163case Opcode::MoveDouble:
22164switch (argIndex) {
22165case 0:
22166switch (args.size()) {
22167case 2:
22168switch (Arg::Addr) {
22169case Arg::Tmp:
22170break;
22171case Arg::Addr:
22172case Arg::Stack:
22173case Arg::CallArg:
22174switch (args[1].kind()) {
22175case Arg::Tmp:
22176OPGEN_RETURN(true);
22177break;
22178break;
22179default:
22180break;
22181}
22182break;
22183case Arg::Index:
22184break;
22185default:
22186break;
22187}
22188break;
22189case 3:
22190OPGEN_RETURN(true);
22191break;
22192default:
22193break;
22194}
22195break;
22196case 1:
22197switch (args.size()) {
22198case 2:
22199switch (args[0].kind()) {
22200case Arg::Tmp:
22201switch (Arg::Addr) {
22202case Arg::Tmp:
22203break;
22204case Arg::Addr:
22205case Arg::Stack:
22206case Arg::CallArg:
22207OPGEN_RETURN(true);
22208break;
22209break;
22210case Arg::Index:
22211break;
22212default:
22213break;
22214}
22215break;
22216case Arg::Addr:
22217case Arg::Stack:
22218case Arg::CallArg:
22219break;
22220case Arg::Index:
22221break;
22222default:
22223break;
22224}
22225break;
22226case 3:
22227OPGEN_RETURN(true);
22228break;
22229default:
22230break;
22231}
22232break;
22233case 2:
22234OPGEN_RETURN(false);
22235break;
22236default:
22237break;
22238}
22239break;
22240case Opcode::MoveZeroToDouble:
22241switch (argIndex) {
22242case 0:
22243OPGEN_RETURN(false);
22244break;
22245default:
22246break;
22247}
22248break;
22249case Opcode::Move64ToDouble:
22250switch (argIndex) {
22251case 0:
22252switch (Arg::Addr) {
22253case Arg::Tmp:
22254break;
22255case Arg::Addr:
22256case Arg::Stack:
22257case Arg::CallArg:
22258switch (args[1].kind()) {
22259case Arg::Tmp:
22260#if CPU(X86_64)
22261OPGEN_RETURN(true);
22262#endif
22263break;
22264break;
22265default:
22266break;
22267}
22268break;
22269case Arg::Index:
22270break;
22271default:
22272break;
22273}
22274break;
22275case 1:
22276OPGEN_RETURN(false);
22277break;
22278default:
22279break;
22280}
22281break;
22282case Opcode::Move32ToFloat:
22283switch (argIndex) {
22284case 0:
22285switch (Arg::Addr) {
22286case Arg::Tmp:
22287break;
22288case Arg::Addr:
22289case Arg::Stack:
22290case Arg::CallArg:
22291switch (args[1].kind()) {
22292case Arg::Tmp:
22293#if CPU(X86) || CPU(X86_64)
22294OPGEN_RETURN(true);
22295#endif
22296break;
22297break;
22298default:
22299break;
22300}
22301break;
22302case Arg::Index:
22303break;
22304default:
22305break;
22306}
22307break;
22308case 1:
22309OPGEN_RETURN(false);
22310break;
22311default:
22312break;
22313}
22314break;
22315case Opcode::MoveDoubleTo64:
22316switch (argIndex) {
22317case 0:
22318switch (Arg::Addr) {
22319case Arg::Tmp:
22320break;
22321case Arg::Addr:
22322case Arg::Stack:
22323case Arg::CallArg:
22324switch (args[1].kind()) {
22325case Arg::Tmp:
22326#if CPU(X86_64) || CPU(ARM64)
22327OPGEN_RETURN(true);
22328#endif
22329break;
22330break;
22331default:
22332break;
22333}
22334break;
22335case Arg::Index:
22336break;
22337default:
22338break;
22339}
22340break;
22341case 1:
22342OPGEN_RETURN(false);
22343break;
22344default:
22345break;
22346}
22347break;
22348case Opcode::MoveFloatTo32:
22349switch (argIndex) {
22350case 0:
22351switch (Arg::Addr) {
22352case Arg::Tmp:
22353break;
22354case Arg::Addr:
22355case Arg::Stack:
22356case Arg::CallArg:
22357switch (args[1].kind()) {
22358case Arg::Tmp:
22359OPGEN_RETURN(true);
22360break;
22361break;
22362default:
22363break;
22364}
22365break;
22366case Arg::Index:
22367break;
22368default:
22369break;
22370}
22371break;
22372case 1:
22373OPGEN_RETURN(false);
22374break;
22375default:
22376break;
22377}
22378break;
22379case Opcode::Load8:
22380switch (argIndex) {
22381case 0:
22382switch (Arg::Addr) {
22383case Arg::Addr:
22384case Arg::Stack:
22385case Arg::CallArg:
22386switch (args[1].kind()) {
22387case Arg::Tmp:
22388OPGEN_RETURN(true);
22389break;
22390break;
22391default:
22392break;
22393}
22394break;
22395case Arg::Index:
22396break;
22397default:
22398break;
22399}
22400break;
22401case 1:
22402OPGEN_RETURN(false);
22403break;
22404default:
22405break;
22406}
22407break;
22408case Opcode::LoadAcq8:
22409switch (argIndex) {
22410case 0:
22411OPGEN_RETURN(false);
22412break;
22413case 1:
22414OPGEN_RETURN(false);
22415break;
22416default:
22417break;
22418}
22419break;
22420case Opcode::Store8:
22421switch (argIndex) {
22422case 0:
22423OPGEN_RETURN(false);
22424break;
22425case 1:
22426switch (args[0].kind()) {
22427case Arg::Tmp:
22428switch (Arg::Addr) {
22429case Arg::Index:
22430break;
22431case Arg::Addr:
22432case Arg::Stack:
22433case Arg::CallArg:
22434OPGEN_RETURN(true);
22435break;
22436break;
22437default:
22438break;
22439}
22440break;
22441case Arg::Imm:
22442switch (Arg::Addr) {
22443case Arg::Index:
22444break;
22445case Arg::Addr:
22446case Arg::Stack:
22447case Arg::CallArg:
22448#if CPU(X86) || CPU(X86_64)
22449OPGEN_RETURN(true);
22450#endif
22451break;
22452break;
22453default:
22454break;
22455}
22456break;
22457default:
22458break;
22459}
22460break;
22461default:
22462break;
22463}
22464break;
22465case Opcode::StoreRel8:
22466switch (argIndex) {
22467case 0:
22468OPGEN_RETURN(false);
22469break;
22470case 1:
22471OPGEN_RETURN(false);
22472break;
22473default:
22474break;
22475}
22476break;
22477case Opcode::Load8SignedExtendTo32:
22478switch (argIndex) {
22479case 0:
22480switch (Arg::Addr) {
22481case Arg::Addr:
22482case Arg::Stack:
22483case Arg::CallArg:
22484switch (args[1].kind()) {
22485case Arg::Tmp:
22486OPGEN_RETURN(true);
22487break;
22488break;
22489default:
22490break;
22491}
22492break;
22493case Arg::Index:
22494break;
22495default:
22496break;
22497}
22498break;
22499case 1:
22500OPGEN_RETURN(false);
22501break;
22502default:
22503break;
22504}
22505break;
22506case Opcode::LoadAcq8SignedExtendTo32:
22507switch (argIndex) {
22508case 0:
22509OPGEN_RETURN(false);
22510break;
22511case 1:
22512OPGEN_RETURN(false);
22513break;
22514default:
22515break;
22516}
22517break;
22518case Opcode::Load16:
22519switch (argIndex) {
22520case 0:
22521switch (Arg::Addr) {
22522case Arg::Addr:
22523case Arg::Stack:
22524case Arg::CallArg:
22525switch (args[1].kind()) {
22526case Arg::Tmp:
22527OPGEN_RETURN(true);
22528break;
22529break;
22530default:
22531break;
22532}
22533break;
22534case Arg::Index:
22535break;
22536default:
22537break;
22538}
22539break;
22540case 1:
22541OPGEN_RETURN(false);
22542break;
22543default:
22544break;
22545}
22546break;
22547case Opcode::LoadAcq16:
22548switch (argIndex) {
22549case 0:
22550OPGEN_RETURN(false);
22551break;
22552case 1:
22553OPGEN_RETURN(false);
22554break;
22555default:
22556break;
22557}
22558break;
22559case Opcode::Load16SignedExtendTo32:
22560switch (argIndex) {
22561case 0:
22562switch (Arg::Addr) {
22563case Arg::Addr:
22564case Arg::Stack:
22565case Arg::CallArg:
22566switch (args[1].kind()) {
22567case Arg::Tmp:
22568OPGEN_RETURN(true);
22569break;
22570break;
22571default:
22572break;
22573}
22574break;
22575case Arg::Index:
22576break;
22577default:
22578break;
22579}
22580break;
22581case 1:
22582OPGEN_RETURN(false);
22583break;
22584default:
22585break;
22586}
22587break;
22588case Opcode::LoadAcq16SignedExtendTo32:
22589switch (argIndex) {
22590case 0:
22591OPGEN_RETURN(false);
22592break;
22593case 1:
22594OPGEN_RETURN(false);
22595break;
22596default:
22597break;
22598}
22599break;
22600case Opcode::Store16:
22601switch (argIndex) {
22602case 0:
22603OPGEN_RETURN(false);
22604break;
22605case 1:
22606switch (args[0].kind()) {
22607case Arg::Tmp:
22608switch (Arg::Addr) {
22609case Arg::Index:
22610break;
22611case Arg::Addr:
22612case Arg::Stack:
22613case Arg::CallArg:
22614OPGEN_RETURN(true);
22615break;
22616break;
22617default:
22618break;
22619}
22620break;
22621case Arg::Imm:
22622switch (Arg::Addr) {
22623case Arg::Index:
22624break;
22625case Arg::Addr:
22626case Arg::Stack:
22627case Arg::CallArg:
22628#if CPU(X86) || CPU(X86_64)
22629OPGEN_RETURN(true);
22630#endif
22631break;
22632break;
22633default:
22634break;
22635}
22636break;
22637default:
22638break;
22639}
22640break;
22641default:
22642break;
22643}
22644break;
22645case Opcode::StoreRel16:
22646switch (argIndex) {
22647case 0:
22648OPGEN_RETURN(false);
22649break;
22650case 1:
22651OPGEN_RETURN(false);
22652break;
22653default:
22654break;
22655}
22656break;
22657case Opcode::LoadAcq32:
22658switch (argIndex) {
22659case 0:
22660OPGEN_RETURN(false);
22661break;
22662case 1:
22663OPGEN_RETURN(false);
22664break;
22665default:
22666break;
22667}
22668break;
22669case Opcode::StoreRel32:
22670switch (argIndex) {
22671case 0:
22672OPGEN_RETURN(false);
22673break;
22674case 1:
22675OPGEN_RETURN(false);
22676break;
22677default:
22678break;
22679}
22680break;
22681case Opcode::LoadAcq64:
22682switch (argIndex) {
22683case 0:
22684OPGEN_RETURN(false);
22685break;
22686case 1:
22687OPGEN_RETURN(false);
22688break;
22689default:
22690break;
22691}
22692break;
22693case Opcode::StoreRel64:
22694switch (argIndex) {
22695case 0:
22696OPGEN_RETURN(false);
22697break;
22698case 1:
22699OPGEN_RETURN(false);
22700break;
22701default:
22702break;
22703}
22704break;
22705case Opcode::Xchg8:
22706switch (argIndex) {
22707case 0:
22708OPGEN_RETURN(false);
22709break;
22710case 1:
22711switch (args[0].kind()) {
22712case Arg::Tmp:
22713switch (Arg::Addr) {
22714case Arg::Addr:
22715case Arg::Stack:
22716case Arg::CallArg:
22717#if CPU(X86) || CPU(X86_64)
22718OPGEN_RETURN(true);
22719#endif
22720break;
22721break;
22722case Arg::Index:
22723break;
22724default:
22725break;
22726}
22727break;
22728default:
22729break;
22730}
22731break;
22732default:
22733break;
22734}
22735break;
22736case Opcode::Xchg16:
22737switch (argIndex) {
22738case 0:
22739OPGEN_RETURN(false);
22740break;
22741case 1:
22742switch (args[0].kind()) {
22743case Arg::Tmp:
22744switch (Arg::Addr) {
22745case Arg::Addr:
22746case Arg::Stack:
22747case Arg::CallArg:
22748#if CPU(X86) || CPU(X86_64)
22749OPGEN_RETURN(true);
22750#endif
22751break;
22752break;
22753case Arg::Index:
22754break;
22755default:
22756break;
22757}
22758break;
22759default:
22760break;
22761}
22762break;
22763default:
22764break;
22765}
22766break;
22767case Opcode::Xchg32:
22768switch (argIndex) {
22769case 0:
22770OPGEN_RETURN(false);
22771break;
22772case 1:
22773switch (args[0].kind()) {
22774case Arg::Tmp:
22775switch (Arg::Addr) {
22776case Arg::Addr:
22777case Arg::Stack:
22778case Arg::CallArg:
22779#if CPU(X86) || CPU(X86_64)
22780OPGEN_RETURN(true);
22781#endif
22782break;
22783break;
22784case Arg::Index:
22785break;
22786default:
22787break;
22788}
22789break;
22790default:
22791break;
22792}
22793break;
22794default:
22795break;
22796}
22797break;
22798case Opcode::Xchg64:
22799switch (argIndex) {
22800case 0:
22801OPGEN_RETURN(false);
22802break;
22803case 1:
22804switch (args[0].kind()) {
22805case Arg::Tmp:
22806switch (Arg::Addr) {
22807case Arg::Addr:
22808case Arg::Stack:
22809case Arg::CallArg:
22810#if CPU(X86_64)
22811OPGEN_RETURN(true);
22812#endif
22813break;
22814break;
22815case Arg::Index:
22816break;
22817default:
22818break;
22819}
22820break;
22821default:
22822break;
22823}
22824break;
22825default:
22826break;
22827}
22828break;
22829case Opcode::AtomicStrongCAS8:
22830switch (argIndex) {
22831case 0:
22832OPGEN_RETURN(false);
22833break;
22834case 1:
22835OPGEN_RETURN(false);
22836break;
22837case 2:
22838switch (args.size()) {
22839case 3:
22840switch (args[0].kind()) {
22841case Arg::Tmp:
22842switch (args[1].kind()) {
22843case Arg::Tmp:
22844switch (Arg::Addr) {
22845case Arg::Addr:
22846case Arg::Stack:
22847case Arg::CallArg:
22848#if CPU(X86) || CPU(X86_64)
22849OPGEN_RETURN(true);
22850#endif
22851break;
22852break;
22853case Arg::Index:
22854break;
22855default:
22856break;
22857}
22858break;
22859default:
22860break;
22861}
22862break;
22863default:
22864break;
22865}
22866break;
22867default:
22868break;
22869}
22870break;
22871case 3:
22872switch (args.size()) {
22873case 5:
22874switch (args[0].kind()) {
22875case Arg::StatusCond:
22876switch (args[1].kind()) {
22877case Arg::Tmp:
22878switch (args[2].kind()) {
22879case Arg::Tmp:
22880switch (Arg::Addr) {
22881case Arg::Addr:
22882case Arg::Stack:
22883case Arg::CallArg:
22884switch (args[4].kind()) {
22885case Arg::Tmp:
22886#if CPU(X86) || CPU(X86_64)
22887OPGEN_RETURN(true);
22888#endif
22889break;
22890break;
22891default:
22892break;
22893}
22894break;
22895case Arg::Index:
22896break;
22897default:
22898break;
22899}
22900break;
22901default:
22902break;
22903}
22904break;
22905default:
22906break;
22907}
22908break;
22909default:
22910break;
22911}
22912break;
22913default:
22914break;
22915}
22916break;
22917case 4:
22918OPGEN_RETURN(false);
22919break;
22920default:
22921break;
22922}
22923break;
22924case Opcode::AtomicStrongCAS16:
22925switch (argIndex) {
22926case 0:
22927OPGEN_RETURN(false);
22928break;
22929case 1:
22930OPGEN_RETURN(false);
22931break;
22932case 2:
22933switch (args.size()) {
22934case 3:
22935switch (args[0].kind()) {
22936case Arg::Tmp:
22937switch (args[1].kind()) {
22938case Arg::Tmp:
22939switch (Arg::Addr) {
22940case Arg::Addr:
22941case Arg::Stack:
22942case Arg::CallArg:
22943#if CPU(X86) || CPU(X86_64)
22944OPGEN_RETURN(true);
22945#endif
22946break;
22947break;
22948case Arg::Index:
22949break;
22950default:
22951break;
22952}
22953break;
22954default:
22955break;
22956}
22957break;
22958default:
22959break;
22960}
22961break;
22962default:
22963break;
22964}
22965break;
22966case 3:
22967switch (args.size()) {
22968case 5:
22969switch (args[0].kind()) {
22970case Arg::StatusCond:
22971switch (args[1].kind()) {
22972case Arg::Tmp:
22973switch (args[2].kind()) {
22974case Arg::Tmp:
22975switch (Arg::Addr) {
22976case Arg::Addr:
22977case Arg::Stack:
22978case Arg::CallArg:
22979switch (args[4].kind()) {
22980case Arg::Tmp:
22981#if CPU(X86) || CPU(X86_64)
22982OPGEN_RETURN(true);
22983#endif
22984break;
22985break;
22986default:
22987break;
22988}
22989break;
22990case Arg::Index:
22991break;
22992default:
22993break;
22994}
22995break;
22996default:
22997break;
22998}
22999break;
23000default:
23001break;
23002}
23003break;
23004default:
23005break;
23006}
23007break;
23008default:
23009break;
23010}
23011break;
23012case 4:
23013OPGEN_RETURN(false);
23014break;
23015default:
23016break;
23017}
23018break;
23019case Opcode::AtomicStrongCAS32:
23020switch (argIndex) {
23021case 0:
23022OPGEN_RETURN(false);
23023break;
23024case 1:
23025OPGEN_RETURN(false);
23026break;
23027case 2:
23028switch (args.size()) {
23029case 3:
23030switch (args[0].kind()) {
23031case Arg::Tmp:
23032switch (args[1].kind()) {
23033case Arg::Tmp:
23034switch (Arg::Addr) {
23035case Arg::Addr:
23036case Arg::Stack:
23037case Arg::CallArg:
23038#if CPU(X86) || CPU(X86_64)
23039OPGEN_RETURN(true);
23040#endif
23041break;
23042break;
23043case Arg::Index:
23044break;
23045default:
23046break;
23047}
23048break;
23049default:
23050break;
23051}
23052break;
23053default:
23054break;
23055}
23056break;
23057default:
23058break;
23059}
23060break;
23061case 3:
23062switch (args.size()) {
23063case 5:
23064switch (args[0].kind()) {
23065case Arg::StatusCond:
23066switch (args[1].kind()) {
23067case Arg::Tmp:
23068switch (args[2].kind()) {
23069case Arg::Tmp:
23070switch (Arg::Addr) {
23071case Arg::Addr:
23072case Arg::Stack:
23073case Arg::CallArg:
23074switch (args[4].kind()) {
23075case Arg::Tmp:
23076#if CPU(X86) || CPU(X86_64)
23077OPGEN_RETURN(true);
23078#endif
23079break;
23080break;
23081default:
23082break;
23083}
23084break;
23085case Arg::Index:
23086break;
23087default:
23088break;
23089}
23090break;
23091default:
23092break;
23093}
23094break;
23095default:
23096break;
23097}
23098break;
23099default:
23100break;
23101}
23102break;
23103default:
23104break;
23105}
23106break;
23107case 4:
23108OPGEN_RETURN(false);
23109break;
23110default:
23111break;
23112}
23113break;
23114case Opcode::AtomicStrongCAS64:
23115switch (argIndex) {
23116case 0:
23117OPGEN_RETURN(false);
23118break;
23119case 1:
23120OPGEN_RETURN(false);
23121break;
23122case 2:
23123switch (args.size()) {
23124case 3:
23125switch (args[0].kind()) {
23126case Arg::Tmp:
23127switch (args[1].kind()) {
23128case Arg::Tmp:
23129switch (Arg::Addr) {
23130case Arg::Addr:
23131case Arg::Stack:
23132case Arg::CallArg:
23133#if CPU(X86_64)
23134OPGEN_RETURN(true);
23135#endif
23136break;
23137break;
23138case Arg::Index:
23139break;
23140default:
23141break;
23142}
23143break;
23144default:
23145break;
23146}
23147break;
23148default:
23149break;
23150}
23151break;
23152default:
23153break;
23154}
23155break;
23156case 3:
23157switch (args.size()) {
23158case 5:
23159switch (args[0].kind()) {
23160case Arg::StatusCond:
23161switch (args[1].kind()) {
23162case Arg::Tmp:
23163switch (args[2].kind()) {
23164case Arg::Tmp:
23165switch (Arg::Addr) {
23166case Arg::Addr:
23167case Arg::Stack:
23168case Arg::CallArg:
23169switch (args[4].kind()) {
23170case Arg::Tmp:
23171#if CPU(X86_64)
23172OPGEN_RETURN(true);
23173#endif
23174break;
23175break;
23176default:
23177break;
23178}
23179break;
23180case Arg::Index:
23181break;
23182default:
23183break;
23184}
23185break;
23186default:
23187break;
23188}
23189break;
23190default:
23191break;
23192}
23193break;
23194default:
23195break;
23196}
23197break;
23198default:
23199break;
23200}
23201break;
23202case 4:
23203OPGEN_RETURN(false);
23204break;
23205default:
23206break;
23207}
23208break;
23209case Opcode::BranchAtomicStrongCAS8:
23210switch (argIndex) {
23211case 0:
23212OPGEN_RETURN(false);
23213break;
23214case 1:
23215OPGEN_RETURN(false);
23216break;
23217case 2:
23218OPGEN_RETURN(false);
23219break;
23220case 3:
23221switch (args[0].kind()) {
23222case Arg::StatusCond:
23223switch (args[1].kind()) {
23224case Arg::Tmp:
23225switch (args[2].kind()) {
23226case Arg::Tmp:
23227switch (Arg::Addr) {
23228case Arg::Addr:
23229case Arg::Stack:
23230case Arg::CallArg:
23231#if CPU(X86) || CPU(X86_64)
23232OPGEN_RETURN(true);
23233#endif
23234break;
23235break;
23236case Arg::Index:
23237break;
23238default:
23239break;
23240}
23241break;
23242default:
23243break;
23244}
23245break;
23246default:
23247break;
23248}
23249break;
23250default:
23251break;
23252}
23253break;
23254default:
23255break;
23256}
23257break;
23258case Opcode::BranchAtomicStrongCAS16:
23259switch (argIndex) {
23260case 0:
23261OPGEN_RETURN(false);
23262break;
23263case 1:
23264OPGEN_RETURN(false);
23265break;
23266case 2:
23267OPGEN_RETURN(false);
23268break;
23269case 3:
23270switch (args[0].kind()) {
23271case Arg::StatusCond:
23272switch (args[1].kind()) {
23273case Arg::Tmp:
23274switch (args[2].kind()) {
23275case Arg::Tmp:
23276switch (Arg::Addr) {
23277case Arg::Addr:
23278case Arg::Stack:
23279case Arg::CallArg:
23280#if CPU(X86) || CPU(X86_64)
23281OPGEN_RETURN(true);
23282#endif
23283break;
23284break;
23285case Arg::Index:
23286break;
23287default:
23288break;
23289}
23290break;
23291default:
23292break;
23293}
23294break;
23295default:
23296break;
23297}
23298break;
23299default:
23300break;
23301}
23302break;
23303default:
23304break;
23305}
23306break;
23307case Opcode::BranchAtomicStrongCAS32:
23308switch (argIndex) {
23309case 0:
23310OPGEN_RETURN(false);
23311break;
23312case 1:
23313OPGEN_RETURN(false);
23314break;
23315case 2:
23316OPGEN_RETURN(false);
23317break;
23318case 3:
23319switch (args[0].kind()) {
23320case Arg::StatusCond:
23321switch (args[1].kind()) {
23322case Arg::Tmp:
23323switch (args[2].kind()) {
23324case Arg::Tmp:
23325switch (Arg::Addr) {
23326case Arg::Addr:
23327case Arg::Stack:
23328case Arg::CallArg:
23329#if CPU(X86) || CPU(X86_64)
23330OPGEN_RETURN(true);
23331#endif
23332break;
23333break;
23334case Arg::Index:
23335break;
23336default:
23337break;
23338}
23339break;
23340default:
23341break;
23342}
23343break;
23344default:
23345break;
23346}
23347break;
23348default:
23349break;
23350}
23351break;
23352default:
23353break;
23354}
23355break;
23356case Opcode::BranchAtomicStrongCAS64:
23357switch (argIndex) {
23358case 0:
23359OPGEN_RETURN(false);
23360break;
23361case 1:
23362OPGEN_RETURN(false);
23363break;
23364case 2:
23365OPGEN_RETURN(false);
23366break;
23367case 3:
23368switch (args[0].kind()) {
23369case Arg::StatusCond:
23370switch (args[1].kind()) {
23371case Arg::Tmp:
23372switch (args[2].kind()) {
23373case Arg::Tmp:
23374switch (Arg::Addr) {
23375case Arg::Addr:
23376case Arg::Stack:
23377case Arg::CallArg:
23378#if CPU(X86_64)
23379OPGEN_RETURN(true);
23380#endif
23381break;
23382break;
23383case Arg::Index:
23384break;
23385default:
23386break;
23387}
23388break;
23389default:
23390break;
23391}
23392break;
23393default:
23394break;
23395}
23396break;
23397default:
23398break;
23399}
23400break;
23401default:
23402break;
23403}
23404break;
23405case Opcode::AtomicAdd8:
23406switch (argIndex) {
23407case 0:
23408OPGEN_RETURN(false);
23409break;
23410case 1:
23411switch (args[0].kind()) {
23412case Arg::Imm:
23413switch (Arg::Addr) {
23414case Arg::Addr:
23415case Arg::Stack:
23416case Arg::CallArg:
23417#if CPU(X86) || CPU(X86_64)
23418OPGEN_RETURN(true);
23419#endif
23420break;
23421break;
23422case Arg::Index:
23423break;
23424default:
23425break;
23426}
23427break;
23428case Arg::Tmp:
23429switch (Arg::Addr) {
23430case Arg::Addr:
23431case Arg::Stack:
23432case Arg::CallArg:
23433#if CPU(X86) || CPU(X86_64)
23434OPGEN_RETURN(true);
23435#endif
23436break;
23437break;
23438case Arg::Index:
23439break;
23440default:
23441break;
23442}
23443break;
23444default:
23445break;
23446}
23447break;
23448default:
23449break;
23450}
23451break;
23452case Opcode::AtomicAdd16:
23453switch (argIndex) {
23454case 0:
23455OPGEN_RETURN(false);
23456break;
23457case 1:
23458switch (args[0].kind()) {
23459case Arg::Imm:
23460switch (Arg::Addr) {
23461case Arg::Addr:
23462case Arg::Stack:
23463case Arg::CallArg:
23464#if CPU(X86) || CPU(X86_64)
23465OPGEN_RETURN(true);
23466#endif
23467break;
23468break;
23469case Arg::Index:
23470break;
23471default:
23472break;
23473}
23474break;
23475case Arg::Tmp:
23476switch (Arg::Addr) {
23477case Arg::Addr:
23478case Arg::Stack:
23479case Arg::CallArg:
23480#if CPU(X86) || CPU(X86_64)
23481OPGEN_RETURN(true);
23482#endif
23483break;
23484break;
23485case Arg::Index:
23486break;
23487default:
23488break;
23489}
23490break;
23491default:
23492break;
23493}
23494break;
23495default:
23496break;
23497}
23498break;
23499case Opcode::AtomicAdd32:
23500switch (argIndex) {
23501case 0:
23502OPGEN_RETURN(false);
23503break;
23504case 1:
23505switch (args[0].kind()) {
23506case Arg::Imm:
23507switch (Arg::Addr) {
23508case Arg::Addr:
23509case Arg::Stack:
23510case Arg::CallArg:
23511#if CPU(X86) || CPU(X86_64)
23512OPGEN_RETURN(true);
23513#endif
23514break;
23515break;
23516case Arg::Index:
23517break;
23518default:
23519break;
23520}
23521break;
23522case Arg::Tmp:
23523switch (Arg::Addr) {
23524case Arg::Addr:
23525case Arg::Stack:
23526case Arg::CallArg:
23527#if CPU(X86) || CPU(X86_64)
23528OPGEN_RETURN(true);
23529#endif
23530break;
23531break;
23532case Arg::Index:
23533break;
23534default:
23535break;
23536}
23537break;
23538default:
23539break;
23540}
23541break;
23542default:
23543break;
23544}
23545break;
23546case Opcode::AtomicAdd64:
23547switch (argIndex) {
23548case 0:
23549OPGEN_RETURN(false);
23550break;
23551case 1:
23552switch (args[0].kind()) {
23553case Arg::Imm:
23554switch (Arg::Addr) {
23555case Arg::Addr:
23556case Arg::Stack:
23557case Arg::CallArg:
23558#if CPU(X86_64)
23559OPGEN_RETURN(true);
23560#endif
23561break;
23562break;
23563case Arg::Index:
23564break;
23565default:
23566break;
23567}
23568break;
23569case Arg::Tmp:
23570switch (Arg::Addr) {
23571case Arg::Addr:
23572case Arg::Stack:
23573case Arg::CallArg:
23574#if CPU(X86_64)
23575OPGEN_RETURN(true);
23576#endif
23577break;
23578break;
23579case Arg::Index:
23580break;
23581default:
23582break;
23583}
23584break;
23585default:
23586break;
23587}
23588break;
23589default:
23590break;
23591}
23592break;
23593case Opcode::AtomicSub8:
23594switch (argIndex) {
23595case 0:
23596OPGEN_RETURN(false);
23597break;
23598case 1:
23599switch (args[0].kind()) {
23600case Arg::Imm:
23601switch (Arg::Addr) {
23602case Arg::Addr:
23603case Arg::Stack:
23604case Arg::CallArg:
23605#if CPU(X86) || CPU(X86_64)
23606OPGEN_RETURN(true);
23607#endif
23608break;
23609break;
23610case Arg::Index:
23611break;
23612default:
23613break;
23614}
23615break;
23616case Arg::Tmp:
23617switch (Arg::Addr) {
23618case Arg::Addr:
23619case Arg::Stack:
23620case Arg::CallArg:
23621#if CPU(X86) || CPU(X86_64)
23622OPGEN_RETURN(true);
23623#endif
23624break;
23625break;
23626case Arg::Index:
23627break;
23628default:
23629break;
23630}
23631break;
23632default:
23633break;
23634}
23635break;
23636default:
23637break;
23638}
23639break;
23640case Opcode::AtomicSub16:
23641switch (argIndex) {
23642case 0:
23643OPGEN_RETURN(false);
23644break;
23645case 1:
23646switch (args[0].kind()) {
23647case Arg::Imm:
23648switch (Arg::Addr) {
23649case Arg::Addr:
23650case Arg::Stack:
23651case Arg::CallArg:
23652#if CPU(X86) || CPU(X86_64)
23653OPGEN_RETURN(true);
23654#endif
23655break;
23656break;
23657case Arg::Index:
23658break;
23659default:
23660break;
23661}
23662break;
23663case Arg::Tmp:
23664switch (Arg::Addr) {
23665case Arg::Addr:
23666case Arg::Stack:
23667case Arg::CallArg:
23668#if CPU(X86) || CPU(X86_64)
23669OPGEN_RETURN(true);
23670#endif
23671break;
23672break;
23673case Arg::Index:
23674break;
23675default:
23676break;
23677}
23678break;
23679default:
23680break;
23681}
23682break;
23683default:
23684break;
23685}
23686break;
23687case Opcode::AtomicSub32:
23688switch (argIndex) {
23689case 0:
23690OPGEN_RETURN(false);
23691break;
23692case 1:
23693switch (args[0].kind()) {
23694case Arg::Imm:
23695switch (Arg::Addr) {
23696case Arg::Addr:
23697case Arg::Stack:
23698case Arg::CallArg:
23699#if CPU(X86) || CPU(X86_64)
23700OPGEN_RETURN(true);
23701#endif
23702break;
23703break;
23704case Arg::Index:
23705break;
23706default:
23707break;
23708}
23709break;
23710case Arg::Tmp:
23711switch (Arg::Addr) {
23712case Arg::Addr:
23713case Arg::Stack:
23714case Arg::CallArg:
23715#if CPU(X86) || CPU(X86_64)
23716OPGEN_RETURN(true);
23717#endif
23718break;
23719break;
23720case Arg::Index:
23721break;
23722default:
23723break;
23724}
23725break;
23726default:
23727break;
23728}
23729break;
23730default:
23731break;
23732}
23733break;
23734case Opcode::AtomicSub64:
23735switch (argIndex) {
23736case 0:
23737OPGEN_RETURN(false);
23738break;
23739case 1:
23740switch (args[0].kind()) {
23741case Arg::Imm:
23742switch (Arg::Addr) {
23743case Arg::Addr:
23744case Arg::Stack:
23745case Arg::CallArg:
23746#if CPU(X86_64)
23747OPGEN_RETURN(true);
23748#endif
23749break;
23750break;
23751case Arg::Index:
23752break;
23753default:
23754break;
23755}
23756break;
23757case Arg::Tmp:
23758switch (Arg::Addr) {
23759case Arg::Addr:
23760case Arg::Stack:
23761case Arg::CallArg:
23762#if CPU(X86_64)
23763OPGEN_RETURN(true);
23764#endif
23765break;
23766break;
23767case Arg::Index:
23768break;
23769default:
23770break;
23771}
23772break;
23773default:
23774break;
23775}
23776break;
23777default:
23778break;
23779}
23780break;
23781case Opcode::AtomicAnd8:
23782switch (argIndex) {
23783case 0:
23784OPGEN_RETURN(false);
23785break;
23786case 1:
23787switch (args[0].kind()) {
23788case Arg::Imm:
23789switch (Arg::Addr) {
23790case Arg::Addr:
23791case Arg::Stack:
23792case Arg::CallArg:
23793#if CPU(X86) || CPU(X86_64)
23794OPGEN_RETURN(true);
23795#endif
23796break;
23797break;
23798case Arg::Index:
23799break;
23800default:
23801break;
23802}
23803break;
23804case Arg::Tmp:
23805switch (Arg::Addr) {
23806case Arg::Addr:
23807case Arg::Stack:
23808case Arg::CallArg:
23809#if CPU(X86) || CPU(X86_64)
23810OPGEN_RETURN(true);
23811#endif
23812break;
23813break;
23814case Arg::Index:
23815break;
23816default:
23817break;
23818}
23819break;
23820default:
23821break;
23822}
23823break;
23824default:
23825break;
23826}
23827break;
23828case Opcode::AtomicAnd16:
23829switch (argIndex) {
23830case 0:
23831OPGEN_RETURN(false);
23832break;
23833case 1:
23834switch (args[0].kind()) {
23835case Arg::Imm:
23836switch (Arg::Addr) {
23837case Arg::Addr:
23838case Arg::Stack:
23839case Arg::CallArg:
23840#if CPU(X86) || CPU(X86_64)
23841OPGEN_RETURN(true);
23842#endif
23843break;
23844break;
23845case Arg::Index:
23846break;
23847default:
23848break;
23849}
23850break;
23851case Arg::Tmp:
23852switch (Arg::Addr) {
23853case Arg::Addr:
23854case Arg::Stack:
23855case Arg::CallArg:
23856#if CPU(X86) || CPU(X86_64)
23857OPGEN_RETURN(true);
23858#endif
23859break;
23860break;
23861case Arg::Index:
23862break;
23863default:
23864break;
23865}
23866break;
23867default:
23868break;
23869}
23870break;
23871default:
23872break;
23873}
23874break;
23875case Opcode::AtomicAnd32:
23876switch (argIndex) {
23877case 0:
23878OPGEN_RETURN(false);
23879break;
23880case 1:
23881switch (args[0].kind()) {
23882case Arg::Imm:
23883switch (Arg::Addr) {
23884case Arg::Addr:
23885case Arg::Stack:
23886case Arg::CallArg:
23887#if CPU(X86) || CPU(X86_64)
23888OPGEN_RETURN(true);
23889#endif
23890break;
23891break;
23892case Arg::Index:
23893break;
23894default:
23895break;
23896}
23897break;
23898case Arg::Tmp:
23899switch (Arg::Addr) {
23900case Arg::Addr:
23901case Arg::Stack:
23902case Arg::CallArg:
23903#if CPU(X86) || CPU(X86_64)
23904OPGEN_RETURN(true);
23905#endif
23906break;
23907break;
23908case Arg::Index:
23909break;
23910default:
23911break;
23912}
23913break;
23914default:
23915break;
23916}
23917break;
23918default:
23919break;
23920}
23921break;
23922case Opcode::AtomicAnd64:
23923switch (argIndex) {
23924case 0:
23925OPGEN_RETURN(false);
23926break;
23927case 1:
23928switch (args[0].kind()) {
23929case Arg::Imm:
23930switch (Arg::Addr) {
23931case Arg::Addr:
23932case Arg::Stack:
23933case Arg::CallArg:
23934#if CPU(X86_64)
23935OPGEN_RETURN(true);
23936#endif
23937break;
23938break;
23939case Arg::Index:
23940break;
23941default:
23942break;
23943}
23944break;
23945case Arg::Tmp:
23946switch (Arg::Addr) {
23947case Arg::Addr:
23948case Arg::Stack:
23949case Arg::CallArg:
23950#if CPU(X86_64)
23951OPGEN_RETURN(true);
23952#endif
23953break;
23954break;
23955case Arg::Index:
23956break;
23957default:
23958break;
23959}
23960break;
23961default:
23962break;
23963}
23964break;
23965default:
23966break;
23967}
23968break;
23969case Opcode::AtomicOr8:
23970switch (argIndex) {
23971case 0:
23972OPGEN_RETURN(false);
23973break;
23974case 1:
23975switch (args[0].kind()) {
23976case Arg::Imm:
23977switch (Arg::Addr) {
23978case Arg::Addr:
23979case Arg::Stack:
23980case Arg::CallArg:
23981#if CPU(X86) || CPU(X86_64)
23982OPGEN_RETURN(true);
23983#endif
23984break;
23985break;
23986case Arg::Index:
23987break;
23988default:
23989break;
23990}
23991break;
23992case Arg::Tmp:
23993switch (Arg::Addr) {
23994case Arg::Addr:
23995case Arg::Stack:
23996case Arg::CallArg:
23997#if CPU(X86) || CPU(X86_64)
23998OPGEN_RETURN(true);
23999#endif
24000break;
24001break;
24002case Arg::Index:
24003break;
24004default:
24005break;
24006}
24007break;
24008default:
24009break;
24010}
24011break;
24012default:
24013break;
24014}
24015break;
24016case Opcode::AtomicOr16:
24017switch (argIndex) {
24018case 0:
24019OPGEN_RETURN(false);
24020break;
24021case 1:
24022switch (args[0].kind()) {
24023case Arg::Imm:
24024switch (Arg::Addr) {
24025case Arg::Addr:
24026case Arg::Stack:
24027case Arg::CallArg:
24028#if CPU(X86) || CPU(X86_64)
24029OPGEN_RETURN(true);
24030#endif
24031break;
24032break;
24033case Arg::Index:
24034break;
24035default:
24036break;
24037}
24038break;
24039case Arg::Tmp:
24040switch (Arg::Addr) {
24041case Arg::Addr:
24042case Arg::Stack:
24043case Arg::CallArg:
24044#if CPU(X86) || CPU(X86_64)
24045OPGEN_RETURN(true);
24046#endif
24047break;
24048break;
24049case Arg::Index:
24050break;
24051default:
24052break;
24053}
24054break;
24055default:
24056break;
24057}
24058break;
24059default:
24060break;
24061}
24062break;
24063case Opcode::AtomicOr32:
24064switch (argIndex) {
24065case 0:
24066OPGEN_RETURN(false);
24067break;
24068case 1:
24069switch (args[0].kind()) {
24070case Arg::Imm:
24071switch (Arg::Addr) {
24072case Arg::Addr:
24073case Arg::Stack:
24074case Arg::CallArg:
24075#if CPU(X86) || CPU(X86_64)
24076OPGEN_RETURN(true);
24077#endif
24078break;
24079break;
24080case Arg::Index:
24081break;
24082default:
24083break;
24084}
24085break;
24086case Arg::Tmp:
24087switch (Arg::Addr) {
24088case Arg::Addr:
24089case Arg::Stack:
24090case Arg::CallArg:
24091#if CPU(X86) || CPU(X86_64)
24092OPGEN_RETURN(true);
24093#endif
24094break;
24095break;
24096case Arg::Index:
24097break;
24098default:
24099break;
24100}
24101break;
24102default:
24103break;
24104}
24105break;
24106default:
24107break;
24108}
24109break;
24110case Opcode::AtomicOr64:
24111switch (argIndex) {
24112case 0:
24113OPGEN_RETURN(false);
24114break;
24115case 1:
24116switch (args[0].kind()) {
24117case Arg::Imm:
24118switch (Arg::Addr) {
24119case Arg::Addr:
24120case Arg::Stack:
24121case Arg::CallArg:
24122#if CPU(X86_64)
24123OPGEN_RETURN(true);
24124#endif
24125break;
24126break;
24127case Arg::Index:
24128break;
24129default:
24130break;
24131}
24132break;
24133case Arg::Tmp:
24134switch (Arg::Addr) {
24135case Arg::Addr:
24136case Arg::Stack:
24137case Arg::CallArg:
24138#if CPU(X86_64)
24139OPGEN_RETURN(true);
24140#endif
24141break;
24142break;
24143case Arg::Index:
24144break;
24145default:
24146break;
24147}
24148break;
24149default:
24150break;
24151}
24152break;
24153default:
24154break;
24155}
24156break;
24157case Opcode::AtomicXor8:
24158switch (argIndex) {
24159case 0:
24160OPGEN_RETURN(false);
24161break;
24162case 1:
24163switch (args[0].kind()) {
24164case Arg::Imm:
24165switch (Arg::Addr) {
24166case Arg::Addr:
24167case Arg::Stack:
24168case Arg::CallArg:
24169#if CPU(X86) || CPU(X86_64)
24170OPGEN_RETURN(true);
24171#endif
24172break;
24173break;
24174case Arg::Index:
24175break;
24176default:
24177break;
24178}
24179break;
24180case Arg::Tmp:
24181switch (Arg::Addr) {
24182case Arg::Addr:
24183case Arg::Stack:
24184case Arg::CallArg:
24185#if CPU(X86) || CPU(X86_64)
24186OPGEN_RETURN(true);
24187#endif
24188break;
24189break;
24190case Arg::Index:
24191break;
24192default:
24193break;
24194}
24195break;
24196default:
24197break;
24198}
24199break;
24200default:
24201break;
24202}
24203break;
24204case Opcode::AtomicXor16:
24205switch (argIndex) {
24206case 0:
24207OPGEN_RETURN(false);
24208break;
24209case 1:
24210switch (args[0].kind()) {
24211case Arg::Imm:
24212switch (Arg::Addr) {
24213case Arg::Addr:
24214case Arg::Stack:
24215case Arg::CallArg:
24216#if CPU(X86) || CPU(X86_64)
24217OPGEN_RETURN(true);
24218#endif
24219break;
24220break;
24221case Arg::Index:
24222break;
24223default:
24224break;
24225}
24226break;
24227case Arg::Tmp:
24228switch (Arg::Addr) {
24229case Arg::Addr:
24230case Arg::Stack:
24231case Arg::CallArg:
24232#if CPU(X86) || CPU(X86_64)
24233OPGEN_RETURN(true);
24234#endif
24235break;
24236break;
24237case Arg::Index:
24238break;
24239default:
24240break;
24241}
24242break;
24243default:
24244break;
24245}
24246break;
24247default:
24248break;
24249}
24250break;
24251case Opcode::AtomicXor32:
24252switch (argIndex) {
24253case 0:
24254OPGEN_RETURN(false);
24255break;
24256case 1:
24257switch (args[0].kind()) {
24258case Arg::Imm:
24259switch (Arg::Addr) {
24260case Arg::Addr:
24261case Arg::Stack:
24262case Arg::CallArg:
24263#if CPU(X86) || CPU(X86_64)
24264OPGEN_RETURN(true);
24265#endif
24266break;
24267break;
24268case Arg::Index:
24269break;
24270default:
24271break;
24272}
24273break;
24274case Arg::Tmp:
24275switch (Arg::Addr) {
24276case Arg::Addr:
24277case Arg::Stack:
24278case Arg::CallArg:
24279#if CPU(X86) || CPU(X86_64)
24280OPGEN_RETURN(true);
24281#endif
24282break;
24283break;
24284case Arg::Index:
24285break;
24286default:
24287break;
24288}
24289break;
24290default:
24291break;
24292}
24293break;
24294default:
24295break;
24296}
24297break;
24298case Opcode::AtomicXor64:
24299switch (argIndex) {
24300case 0:
24301OPGEN_RETURN(false);
24302break;
24303case 1:
24304switch (args[0].kind()) {
24305case Arg::Imm:
24306switch (Arg::Addr) {
24307case Arg::Addr:
24308case Arg::Stack:
24309case Arg::CallArg:
24310#if CPU(X86_64)
24311OPGEN_RETURN(true);
24312#endif
24313break;
24314break;
24315case Arg::Index:
24316break;
24317default:
24318break;
24319}
24320break;
24321case Arg::Tmp:
24322switch (Arg::Addr) {
24323case Arg::Addr:
24324case Arg::Stack:
24325case Arg::CallArg:
24326#if CPU(X86_64)
24327OPGEN_RETURN(true);
24328#endif
24329break;
24330break;
24331case Arg::Index:
24332break;
24333default:
24334break;
24335}
24336break;
24337default:
24338break;
24339}
24340break;
24341default:
24342break;
24343}
24344break;
24345case Opcode::AtomicNeg8:
24346switch (argIndex) {
24347case 0:
24348switch (Arg::Addr) {
24349case Arg::Addr:
24350case Arg::Stack:
24351case Arg::CallArg:
24352#if CPU(X86) || CPU(X86_64)
24353OPGEN_RETURN(true);
24354#endif
24355break;
24356break;
24357case Arg::Index:
24358break;
24359default:
24360break;
24361}
24362break;
24363default:
24364break;
24365}
24366break;
24367case Opcode::AtomicNeg16:
24368switch (argIndex) {
24369case 0:
24370switch (Arg::Addr) {
24371case Arg::Addr:
24372case Arg::Stack:
24373case Arg::CallArg:
24374#if CPU(X86) || CPU(X86_64)
24375OPGEN_RETURN(true);
24376#endif
24377break;
24378break;
24379case Arg::Index:
24380break;
24381default:
24382break;
24383}
24384break;
24385default:
24386break;
24387}
24388break;
24389case Opcode::AtomicNeg32:
24390switch (argIndex) {
24391case 0:
24392switch (Arg::Addr) {
24393case Arg::Addr:
24394case Arg::Stack:
24395case Arg::CallArg:
24396#if CPU(X86) || CPU(X86_64)
24397OPGEN_RETURN(true);
24398#endif
24399break;
24400break;
24401case Arg::Index:
24402break;
24403default:
24404break;
24405}
24406break;
24407default:
24408break;
24409}
24410break;
24411case Opcode::AtomicNeg64:
24412switch (argIndex) {
24413case 0:
24414switch (Arg::Addr) {
24415case Arg::Addr:
24416case Arg::Stack:
24417case Arg::CallArg:
24418#if CPU(X86_64)
24419OPGEN_RETURN(true);
24420#endif
24421break;
24422break;
24423case Arg::Index:
24424break;
24425default:
24426break;
24427}
24428break;
24429default:
24430break;
24431}
24432break;
24433case Opcode::AtomicNot8:
24434switch (argIndex) {
24435case 0:
24436switch (Arg::Addr) {
24437case Arg::Addr:
24438case Arg::Stack:
24439case Arg::CallArg:
24440#if CPU(X86) || CPU(X86_64)
24441OPGEN_RETURN(true);
24442#endif
24443break;
24444break;
24445case Arg::Index:
24446break;
24447default:
24448break;
24449}
24450break;
24451default:
24452break;
24453}
24454break;
24455case Opcode::AtomicNot16:
24456switch (argIndex) {
24457case 0:
24458switch (Arg::Addr) {
24459case Arg::Addr:
24460case Arg::Stack:
24461case Arg::CallArg:
24462#if CPU(X86) || CPU(X86_64)
24463OPGEN_RETURN(true);
24464#endif
24465break;
24466break;
24467case Arg::Index:
24468break;
24469default:
24470break;
24471}
24472break;
24473default:
24474break;
24475}
24476break;
24477case Opcode::AtomicNot32:
24478switch (argIndex) {
24479case 0:
24480switch (Arg::Addr) {
24481case Arg::Addr:
24482case Arg::Stack:
24483case Arg::CallArg:
24484#if CPU(X86) || CPU(X86_64)
24485OPGEN_RETURN(true);
24486#endif
24487break;
24488break;
24489case Arg::Index:
24490break;
24491default:
24492break;
24493}
24494break;
24495default:
24496break;
24497}
24498break;
24499case Opcode::AtomicNot64:
24500switch (argIndex) {
24501case 0:
24502switch (Arg::Addr) {
24503case Arg::Addr:
24504case Arg::Stack:
24505case Arg::CallArg:
24506#if CPU(X86_64)
24507OPGEN_RETURN(true);
24508#endif
24509break;
24510break;
24511case Arg::Index:
24512break;
24513default:
24514break;
24515}
24516break;
24517default:
24518break;
24519}
24520break;
24521case Opcode::AtomicXchgAdd8:
24522switch (argIndex) {
24523case 0:
24524OPGEN_RETURN(false);
24525break;
24526case 1:
24527switch (args[0].kind()) {
24528case Arg::Tmp:
24529switch (Arg::Addr) {
24530case Arg::Addr:
24531case Arg::Stack:
24532case Arg::CallArg:
24533#if CPU(X86) || CPU(X86_64)
24534OPGEN_RETURN(true);
24535#endif
24536break;
24537break;
24538case Arg::Index:
24539break;
24540default:
24541break;
24542}
24543break;
24544default:
24545break;
24546}
24547break;
24548default:
24549break;
24550}
24551break;
24552case Opcode::AtomicXchgAdd16:
24553switch (argIndex) {
24554case 0:
24555OPGEN_RETURN(false);
24556break;
24557case 1:
24558switch (args[0].kind()) {
24559case Arg::Tmp:
24560switch (Arg::Addr) {
24561case Arg::Addr:
24562case Arg::Stack:
24563case Arg::CallArg:
24564#if CPU(X86) || CPU(X86_64)
24565OPGEN_RETURN(true);
24566#endif
24567break;
24568break;
24569case Arg::Index:
24570break;
24571default:
24572break;
24573}
24574break;
24575default:
24576break;
24577}
24578break;
24579default:
24580break;
24581}
24582break;
24583case Opcode::AtomicXchgAdd32:
24584switch (argIndex) {
24585case 0:
24586OPGEN_RETURN(false);
24587break;
24588case 1:
24589switch (args[0].kind()) {
24590case Arg::Tmp:
24591switch (Arg::Addr) {
24592case Arg::Addr:
24593case Arg::Stack:
24594case Arg::CallArg:
24595#if CPU(X86) || CPU(X86_64)
24596OPGEN_RETURN(true);
24597#endif
24598break;
24599break;
24600case Arg::Index:
24601break;
24602default:
24603break;
24604}
24605break;
24606default:
24607break;
24608}
24609break;
24610default:
24611break;
24612}
24613break;
24614case Opcode::AtomicXchgAdd64:
24615switch (argIndex) {
24616case 0:
24617OPGEN_RETURN(false);
24618break;
24619case 1:
24620switch (args[0].kind()) {
24621case Arg::Tmp:
24622switch (Arg::Addr) {
24623case Arg::Addr:
24624case Arg::Stack:
24625case Arg::CallArg:
24626#if CPU(X86_64)
24627OPGEN_RETURN(true);
24628#endif
24629break;
24630break;
24631case Arg::Index:
24632break;
24633default:
24634break;
24635}
24636break;
24637default:
24638break;
24639}
24640break;
24641default:
24642break;
24643}
24644break;
24645case Opcode::AtomicXchg8:
24646switch (argIndex) {
24647case 0:
24648OPGEN_RETURN(false);
24649break;
24650case 1:
24651switch (args[0].kind()) {
24652case Arg::Tmp:
24653switch (Arg::Addr) {
24654case Arg::Addr:
24655case Arg::Stack:
24656case Arg::CallArg:
24657#if CPU(X86) || CPU(X86_64)
24658OPGEN_RETURN(true);
24659#endif
24660break;
24661break;
24662case Arg::Index:
24663break;
24664default:
24665break;
24666}
24667break;
24668default:
24669break;
24670}
24671break;
24672default:
24673break;
24674}
24675break;
24676case Opcode::AtomicXchg16:
24677switch (argIndex) {
24678case 0:
24679OPGEN_RETURN(false);
24680break;
24681case 1:
24682switch (args[0].kind()) {
24683case Arg::Tmp:
24684switch (Arg::Addr) {
24685case Arg::Addr:
24686case Arg::Stack:
24687case Arg::CallArg:
24688#if CPU(X86) || CPU(X86_64)
24689OPGEN_RETURN(true);
24690#endif
24691break;
24692break;
24693case Arg::Index:
24694break;
24695default:
24696break;
24697}
24698break;
24699default:
24700break;
24701}
24702break;
24703default:
24704break;
24705}
24706break;
24707case Opcode::AtomicXchg32:
24708switch (argIndex) {
24709case 0:
24710OPGEN_RETURN(false);
24711break;
24712case 1:
24713switch (args[0].kind()) {
24714case Arg::Tmp:
24715switch (Arg::Addr) {
24716case Arg::Addr:
24717case Arg::Stack:
24718case Arg::CallArg:
24719#if CPU(X86) || CPU(X86_64)
24720OPGEN_RETURN(true);
24721#endif
24722break;
24723break;
24724case Arg::Index:
24725break;
24726default:
24727break;
24728}
24729break;
24730default:
24731break;
24732}
24733break;
24734default:
24735break;
24736}
24737break;
24738case Opcode::AtomicXchg64:
24739switch (argIndex) {
24740case 0:
24741OPGEN_RETURN(false);
24742break;
24743case 1:
24744switch (args[0].kind()) {
24745case Arg::Tmp:
24746switch (Arg::Addr) {
24747case Arg::Addr:
24748case Arg::Stack:
24749case Arg::CallArg:
24750#if CPU(X86_64)
24751OPGEN_RETURN(true);
24752#endif
24753break;
24754break;
24755case Arg::Index:
24756break;
24757default:
24758break;
24759}
24760break;
24761default:
24762break;
24763}
24764break;
24765default:
24766break;
24767}
24768break;
24769case Opcode::LoadLink8:
24770switch (argIndex) {
24771case 0:
24772OPGEN_RETURN(false);
24773break;
24774case 1:
24775OPGEN_RETURN(false);
24776break;
24777default:
24778break;
24779}
24780break;
24781case Opcode::LoadLinkAcq8:
24782switch (argIndex) {
24783case 0:
24784OPGEN_RETURN(false);
24785break;
24786case 1:
24787OPGEN_RETURN(false);
24788break;
24789default:
24790break;
24791}
24792break;
24793case Opcode::StoreCond8:
24794switch (argIndex) {
24795case 0:
24796OPGEN_RETURN(false);
24797break;
24798case 1:
24799OPGEN_RETURN(false);
24800break;
24801case 2:
24802OPGEN_RETURN(false);
24803break;
24804default:
24805break;
24806}
24807break;
24808case Opcode::StoreCondRel8:
24809switch (argIndex) {
24810case 0:
24811OPGEN_RETURN(false);
24812break;
24813case 1:
24814OPGEN_RETURN(false);
24815break;
24816case 2:
24817OPGEN_RETURN(false);
24818break;
24819default:
24820break;
24821}
24822break;
24823case Opcode::LoadLink16:
24824switch (argIndex) {
24825case 0:
24826OPGEN_RETURN(false);
24827break;
24828case 1:
24829OPGEN_RETURN(false);
24830break;
24831default:
24832break;
24833}
24834break;
24835case Opcode::LoadLinkAcq16:
24836switch (argIndex) {
24837case 0:
24838OPGEN_RETURN(false);
24839break;
24840case 1:
24841OPGEN_RETURN(false);
24842break;
24843default:
24844break;
24845}
24846break;
24847case Opcode::StoreCond16:
24848switch (argIndex) {
24849case 0:
24850OPGEN_RETURN(false);
24851break;
24852case 1:
24853OPGEN_RETURN(false);
24854break;
24855case 2:
24856OPGEN_RETURN(false);
24857break;
24858default:
24859break;
24860}
24861break;
24862case Opcode::StoreCondRel16:
24863switch (argIndex) {
24864case 0:
24865OPGEN_RETURN(false);
24866break;
24867case 1:
24868OPGEN_RETURN(false);
24869break;
24870case 2:
24871OPGEN_RETURN(false);
24872break;
24873default:
24874break;
24875}
24876break;
24877case Opcode::LoadLink32:
24878switch (argIndex) {
24879case 0:
24880OPGEN_RETURN(false);
24881break;
24882case 1:
24883OPGEN_RETURN(false);
24884break;
24885default:
24886break;
24887}
24888break;
24889case Opcode::LoadLinkAcq32:
24890switch (argIndex) {
24891case 0:
24892OPGEN_RETURN(false);
24893break;
24894case 1:
24895OPGEN_RETURN(false);
24896break;
24897default:
24898break;
24899}
24900break;
24901case Opcode::StoreCond32:
24902switch (argIndex) {
24903case 0:
24904OPGEN_RETURN(false);
24905break;
24906case 1:
24907OPGEN_RETURN(false);
24908break;
24909case 2:
24910OPGEN_RETURN(false);
24911break;
24912default:
24913break;
24914}
24915break;
24916case Opcode::StoreCondRel32:
24917switch (argIndex) {
24918case 0:
24919OPGEN_RETURN(false);
24920break;
24921case 1:
24922OPGEN_RETURN(false);
24923break;
24924case 2:
24925OPGEN_RETURN(false);
24926break;
24927default:
24928break;
24929}
24930break;
24931case Opcode::LoadLink64:
24932switch (argIndex) {
24933case 0:
24934OPGEN_RETURN(false);
24935break;
24936case 1:
24937OPGEN_RETURN(false);
24938break;
24939default:
24940break;
24941}
24942break;
24943case Opcode::LoadLinkAcq64:
24944switch (argIndex) {
24945case 0:
24946OPGEN_RETURN(false);
24947break;
24948case 1:
24949OPGEN_RETURN(false);
24950break;
24951default:
24952break;
24953}
24954break;
24955case Opcode::StoreCond64:
24956switch (argIndex) {
24957case 0:
24958OPGEN_RETURN(false);
24959break;
24960case 1:
24961OPGEN_RETURN(false);
24962break;
24963case 2:
24964OPGEN_RETURN(false);
24965break;
24966default:
24967break;
24968}
24969break;
24970case Opcode::StoreCondRel64:
24971switch (argIndex) {
24972case 0:
24973OPGEN_RETURN(false);
24974break;
24975case 1:
24976OPGEN_RETURN(false);
24977break;
24978case 2:
24979OPGEN_RETURN(false);
24980break;
24981default:
24982break;
24983}
24984break;
24985case Opcode::Depend32:
24986switch (argIndex) {
24987case 0:
24988OPGEN_RETURN(false);
24989break;
24990case 1:
24991OPGEN_RETURN(false);
24992break;
24993default:
24994break;
24995}
24996break;
24997case Opcode::Depend64:
24998switch (argIndex) {
24999case 0:
25000OPGEN_RETURN(false);
25001break;
25002case 1:
25003OPGEN_RETURN(false);
25004break;
25005default:
25006break;
25007}
25008break;
25009case Opcode::Compare32:
25010switch (argIndex) {
25011case 0:
25012OPGEN_RETURN(false);
25013break;
25014case 1:
25015OPGEN_RETURN(false);
25016break;
25017case 2:
25018OPGEN_RETURN(false);
25019break;
25020case 3:
25021OPGEN_RETURN(false);
25022break;
25023default:
25024break;
25025}
25026break;
25027case Opcode::Compare64:
25028switch (argIndex) {
25029case 0:
25030OPGEN_RETURN(false);
25031break;
25032case 1:
25033OPGEN_RETURN(false);
25034break;
25035case 2:
25036OPGEN_RETURN(false);
25037break;
25038case 3:
25039OPGEN_RETURN(false);
25040break;
25041default:
25042break;
25043}
25044break;
25045case Opcode::Test32:
25046switch (argIndex) {
25047case 0:
25048OPGEN_RETURN(false);
25049break;
25050case 1:
25051switch (args[0].kind()) {
25052case Arg::ResCond:
25053switch (Arg::Addr) {
25054case Arg::Addr:
25055case Arg::Stack:
25056case Arg::CallArg:
25057switch (args[2].kind()) {
25058case Arg::Imm:
25059switch (args[3].kind()) {
25060case Arg::Tmp:
25061#if CPU(X86) || CPU(X86_64)
25062OPGEN_RETURN(true);
25063#endif
25064break;
25065break;
25066default:
25067break;
25068}
25069break;
25070default:
25071break;
25072}
25073break;
25074case Arg::Tmp:
25075break;
25076default:
25077break;
25078}
25079break;
25080default:
25081break;
25082}
25083break;
25084case 2:
25085OPGEN_RETURN(false);
25086break;
25087case 3:
25088OPGEN_RETURN(false);
25089break;
25090default:
25091break;
25092}
25093break;
25094case Opcode::Test64:
25095switch (argIndex) {
25096case 0:
25097OPGEN_RETURN(false);
25098break;
25099case 1:
25100OPGEN_RETURN(false);
25101break;
25102case 2:
25103OPGEN_RETURN(false);
25104break;
25105case 3:
25106OPGEN_RETURN(false);
25107break;
25108default:
25109break;
25110}
25111break;
25112case Opcode::CompareDouble:
25113switch (argIndex) {
25114case 0:
25115OPGEN_RETURN(false);
25116break;
25117case 1:
25118OPGEN_RETURN(false);
25119break;
25120case 2:
25121OPGEN_RETURN(false);
25122break;
25123case 3:
25124OPGEN_RETURN(false);
25125break;
25126default:
25127break;
25128}
25129break;
25130case Opcode::CompareFloat:
25131switch (argIndex) {
25132case 0:
25133OPGEN_RETURN(false);
25134break;
25135case 1:
25136OPGEN_RETURN(false);
25137break;
25138case 2:
25139OPGEN_RETURN(false);
25140break;
25141case 3:
25142OPGEN_RETURN(false);
25143break;
25144default:
25145break;
25146}
25147break;
25148case Opcode::Branch8:
25149switch (argIndex) {
25150case 0:
25151OPGEN_RETURN(false);
25152break;
25153case 1:
25154switch (args[0].kind()) {
25155case Arg::RelCond:
25156switch (Arg::Addr) {
25157case Arg::Addr:
25158case Arg::Stack:
25159case Arg::CallArg:
25160switch (args[2].kind()) {
25161case Arg::Imm:
25162#if CPU(X86) || CPU(X86_64)
25163OPGEN_RETURN(true);
25164#endif
25165break;
25166break;
25167default:
25168break;
25169}
25170break;
25171case Arg::Index:
25172break;
25173default:
25174break;
25175}
25176break;
25177default:
25178break;
25179}
25180break;
25181case 2:
25182OPGEN_RETURN(false);
25183break;
25184default:
25185break;
25186}
25187break;
25188case Opcode::Branch32:
25189switch (argIndex) {
25190case 0:
25191OPGEN_RETURN(false);
25192break;
25193case 1:
25194switch (args[0].kind()) {
25195case Arg::RelCond:
25196switch (Arg::Addr) {
25197case Arg::Addr:
25198case Arg::Stack:
25199case Arg::CallArg:
25200switch (args[2].kind()) {
25201case Arg::Imm:
25202#if CPU(X86) || CPU(X86_64)
25203OPGEN_RETURN(true);
25204#endif
25205break;
25206break;
25207case Arg::Tmp:
25208#if CPU(X86) || CPU(X86_64)
25209OPGEN_RETURN(true);
25210#endif
25211break;
25212break;
25213default:
25214break;
25215}
25216break;
25217case Arg::Tmp:
25218break;
25219case Arg::Index:
25220break;
25221default:
25222break;
25223}
25224break;
25225default:
25226break;
25227}
25228break;
25229case 2:
25230switch (args[0].kind()) {
25231case Arg::RelCond:
25232switch (args[1].kind()) {
25233case Arg::Addr:
25234case Arg::Stack:
25235case Arg::CallArg:
25236break;
25237case Arg::Tmp:
25238switch (Arg::Addr) {
25239case Arg::Tmp:
25240break;
25241case Arg::Imm:
25242break;
25243case Arg::Addr:
25244case Arg::Stack:
25245case Arg::CallArg:
25246#if CPU(X86) || CPU(X86_64)
25247OPGEN_RETURN(true);
25248#endif
25249break;
25250break;
25251default:
25252break;
25253}
25254break;
25255case Arg::Index:
25256break;
25257default:
25258break;
25259}
25260break;
25261default:
25262break;
25263}
25264break;
25265default:
25266break;
25267}
25268break;
25269case Opcode::Branch64:
25270switch (argIndex) {
25271case 0:
25272OPGEN_RETURN(false);
25273break;
25274case 1:
25275switch (args[0].kind()) {
25276case Arg::RelCond:
25277switch (Arg::Addr) {
25278case Arg::Tmp:
25279break;
25280case Arg::Addr:
25281case Arg::Stack:
25282case Arg::CallArg:
25283switch (args[2].kind()) {
25284case Arg::Tmp:
25285#if CPU(X86_64)
25286OPGEN_RETURN(true);
25287#endif
25288break;
25289break;
25290case Arg::Imm:
25291#if CPU(X86_64)
25292OPGEN_RETURN(true);
25293#endif
25294break;
25295break;
25296default:
25297break;
25298}
25299break;
25300case Arg::Index:
25301break;
25302default:
25303break;
25304}
25305break;
25306default:
25307break;
25308}
25309break;
25310case 2:
25311switch (args[0].kind()) {
25312case Arg::RelCond:
25313switch (args[1].kind()) {
25314case Arg::Tmp:
25315switch (Arg::Addr) {
25316case Arg::Tmp:
25317break;
25318case Arg::Imm:
25319break;
25320case Arg::Addr:
25321case Arg::Stack:
25322case Arg::CallArg:
25323#if CPU(X86_64)
25324OPGEN_RETURN(true);
25325#endif
25326break;
25327break;
25328default:
25329break;
25330}
25331break;
25332case Arg::Addr:
25333case Arg::Stack:
25334case Arg::CallArg:
25335break;
25336case Arg::Index:
25337break;
25338default:
25339break;
25340}
25341break;
25342default:
25343break;
25344}
25345break;
25346default:
25347break;
25348}
25349break;
25350case Opcode::BranchTest8:
25351switch (argIndex) {
25352case 0:
25353OPGEN_RETURN(false);
25354break;
25355case 1:
25356switch (args[0].kind()) {
25357case Arg::ResCond:
25358switch (Arg::Addr) {
25359case Arg::Addr:
25360case Arg::Stack:
25361case Arg::CallArg:
25362switch (args[2].kind()) {
25363case Arg::BitImm:
25364#if CPU(X86) || CPU(X86_64)
25365OPGEN_RETURN(true);
25366#endif
25367break;
25368break;
25369default:
25370break;
25371}
25372break;
25373case Arg::Index:
25374break;
25375default:
25376break;
25377}
25378break;
25379default:
25380break;
25381}
25382break;
25383case 2:
25384OPGEN_RETURN(false);
25385break;
25386default:
25387break;
25388}
25389break;
25390case Opcode::BranchTest32:
25391switch (argIndex) {
25392case 0:
25393OPGEN_RETURN(false);
25394break;
25395case 1:
25396switch (args[0].kind()) {
25397case Arg::ResCond:
25398switch (Arg::Addr) {
25399case Arg::Tmp:
25400break;
25401case Arg::Addr:
25402case Arg::Stack:
25403case Arg::CallArg:
25404switch (args[2].kind()) {
25405case Arg::BitImm:
25406#if CPU(X86) || CPU(X86_64)
25407OPGEN_RETURN(true);
25408#endif
25409break;
25410break;
25411default:
25412break;
25413}
25414break;
25415case Arg::Index:
25416break;
25417default:
25418break;
25419}
25420break;
25421default:
25422break;
25423}
25424break;
25425case 2:
25426OPGEN_RETURN(false);
25427break;
25428default:
25429break;
25430}
25431break;
25432case Opcode::BranchTest64:
25433switch (argIndex) {
25434case 0:
25435OPGEN_RETURN(false);
25436break;
25437case 1:
25438switch (args[0].kind()) {
25439case Arg::ResCond:
25440switch (Arg::Addr) {
25441case Arg::Tmp:
25442break;
25443case Arg::Addr:
25444case Arg::Stack:
25445case Arg::CallArg:
25446switch (args[2].kind()) {
25447case Arg::BitImm:
25448#if CPU(X86_64)
25449OPGEN_RETURN(true);
25450#endif
25451break;
25452break;
25453case Arg::Tmp:
25454#if CPU(X86_64)
25455OPGEN_RETURN(true);
25456#endif
25457break;
25458break;
25459default:
25460break;
25461}
25462break;
25463case Arg::Index:
25464break;
25465default:
25466break;
25467}
25468break;
25469default:
25470break;
25471}
25472break;
25473case 2:
25474OPGEN_RETURN(false);
25475break;
25476default:
25477break;
25478}
25479break;
25480case Opcode::BranchDouble:
25481switch (argIndex) {
25482case 0:
25483OPGEN_RETURN(false);
25484break;
25485case 1:
25486OPGEN_RETURN(false);
25487break;
25488case 2:
25489OPGEN_RETURN(false);
25490break;
25491default:
25492break;
25493}
25494break;
25495case Opcode::BranchFloat:
25496switch (argIndex) {
25497case 0:
25498OPGEN_RETURN(false);
25499break;
25500case 1:
25501OPGEN_RETURN(false);
25502break;
25503case 2:
25504OPGEN_RETURN(false);
25505break;
25506default:
25507break;
25508}
25509break;
25510case Opcode::BranchAdd32:
25511switch (argIndex) {
25512case 0:
25513OPGEN_RETURN(false);
25514break;
25515case 1:
25516switch (args.size()) {
25517case 4:
25518switch (args[0].kind()) {
25519case Arg::ResCond:
25520switch (Arg::Addr) {
25521case Arg::Tmp:
25522break;
25523case Arg::Addr:
25524case Arg::Stack:
25525case Arg::CallArg:
25526switch (args[2].kind()) {
25527case Arg::Tmp:
25528switch (args[3].kind()) {
25529case Arg::Tmp:
25530#if CPU(X86) || CPU(X86_64)
25531OPGEN_RETURN(true);
25532#endif
25533break;
25534break;
25535default:
25536break;
25537}
25538break;
25539default:
25540break;
25541}
25542break;
25543default:
25544break;
25545}
25546break;
25547default:
25548break;
25549}
25550break;
25551case 3:
25552switch (args[0].kind()) {
25553case Arg::ResCond:
25554switch (Arg::Addr) {
25555case Arg::Tmp:
25556break;
25557case Arg::Imm:
25558break;
25559case Arg::Addr:
25560case Arg::Stack:
25561case Arg::CallArg:
25562switch (args[2].kind()) {
25563case Arg::Tmp:
25564#if CPU(X86) || CPU(X86_64)
25565OPGEN_RETURN(true);
25566#endif
25567break;
25568break;
25569default:
25570break;
25571}
25572break;
25573default:
25574break;
25575}
25576break;
25577default:
25578break;
25579}
25580break;
25581default:
25582break;
25583}
25584break;
25585case 2:
25586switch (args.size()) {
25587case 4:
25588switch (args[0].kind()) {
25589case Arg::ResCond:
25590switch (args[1].kind()) {
25591case Arg::Tmp:
25592switch (Arg::Addr) {
25593case Arg::Tmp:
25594break;
25595case Arg::Addr:
25596case Arg::Stack:
25597case Arg::CallArg:
25598switch (args[3].kind()) {
25599case Arg::Tmp:
25600#if CPU(X86) || CPU(X86_64)
25601OPGEN_RETURN(true);
25602#endif
25603break;
25604break;
25605default:
25606break;
25607}
25608break;
25609default:
25610break;
25611}
25612break;
25613case Arg::Addr:
25614case Arg::Stack:
25615case Arg::CallArg:
25616break;
25617default:
25618break;
25619}
25620break;
25621default:
25622break;
25623}
25624break;
25625case 3:
25626switch (args[0].kind()) {
25627case Arg::ResCond:
25628switch (args[1].kind()) {
25629case Arg::Tmp:
25630switch (Arg::Addr) {
25631case Arg::Tmp:
25632break;
25633case Arg::Addr:
25634case Arg::Stack:
25635case Arg::CallArg:
25636#if CPU(X86) || CPU(X86_64)
25637OPGEN_RETURN(true);
25638#endif
25639break;
25640break;
25641default:
25642break;
25643}
25644break;
25645case Arg::Imm:
25646switch (Arg::Addr) {
25647case Arg::Tmp:
25648break;
25649case Arg::Addr:
25650case Arg::Stack:
25651case Arg::CallArg:
25652#if CPU(X86) || CPU(X86_64)
25653OPGEN_RETURN(true);
25654#endif
25655break;
25656break;
25657default:
25658break;
25659}
25660break;
25661case Arg::Addr:
25662case Arg::Stack:
25663case Arg::CallArg:
25664break;
25665default:
25666break;
25667}
25668break;
25669default:
25670break;
25671}
25672break;
25673default:
25674break;
25675}
25676break;
25677case 3:
25678OPGEN_RETURN(false);
25679break;
25680default:
25681break;
25682}
25683break;
25684case Opcode::BranchAdd64:
25685switch (argIndex) {
25686case 0:
25687OPGEN_RETURN(false);
25688break;
25689case 1:
25690switch (args.size()) {
25691case 4:
25692switch (args[0].kind()) {
25693case Arg::ResCond:
25694switch (Arg::Addr) {
25695case Arg::Tmp:
25696break;
25697case Arg::Addr:
25698case Arg::Stack:
25699case Arg::CallArg:
25700switch (args[2].kind()) {
25701case Arg::Tmp:
25702switch (args[3].kind()) {
25703case Arg::Tmp:
25704#if CPU(X86) || CPU(X86_64)
25705OPGEN_RETURN(true);
25706#endif
25707break;
25708break;
25709default:
25710break;
25711}
25712break;
25713default:
25714break;
25715}
25716break;
25717default:
25718break;
25719}
25720break;
25721default:
25722break;
25723}
25724break;
25725case 3:
25726switch (args[0].kind()) {
25727case Arg::ResCond:
25728switch (Arg::Addr) {
25729case Arg::Imm:
25730break;
25731case Arg::Tmp:
25732break;
25733case Arg::Addr:
25734case Arg::Stack:
25735case Arg::CallArg:
25736switch (args[2].kind()) {
25737case Arg::Tmp:
25738#if CPU(X86_64)
25739OPGEN_RETURN(true);
25740#endif
25741break;
25742break;
25743default:
25744break;
25745}
25746break;
25747default:
25748break;
25749}
25750break;
25751default:
25752break;
25753}
25754break;
25755default:
25756break;
25757}
25758break;
25759case 2:
25760switch (args.size()) {
25761case 4:
25762switch (args[0].kind()) {
25763case Arg::ResCond:
25764switch (args[1].kind()) {
25765case Arg::Tmp:
25766switch (Arg::Addr) {
25767case Arg::Tmp:
25768break;
25769case Arg::Addr:
25770case Arg::Stack:
25771case Arg::CallArg:
25772switch (args[3].kind()) {
25773case Arg::Tmp:
25774#if CPU(X86) || CPU(X86_64)
25775OPGEN_RETURN(true);
25776#endif
25777break;
25778break;
25779default:
25780break;
25781}
25782break;
25783default:
25784break;
25785}
25786break;
25787case Arg::Addr:
25788case Arg::Stack:
25789case Arg::CallArg:
25790break;
25791default:
25792break;
25793}
25794break;
25795default:
25796break;
25797}
25798break;
25799default:
25800break;
25801}
25802break;
25803case 3:
25804OPGEN_RETURN(false);
25805break;
25806default:
25807break;
25808}
25809break;
25810case Opcode::BranchMul32:
25811switch (argIndex) {
25812case 0:
25813OPGEN_RETURN(false);
25814break;
25815case 1:
25816switch (args.size()) {
25817case 3:
25818switch (args[0].kind()) {
25819case Arg::ResCond:
25820switch (Arg::Addr) {
25821case Arg::Tmp:
25822break;
25823case Arg::Addr:
25824case Arg::Stack:
25825case Arg::CallArg:
25826switch (args[2].kind()) {
25827case Arg::Tmp:
25828#if CPU(X86) || CPU(X86_64)
25829OPGEN_RETURN(true);
25830#endif
25831break;
25832break;
25833default:
25834break;
25835}
25836break;
25837default:
25838break;
25839}
25840break;
25841default:
25842break;
25843}
25844break;
25845default:
25846break;
25847}
25848break;
25849case 2:
25850OPGEN_RETURN(false);
25851break;
25852case 3:
25853OPGEN_RETURN(false);
25854break;
25855case 4:
25856OPGEN_RETURN(false);
25857break;
25858case 5:
25859OPGEN_RETURN(false);
25860break;
25861default:
25862break;
25863}
25864break;
25865case Opcode::BranchMul64:
25866switch (argIndex) {
25867case 0:
25868OPGEN_RETURN(false);
25869break;
25870case 1:
25871OPGEN_RETURN(false);
25872break;
25873case 2:
25874OPGEN_RETURN(false);
25875break;
25876case 3:
25877OPGEN_RETURN(false);
25878break;
25879case 4:
25880OPGEN_RETURN(false);
25881break;
25882case 5:
25883OPGEN_RETURN(false);
25884break;
25885default:
25886break;
25887}
25888break;
25889case Opcode::BranchSub32:
25890switch (argIndex) {
25891case 0:
25892OPGEN_RETURN(false);
25893break;
25894case 1:
25895switch (args[0].kind()) {
25896case Arg::ResCond:
25897switch (Arg::Addr) {
25898case Arg::Tmp:
25899break;
25900case Arg::Imm:
25901break;
25902case Arg::Addr:
25903case Arg::Stack:
25904case Arg::CallArg:
25905switch (args[2].kind()) {
25906case Arg::Tmp:
25907#if CPU(X86) || CPU(X86_64)
25908OPGEN_RETURN(true);
25909#endif
25910break;
25911break;
25912default:
25913break;
25914}
25915break;
25916default:
25917break;
25918}
25919break;
25920default:
25921break;
25922}
25923break;
25924case 2:
25925switch (args[0].kind()) {
25926case Arg::ResCond:
25927switch (args[1].kind()) {
25928case Arg::Tmp:
25929switch (Arg::Addr) {
25930case Arg::Tmp:
25931break;
25932case Arg::Addr:
25933case Arg::Stack:
25934case Arg::CallArg:
25935#if CPU(X86) || CPU(X86_64)
25936OPGEN_RETURN(true);
25937#endif
25938break;
25939break;
25940default:
25941break;
25942}
25943break;
25944case Arg::Imm:
25945switch (Arg::Addr) {
25946case Arg::Tmp:
25947break;
25948case Arg::Addr:
25949case Arg::Stack:
25950case Arg::CallArg:
25951#if CPU(X86) || CPU(X86_64)
25952OPGEN_RETURN(true);
25953#endif
25954break;
25955break;
25956default:
25957break;
25958}
25959break;
25960case Arg::Addr:
25961case Arg::Stack:
25962case Arg::CallArg:
25963break;
25964default:
25965break;
25966}
25967break;
25968default:
25969break;
25970}
25971break;
25972default:
25973break;
25974}
25975break;
25976case Opcode::BranchSub64:
25977switch (argIndex) {
25978case 0:
25979OPGEN_RETURN(false);
25980break;
25981case 1:
25982OPGEN_RETURN(false);
25983break;
25984case 2:
25985OPGEN_RETURN(false);
25986break;
25987default:
25988break;
25989}
25990break;
25991case Opcode::BranchNeg32:
25992switch (argIndex) {
25993case 0:
25994OPGEN_RETURN(false);
25995break;
25996case 1:
25997OPGEN_RETURN(false);
25998break;
25999default:
26000break;
26001}
26002break;
26003case Opcode::BranchNeg64:
26004switch (argIndex) {
26005case 0:
26006OPGEN_RETURN(false);
26007break;
26008case 1:
26009OPGEN_RETURN(false);
26010break;
26011default:
26012break;
26013}
26014break;
26015case Opcode::MoveConditionally32:
26016switch (argIndex) {
26017case 0:
26018OPGEN_RETURN(false);
26019break;
26020case 1:
26021OPGEN_RETURN(false);
26022break;
26023case 2:
26024OPGEN_RETURN(false);
26025break;
26026case 3:
26027OPGEN_RETURN(false);
26028break;
26029case 4:
26030OPGEN_RETURN(false);
26031break;
26032case 5:
26033OPGEN_RETURN(false);
26034break;
26035default:
26036break;
26037}
26038break;
26039case Opcode::MoveConditionally64:
26040switch (argIndex) {
26041case 0:
26042OPGEN_RETURN(false);
26043break;
26044case 1:
26045OPGEN_RETURN(false);
26046break;
26047case 2:
26048OPGEN_RETURN(false);
26049break;
26050case 3:
26051OPGEN_RETURN(false);
26052break;
26053case 4:
26054OPGEN_RETURN(false);
26055break;
26056case 5:
26057OPGEN_RETURN(false);
26058break;
26059default:
26060break;
26061}
26062break;
26063case Opcode::MoveConditionallyTest32:
26064switch (argIndex) {
26065case 0:
26066OPGEN_RETURN(false);
26067break;
26068case 1:
26069OPGEN_RETURN(false);
26070break;
26071case 2:
26072OPGEN_RETURN(false);
26073break;
26074case 3:
26075OPGEN_RETURN(false);
26076break;
26077case 4:
26078OPGEN_RETURN(false);
26079break;
26080case 5:
26081OPGEN_RETURN(false);
26082break;
26083default:
26084break;
26085}
26086break;
26087case Opcode::MoveConditionallyTest64:
26088switch (argIndex) {
26089case 0:
26090OPGEN_RETURN(false);
26091break;
26092case 1:
26093OPGEN_RETURN(false);
26094break;
26095case 2:
26096OPGEN_RETURN(false);
26097break;
26098case 3:
26099OPGEN_RETURN(false);
26100break;
26101case 4:
26102OPGEN_RETURN(false);
26103break;
26104case 5:
26105OPGEN_RETURN(false);
26106break;
26107default:
26108break;
26109}
26110break;
26111case Opcode::MoveConditionallyDouble:
26112switch (argIndex) {
26113case 0:
26114OPGEN_RETURN(false);
26115break;
26116case 1:
26117OPGEN_RETURN(false);
26118break;
26119case 2:
26120OPGEN_RETURN(false);
26121break;
26122case 3:
26123OPGEN_RETURN(false);
26124break;
26125case 4:
26126OPGEN_RETURN(false);
26127break;
26128case 5:
26129OPGEN_RETURN(false);
26130break;
26131default:
26132break;
26133}
26134break;
26135case Opcode::MoveConditionallyFloat:
26136switch (argIndex) {
26137case 0:
26138OPGEN_RETURN(false);
26139break;
26140case 1:
26141OPGEN_RETURN(false);
26142break;
26143case 2:
26144OPGEN_RETURN(false);
26145break;
26146case 3:
26147OPGEN_RETURN(false);
26148break;
26149case 4:
26150OPGEN_RETURN(false);
26151break;
26152case 5:
26153OPGEN_RETURN(false);
26154break;
26155default:
26156break;
26157}
26158break;
26159case Opcode::MoveDoubleConditionally32:
26160switch (argIndex) {
26161case 0:
26162OPGEN_RETURN(false);
26163break;
26164case 1:
26165switch (args[0].kind()) {
26166case Arg::RelCond:
26167switch (Arg::Addr) {
26168case Arg::Tmp:
26169break;
26170case Arg::Addr:
26171case Arg::Stack:
26172case Arg::CallArg:
26173switch (args[2].kind()) {
26174case Arg::Imm:
26175switch (args[3].kind()) {
26176case Arg::Tmp:
26177switch (args[4].kind()) {
26178case Arg::Tmp:
26179switch (args[5].kind()) {
26180case Arg::Tmp:
26181#if CPU(X86) || CPU(X86_64)
26182OPGEN_RETURN(true);
26183#endif
26184break;
26185break;
26186default:
26187break;
26188}
26189break;
26190default:
26191break;
26192}
26193break;
26194default:
26195break;
26196}
26197break;
26198case Arg::Tmp:
26199switch (args[3].kind()) {
26200case Arg::Tmp:
26201switch (args[4].kind()) {
26202case Arg::Tmp:
26203switch (args[5].kind()) {
26204case Arg::Tmp:
26205#if CPU(X86) || CPU(X86_64)
26206OPGEN_RETURN(true);
26207#endif
26208break;
26209break;
26210default:
26211break;
26212}
26213break;
26214default:
26215break;
26216}
26217break;
26218default:
26219break;
26220}
26221break;
26222default:
26223break;
26224}
26225break;
26226case Arg::Index:
26227break;
26228default:
26229break;
26230}
26231break;
26232default:
26233break;
26234}
26235break;
26236case 2:
26237switch (args[0].kind()) {
26238case Arg::RelCond:
26239switch (args[1].kind()) {
26240case Arg::Tmp:
26241switch (Arg::Addr) {
26242case Arg::Tmp:
26243break;
26244case Arg::Imm:
26245break;
26246case Arg::Addr:
26247case Arg::Stack:
26248case Arg::CallArg:
26249switch (args[3].kind()) {
26250case Arg::Tmp:
26251switch (args[4].kind()) {
26252case Arg::Tmp:
26253switch (args[5].kind()) {
26254case Arg::Tmp:
26255#if CPU(X86) || CPU(X86_64)
26256OPGEN_RETURN(true);
26257#endif
26258break;
26259break;
26260default:
26261break;
26262}
26263break;
26264default:
26265break;
26266}
26267break;
26268default:
26269break;
26270}
26271break;
26272default:
26273break;
26274}
26275break;
26276case Arg::Addr:
26277case Arg::Stack:
26278case Arg::CallArg:
26279break;
26280case Arg::Index:
26281break;
26282default:
26283break;
26284}
26285break;
26286default:
26287break;
26288}
26289break;
26290case 3:
26291OPGEN_RETURN(false);
26292break;
26293case 4:
26294OPGEN_RETURN(false);
26295break;
26296case 5:
26297OPGEN_RETURN(false);
26298break;
26299default:
26300break;
26301}
26302break;
26303case Opcode::MoveDoubleConditionally64:
26304switch (argIndex) {
26305case 0:
26306OPGEN_RETURN(false);
26307break;
26308case 1:
26309switch (args[0].kind()) {
26310case Arg::RelCond:
26311switch (Arg::Addr) {
26312case Arg::Tmp:
26313break;
26314case Arg::Addr:
26315case Arg::Stack:
26316case Arg::CallArg:
26317switch (args[2].kind()) {
26318case Arg::Tmp:
26319switch (args[3].kind()) {
26320case Arg::Tmp:
26321switch (args[4].kind()) {
26322case Arg::Tmp:
26323switch (args[5].kind()) {
26324case Arg::Tmp:
26325#if CPU(X86_64)
26326OPGEN_RETURN(true);
26327#endif
26328break;
26329break;
26330default:
26331break;
26332}
26333break;
26334default:
26335break;
26336}
26337break;
26338default:
26339break;
26340}
26341break;
26342case Arg::Imm:
26343switch (args[3].kind()) {
26344case Arg::Tmp:
26345switch (args[4].kind()) {
26346case Arg::Tmp:
26347switch (args[5].kind()) {
26348case Arg::Tmp:
26349#if CPU(X86_64)
26350OPGEN_RETURN(true);
26351#endif
26352break;
26353break;
26354default:
26355break;
26356}
26357break;
26358default:
26359break;
26360}
26361break;
26362default:
26363break;
26364}
26365break;
26366default:
26367break;
26368}
26369break;
26370case Arg::Index:
26371break;
26372default:
26373break;
26374}
26375break;
26376default:
26377break;
26378}
26379break;
26380case 2:
26381switch (args[0].kind()) {
26382case Arg::RelCond:
26383switch (args[1].kind()) {
26384case Arg::Tmp:
26385switch (Arg::Addr) {
26386case Arg::Tmp:
26387break;
26388case Arg::Imm:
26389break;
26390case Arg::Addr:
26391case Arg::Stack:
26392case Arg::CallArg:
26393switch (args[3].kind()) {
26394case Arg::Tmp:
26395switch (args[4].kind()) {
26396case Arg::Tmp:
26397switch (args[5].kind()) {
26398case Arg::Tmp:
26399#if CPU(X86_64)
26400OPGEN_RETURN(true);
26401#endif
26402break;
26403break;
26404default:
26405break;
26406}
26407break;
26408default:
26409break;
26410}
26411break;
26412default:
26413break;
26414}
26415break;
26416default:
26417break;
26418}
26419break;
26420case Arg::Addr:
26421case Arg::Stack:
26422case Arg::CallArg:
26423break;
26424case Arg::Index:
26425break;
26426default:
26427break;
26428}
26429break;
26430default:
26431break;
26432}
26433break;
26434case 3:
26435OPGEN_RETURN(false);
26436break;
26437case 4:
26438OPGEN_RETURN(false);
26439break;
26440case 5:
26441OPGEN_RETURN(false);
26442break;
26443default:
26444break;
26445}
26446break;
26447case Opcode::MoveDoubleConditionallyTest32:
26448switch (argIndex) {
26449case 0:
26450OPGEN_RETURN(false);
26451break;
26452case 1:
26453switch (args[0].kind()) {
26454case Arg::ResCond:
26455switch (Arg::Addr) {
26456case Arg::Tmp:
26457break;
26458case Arg::Addr:
26459case Arg::Stack:
26460case Arg::CallArg:
26461switch (args[2].kind()) {
26462case Arg::Imm:
26463switch (args[3].kind()) {
26464case Arg::Tmp:
26465switch (args[4].kind()) {
26466case Arg::Tmp:
26467switch (args[5].kind()) {
26468case Arg::Tmp:
26469#if CPU(X86) || CPU(X86_64)
26470OPGEN_RETURN(true);
26471#endif
26472break;
26473break;
26474default:
26475break;
26476}
26477break;
26478default:
26479break;
26480}
26481break;
26482default:
26483break;
26484}
26485break;
26486default:
26487break;
26488}
26489break;
26490case Arg::Index:
26491break;
26492default:
26493break;
26494}
26495break;
26496default:
26497break;
26498}
26499break;
26500case 2:
26501OPGEN_RETURN(false);
26502break;
26503case 3:
26504OPGEN_RETURN(false);
26505break;
26506case 4:
26507OPGEN_RETURN(false);
26508break;
26509case 5:
26510OPGEN_RETURN(false);
26511break;
26512default:
26513break;
26514}
26515break;
26516case Opcode::MoveDoubleConditionallyTest64:
26517switch (argIndex) {
26518case 0:
26519OPGEN_RETURN(false);
26520break;
26521case 1:
26522switch (args[0].kind()) {
26523case Arg::ResCond:
26524switch (Arg::Addr) {
26525case Arg::Tmp:
26526break;
26527case Arg::Addr:
26528case Arg::Stack:
26529case Arg::CallArg:
26530switch (args[2].kind()) {
26531case Arg::Imm:
26532switch (args[3].kind()) {
26533case Arg::Tmp:
26534switch (args[4].kind()) {
26535case Arg::Tmp:
26536switch (args[5].kind()) {
26537case Arg::Tmp:
26538#if CPU(X86_64)
26539OPGEN_RETURN(true);
26540#endif
26541break;
26542break;
26543default:
26544break;
26545}
26546break;
26547default:
26548break;
26549}
26550break;
26551default:
26552break;
26553}
26554break;
26555case Arg::Tmp:
26556switch (args[3].kind()) {
26557case Arg::Tmp:
26558switch (args[4].kind()) {
26559case Arg::Tmp:
26560switch (args[5].kind()) {
26561case Arg::Tmp:
26562#if CPU(X86_64)
26563OPGEN_RETURN(true);
26564#endif
26565break;
26566break;
26567default:
26568break;
26569}
26570break;
26571default:
26572break;
26573}
26574break;
26575default:
26576break;
26577}
26578break;
26579default:
26580break;
26581}
26582break;
26583case Arg::Index:
26584break;
26585default:
26586break;
26587}
26588break;
26589default:
26590break;
26591}
26592break;
26593case 2:
26594OPGEN_RETURN(false);
26595break;
26596case 3:
26597OPGEN_RETURN(false);
26598break;
26599case 4:
26600OPGEN_RETURN(false);
26601break;
26602case 5:
26603OPGEN_RETURN(false);
26604break;
26605default:
26606break;
26607}
26608break;
26609case Opcode::MoveDoubleConditionallyDouble:
26610switch (argIndex) {
26611case 0:
26612OPGEN_RETURN(false);
26613break;
26614case 1:
26615OPGEN_RETURN(false);
26616break;
26617case 2:
26618OPGEN_RETURN(false);
26619break;
26620case 3:
26621OPGEN_RETURN(false);
26622break;
26623case 4:
26624OPGEN_RETURN(false);
26625break;
26626case 5:
26627OPGEN_RETURN(false);
26628break;
26629default:
26630break;
26631}
26632break;
26633case Opcode::MoveDoubleConditionallyFloat:
26634switch (argIndex) {
26635case 0:
26636OPGEN_RETURN(false);
26637break;
26638case 1:
26639OPGEN_RETURN(false);
26640break;
26641case 2:
26642OPGEN_RETURN(false);
26643break;
26644case 3:
26645OPGEN_RETURN(false);
26646break;
26647case 4:
26648OPGEN_RETURN(false);
26649break;
26650case 5:
26651OPGEN_RETURN(false);
26652break;
26653default:
26654break;
26655}
26656break;
26657case Opcode::MemoryFence:
26658switch (argIndex) {
26659default:
26660break;
26661}
26662break;
26663case Opcode::StoreFence:
26664switch (argIndex) {
26665default:
26666break;
26667}
26668break;
26669case Opcode::LoadFence:
26670switch (argIndex) {
26671default:
26672break;
26673}
26674break;
26675case Opcode::Jump:
26676switch (argIndex) {
26677default:
26678break;
26679}
26680break;
26681case Opcode::RetVoid:
26682switch (argIndex) {
26683default:
26684break;
26685}
26686break;
26687case Opcode::Ret32:
26688switch (argIndex) {
26689case 0:
26690OPGEN_RETURN(false);
26691break;
26692default:
26693break;
26694}
26695break;
26696case Opcode::Ret64:
26697switch (argIndex) {
26698case 0:
26699OPGEN_RETURN(false);
26700break;
26701default:
26702break;
26703}
26704break;
26705case Opcode::RetFloat:
26706switch (argIndex) {
26707case 0:
26708OPGEN_RETURN(false);
26709break;
26710default:
26711break;
26712}
26713break;
26714case Opcode::RetDouble:
26715switch (argIndex) {
26716case 0:
26717OPGEN_RETURN(false);
26718break;
26719default:
26720break;
26721}
26722break;
26723case Opcode::Oops:
26724switch (argIndex) {
26725default:
26726break;
26727}
26728break;
26729case Opcode::EntrySwitch:
26730OPGEN_RETURN(EntrySwitchCustom::admitsStack(*this, argIndex));
26731break;
26732case Opcode::Shuffle:
26733OPGEN_RETURN(ShuffleCustom::admitsStack(*this, argIndex));
26734break;
26735case Opcode::Patch:
26736OPGEN_RETURN(PatchCustom::admitsStack(*this, argIndex));
26737break;
26738case Opcode::CCall:
26739OPGEN_RETURN(CCallCustom::admitsStack(*this, argIndex));
26740break;
26741case Opcode::ColdCCall:
26742OPGEN_RETURN(ColdCCallCustom::admitsStack(*this, argIndex));
26743break;
26744case Opcode::WasmBoundsCheck:
26745OPGEN_RETURN(WasmBoundsCheckCustom::admitsStack(*this, argIndex));
26746break;
26747default:
26748break;
26749}
26750return false;
26751}
26752bool Inst::admitsExtendedOffsetAddr(unsigned argIndex)
26753{
26754switch (kind.opcode) {
26755case Opcode::EntrySwitch:
26756OPGEN_RETURN(EntrySwitchCustom::admitsExtendedOffsetAddr(*this, argIndex));
26757break;
26758case Opcode::Shuffle:
26759OPGEN_RETURN(ShuffleCustom::admitsExtendedOffsetAddr(*this, argIndex));
26760break;
26761case Opcode::Patch:
26762OPGEN_RETURN(PatchCustom::admitsExtendedOffsetAddr(*this, argIndex));
26763break;
26764case Opcode::CCall:
26765OPGEN_RETURN(CCallCustom::admitsExtendedOffsetAddr(*this, argIndex));
26766break;
26767case Opcode::ColdCCall:
26768OPGEN_RETURN(ColdCCallCustom::admitsExtendedOffsetAddr(*this, argIndex));
26769break;
26770case Opcode::WasmBoundsCheck:
26771OPGEN_RETURN(WasmBoundsCheckCustom::admitsExtendedOffsetAddr(*this, argIndex));
26772break;
26773default:
26774break;
26775}
26776return false;
26777}
26778bool Inst::isTerminal()
26779{
26780switch (kind.opcode) {
26781case Opcode::BranchAtomicStrongCAS8:
26782case Opcode::BranchAtomicStrongCAS16:
26783case Opcode::BranchAtomicStrongCAS32:
26784case Opcode::BranchAtomicStrongCAS64:
26785case Opcode::Branch8:
26786case Opcode::Branch32:
26787case Opcode::Branch64:
26788case Opcode::BranchTest8:
26789case Opcode::BranchTest32:
26790case Opcode::BranchTest64:
26791case Opcode::BranchDouble:
26792case Opcode::BranchFloat:
26793case Opcode::BranchAdd32:
26794case Opcode::BranchAdd64:
26795case Opcode::BranchMul32:
26796case Opcode::BranchMul64:
26797case Opcode::BranchSub32:
26798case Opcode::BranchSub64:
26799case Opcode::BranchNeg32:
26800case Opcode::BranchNeg64:
26801case Opcode::Jump:
26802case Opcode::RetVoid:
26803case Opcode::Ret32:
26804case Opcode::Ret64:
26805case Opcode::RetFloat:
26806case Opcode::RetDouble:
26807case Opcode::Oops:
26808return true;
26809case Opcode::EntrySwitch:
26810return EntrySwitchCustom::isTerminal(*this);
26811case Opcode::Shuffle:
26812return ShuffleCustom::isTerminal(*this);
26813case Opcode::Patch:
26814return PatchCustom::isTerminal(*this);
26815case Opcode::CCall:
26816return CCallCustom::isTerminal(*this);
26817case Opcode::ColdCCall:
26818return ColdCCallCustom::isTerminal(*this);
26819case Opcode::WasmBoundsCheck:
26820return WasmBoundsCheckCustom::isTerminal(*this);
26821default:
26822return false;
26823}
26824}
26825bool Inst::hasNonArgNonControlEffects()
26826{
26827if (kind.effects)
26828return true;
26829switch (kind.opcode) {
26830case Opcode::LoadAcq8:
26831case Opcode::StoreRel8:
26832case Opcode::LoadAcq8SignedExtendTo32:
26833case Opcode::LoadAcq16:
26834case Opcode::LoadAcq16SignedExtendTo32:
26835case Opcode::StoreRel16:
26836case Opcode::LoadAcq32:
26837case Opcode::StoreRel32:
26838case Opcode::LoadAcq64:
26839case Opcode::StoreRel64:
26840case Opcode::Xchg8:
26841case Opcode::Xchg16:
26842case Opcode::Xchg32:
26843case Opcode::Xchg64:
26844case Opcode::AtomicStrongCAS8:
26845case Opcode::AtomicStrongCAS16:
26846case Opcode::AtomicStrongCAS32:
26847case Opcode::AtomicStrongCAS64:
26848case Opcode::BranchAtomicStrongCAS8:
26849case Opcode::BranchAtomicStrongCAS16:
26850case Opcode::BranchAtomicStrongCAS32:
26851case Opcode::BranchAtomicStrongCAS64:
26852case Opcode::AtomicAdd8:
26853case Opcode::AtomicAdd16:
26854case Opcode::AtomicAdd32:
26855case Opcode::AtomicAdd64:
26856case Opcode::AtomicSub8:
26857case Opcode::AtomicSub16:
26858case Opcode::AtomicSub32:
26859case Opcode::AtomicSub64:
26860case Opcode::AtomicAnd8:
26861case Opcode::AtomicAnd16:
26862case Opcode::AtomicAnd32:
26863case Opcode::AtomicAnd64:
26864case Opcode::AtomicOr8:
26865case Opcode::AtomicOr16:
26866case Opcode::AtomicOr32:
26867case Opcode::AtomicOr64:
26868case Opcode::AtomicXor8:
26869case Opcode::AtomicXor16:
26870case Opcode::AtomicXor32:
26871case Opcode::AtomicXor64:
26872case Opcode::AtomicNeg8:
26873case Opcode::AtomicNeg16:
26874case Opcode::AtomicNeg32:
26875case Opcode::AtomicNeg64:
26876case Opcode::AtomicNot8:
26877case Opcode::AtomicNot16:
26878case Opcode::AtomicNot32:
26879case Opcode::AtomicNot64:
26880case Opcode::AtomicXchgAdd8:
26881case Opcode::AtomicXchgAdd16:
26882case Opcode::AtomicXchgAdd32:
26883case Opcode::AtomicXchgAdd64:
26884case Opcode::AtomicXchg8:
26885case Opcode::AtomicXchg16:
26886case Opcode::AtomicXchg32:
26887case Opcode::AtomicXchg64:
26888case Opcode::LoadLink8:
26889case Opcode::LoadLinkAcq8:
26890case Opcode::StoreCond8:
26891case Opcode::StoreCondRel8:
26892case Opcode::LoadLink16:
26893case Opcode::LoadLinkAcq16:
26894case Opcode::StoreCond16:
26895case Opcode::StoreCondRel16:
26896case Opcode::LoadLink32:
26897case Opcode::LoadLinkAcq32:
26898case Opcode::StoreCond32:
26899case Opcode::StoreCondRel32:
26900case Opcode::LoadLink64:
26901case Opcode::LoadLinkAcq64:
26902case Opcode::StoreCond64:
26903case Opcode::StoreCondRel64:
26904case Opcode::MemoryFence:
26905case Opcode::StoreFence:
26906case Opcode::LoadFence:
26907return true;
26908case Opcode::EntrySwitch:
26909return EntrySwitchCustom::hasNonArgNonControlEffects(*this);
26910case Opcode::Shuffle:
26911return ShuffleCustom::hasNonArgNonControlEffects(*this);
26912case Opcode::Patch:
26913return PatchCustom::hasNonArgNonControlEffects(*this);
26914case Opcode::CCall:
26915return CCallCustom::hasNonArgNonControlEffects(*this);
26916case Opcode::ColdCCall:
26917return ColdCCallCustom::hasNonArgNonControlEffects(*this);
26918case Opcode::WasmBoundsCheck:
26919return WasmBoundsCheckCustom::hasNonArgNonControlEffects(*this);
26920default:
26921return false;
26922}
26923}
26924bool Inst::hasNonArgEffects()
26925{
26926if (kind.effects)
26927return true;
26928switch (kind.opcode) {
26929case Opcode::LoadAcq8:
26930case Opcode::StoreRel8:
26931case Opcode::LoadAcq8SignedExtendTo32:
26932case Opcode::LoadAcq16:
26933case Opcode::LoadAcq16SignedExtendTo32:
26934case Opcode::StoreRel16:
26935case Opcode::LoadAcq32:
26936case Opcode::StoreRel32:
26937case Opcode::LoadAcq64:
26938case Opcode::StoreRel64:
26939case Opcode::Xchg8:
26940case Opcode::Xchg16:
26941case Opcode::Xchg32:
26942case Opcode::Xchg64:
26943case Opcode::AtomicStrongCAS8:
26944case Opcode::AtomicStrongCAS16:
26945case Opcode::AtomicStrongCAS32:
26946case Opcode::AtomicStrongCAS64:
26947case Opcode::BranchAtomicStrongCAS8:
26948case Opcode::BranchAtomicStrongCAS16:
26949case Opcode::BranchAtomicStrongCAS32:
26950case Opcode::BranchAtomicStrongCAS64:
26951case Opcode::AtomicAdd8:
26952case Opcode::AtomicAdd16:
26953case Opcode::AtomicAdd32:
26954case Opcode::AtomicAdd64:
26955case Opcode::AtomicSub8:
26956case Opcode::AtomicSub16:
26957case Opcode::AtomicSub32:
26958case Opcode::AtomicSub64:
26959case Opcode::AtomicAnd8:
26960case Opcode::AtomicAnd16:
26961case Opcode::AtomicAnd32:
26962case Opcode::AtomicAnd64:
26963case Opcode::AtomicOr8:
26964case Opcode::AtomicOr16:
26965case Opcode::AtomicOr32:
26966case Opcode::AtomicOr64:
26967case Opcode::AtomicXor8:
26968case Opcode::AtomicXor16:
26969case Opcode::AtomicXor32:
26970case Opcode::AtomicXor64:
26971case Opcode::AtomicNeg8:
26972case Opcode::AtomicNeg16:
26973case Opcode::AtomicNeg32:
26974case Opcode::AtomicNeg64:
26975case Opcode::AtomicNot8:
26976case Opcode::AtomicNot16:
26977case Opcode::AtomicNot32:
26978case Opcode::AtomicNot64:
26979case Opcode::AtomicXchgAdd8:
26980case Opcode::AtomicXchgAdd16:
26981case Opcode::AtomicXchgAdd32:
26982case Opcode::AtomicXchgAdd64:
26983case Opcode::AtomicXchg8:
26984case Opcode::AtomicXchg16:
26985case Opcode::AtomicXchg32:
26986case Opcode::AtomicXchg64:
26987case Opcode::LoadLink8:
26988case Opcode::LoadLinkAcq8:
26989case Opcode::StoreCond8:
26990case Opcode::StoreCondRel8:
26991case Opcode::LoadLink16:
26992case Opcode::LoadLinkAcq16:
26993case Opcode::StoreCond16:
26994case Opcode::StoreCondRel16:
26995case Opcode::LoadLink32:
26996case Opcode::LoadLinkAcq32:
26997case Opcode::StoreCond32:
26998case Opcode::StoreCondRel32:
26999case Opcode::LoadLink64:
27000case Opcode::LoadLinkAcq64:
27001case Opcode::StoreCond64:
27002case Opcode::StoreCondRel64:
27003case Opcode::Branch8:
27004case Opcode::Branch32:
27005case Opcode::Branch64:
27006case Opcode::BranchTest8:
27007case Opcode::BranchTest32:
27008case Opcode::BranchTest64:
27009case Opcode::BranchDouble:
27010case Opcode::BranchFloat:
27011case Opcode::BranchAdd32:
27012case Opcode::BranchAdd64:
27013case Opcode::BranchMul32:
27014case Opcode::BranchMul64:
27015case Opcode::BranchSub32:
27016case Opcode::BranchSub64:
27017case Opcode::BranchNeg32:
27018case Opcode::BranchNeg64:
27019case Opcode::MemoryFence:
27020case Opcode::StoreFence:
27021case Opcode::LoadFence:
27022case Opcode::Jump:
27023case Opcode::RetVoid:
27024case Opcode::Ret32:
27025case Opcode::Ret64:
27026case Opcode::RetFloat:
27027case Opcode::RetDouble:
27028case Opcode::Oops:
27029return true;
27030case Opcode::EntrySwitch:
27031return EntrySwitchCustom::hasNonArgEffects(*this);
27032case Opcode::Shuffle:
27033return ShuffleCustom::hasNonArgEffects(*this);
27034case Opcode::Patch:
27035return PatchCustom::hasNonArgEffects(*this);
27036case Opcode::CCall:
27037return CCallCustom::hasNonArgEffects(*this);
27038case Opcode::ColdCCall:
27039return ColdCCallCustom::hasNonArgEffects(*this);
27040case Opcode::WasmBoundsCheck:
27041return WasmBoundsCheckCustom::hasNonArgEffects(*this);
27042default:
27043return false;
27044}
27045}
27046CCallHelpers::Jump Inst::generate(CCallHelpers& jit, GenerationContext& context)
27047{
27048UNUSED_PARAM(jit);
27049UNUSED_PARAM(context);
27050CCallHelpers::Jump result;
27051switch (this->kind.opcode) {
27052case Opcode::Nop:
27053jit.nop();
27054OPGEN_RETURN(result);
27055break;
27056break;
27057case Opcode::Add32:
27058switch (this->args.size()) {
27059case 3:
27060switch (this->args[0].kind()) {
27061case Arg::Imm:
27062jit.add32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
27063OPGEN_RETURN(result);
27064break;
27065break;
27066case Arg::Tmp:
27067jit.add32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27068OPGEN_RETURN(result);
27069break;
27070break;
27071default:
27072break;
27073}
27074break;
27075case 2:
27076switch (this->args[0].kind()) {
27077case Arg::Tmp:
27078switch (this->args[1].kind()) {
27079case Arg::Tmp:
27080jit.add32(args[0].gpr(), args[1].gpr());
27081OPGEN_RETURN(result);
27082break;
27083break;
27084case Arg::Addr:
27085case Arg::Stack:
27086case Arg::CallArg:
27087#if CPU(X86) || CPU(X86_64)
27088jit.add32(args[0].gpr(), args[1].asAddress());
27089OPGEN_RETURN(result);
27090#endif
27091break;
27092break;
27093case Arg::Index:
27094#if CPU(X86) || CPU(X86_64)
27095jit.add32(args[0].gpr(), args[1].asBaseIndex());
27096OPGEN_RETURN(result);
27097#endif
27098break;
27099break;
27100default:
27101break;
27102}
27103break;
27104case Arg::Imm:
27105switch (this->args[1].kind()) {
27106case Arg::Addr:
27107case Arg::Stack:
27108case Arg::CallArg:
27109#if CPU(X86) || CPU(X86_64)
27110jit.add32(args[0].asTrustedImm32(), args[1].asAddress());
27111OPGEN_RETURN(result);
27112#endif
27113break;
27114break;
27115case Arg::Index:
27116#if CPU(X86) || CPU(X86_64)
27117jit.add32(args[0].asTrustedImm32(), args[1].asBaseIndex());
27118OPGEN_RETURN(result);
27119#endif
27120break;
27121break;
27122case Arg::Tmp:
27123jit.add32(args[0].asTrustedImm32(), args[1].gpr());
27124OPGEN_RETURN(result);
27125break;
27126break;
27127default:
27128break;
27129}
27130break;
27131case Arg::Addr:
27132case Arg::Stack:
27133case Arg::CallArg:
27134#if CPU(X86) || CPU(X86_64)
27135jit.add32(args[0].asAddress(), args[1].gpr());
27136OPGEN_RETURN(result);
27137#endif
27138break;
27139break;
27140case Arg::Index:
27141#if CPU(X86) || CPU(X86_64)
27142jit.add32(args[0].asBaseIndex(), args[1].gpr());
27143OPGEN_RETURN(result);
27144#endif
27145break;
27146break;
27147default:
27148break;
27149}
27150break;
27151default:
27152break;
27153}
27154break;
27155case Opcode::Add8:
27156switch (this->args[0].kind()) {
27157case Arg::Imm:
27158switch (this->args[1].kind()) {
27159case Arg::Addr:
27160case Arg::Stack:
27161case Arg::CallArg:
27162#if CPU(X86) || CPU(X86_64)
27163jit.add8(args[0].asTrustedImm32(), args[1].asAddress());
27164OPGEN_RETURN(result);
27165#endif
27166break;
27167break;
27168case Arg::Index:
27169#if CPU(X86) || CPU(X86_64)
27170jit.add8(args[0].asTrustedImm32(), args[1].asBaseIndex());
27171OPGEN_RETURN(result);
27172#endif
27173break;
27174break;
27175default:
27176break;
27177}
27178break;
27179case Arg::Tmp:
27180switch (this->args[1].kind()) {
27181case Arg::Addr:
27182case Arg::Stack:
27183case Arg::CallArg:
27184#if CPU(X86) || CPU(X86_64)
27185jit.add8(args[0].gpr(), args[1].asAddress());
27186OPGEN_RETURN(result);
27187#endif
27188break;
27189break;
27190case Arg::Index:
27191#if CPU(X86) || CPU(X86_64)
27192jit.add8(args[0].gpr(), args[1].asBaseIndex());
27193OPGEN_RETURN(result);
27194#endif
27195break;
27196break;
27197default:
27198break;
27199}
27200break;
27201default:
27202break;
27203}
27204break;
27205case Opcode::Add16:
27206switch (this->args[0].kind()) {
27207case Arg::Imm:
27208switch (this->args[1].kind()) {
27209case Arg::Addr:
27210case Arg::Stack:
27211case Arg::CallArg:
27212#if CPU(X86) || CPU(X86_64)
27213jit.add16(args[0].asTrustedImm32(), args[1].asAddress());
27214OPGEN_RETURN(result);
27215#endif
27216break;
27217break;
27218case Arg::Index:
27219#if CPU(X86) || CPU(X86_64)
27220jit.add16(args[0].asTrustedImm32(), args[1].asBaseIndex());
27221OPGEN_RETURN(result);
27222#endif
27223break;
27224break;
27225default:
27226break;
27227}
27228break;
27229case Arg::Tmp:
27230switch (this->args[1].kind()) {
27231case Arg::Addr:
27232case Arg::Stack:
27233case Arg::CallArg:
27234#if CPU(X86) || CPU(X86_64)
27235jit.add16(args[0].gpr(), args[1].asAddress());
27236OPGEN_RETURN(result);
27237#endif
27238break;
27239break;
27240case Arg::Index:
27241#if CPU(X86) || CPU(X86_64)
27242jit.add16(args[0].gpr(), args[1].asBaseIndex());
27243OPGEN_RETURN(result);
27244#endif
27245break;
27246break;
27247default:
27248break;
27249}
27250break;
27251default:
27252break;
27253}
27254break;
27255case Opcode::Add64:
27256switch (this->args.size()) {
27257case 2:
27258switch (this->args[0].kind()) {
27259case Arg::Tmp:
27260switch (this->args[1].kind()) {
27261case Arg::Tmp:
27262#if CPU(X86_64) || CPU(ARM64)
27263jit.add64(args[0].gpr(), args[1].gpr());
27264OPGEN_RETURN(result);
27265#endif
27266break;
27267break;
27268case Arg::Addr:
27269case Arg::Stack:
27270case Arg::CallArg:
27271#if CPU(X86_64)
27272jit.add64(args[0].gpr(), args[1].asAddress());
27273OPGEN_RETURN(result);
27274#endif
27275break;
27276break;
27277case Arg::Index:
27278#if CPU(X86_64)
27279jit.add64(args[0].gpr(), args[1].asBaseIndex());
27280OPGEN_RETURN(result);
27281#endif
27282break;
27283break;
27284default:
27285break;
27286}
27287break;
27288case Arg::Imm:
27289switch (this->args[1].kind()) {
27290case Arg::Addr:
27291case Arg::Stack:
27292case Arg::CallArg:
27293#if CPU(X86_64)
27294jit.add64(args[0].asTrustedImm32(), args[1].asAddress());
27295OPGEN_RETURN(result);
27296#endif
27297break;
27298break;
27299case Arg::Index:
27300#if CPU(X86_64)
27301jit.add64(args[0].asTrustedImm32(), args[1].asBaseIndex());
27302OPGEN_RETURN(result);
27303#endif
27304break;
27305break;
27306case Arg::Tmp:
27307#if CPU(X86_64) || CPU(ARM64)
27308jit.add64(args[0].asTrustedImm32(), args[1].gpr());
27309OPGEN_RETURN(result);
27310#endif
27311break;
27312break;
27313default:
27314break;
27315}
27316break;
27317case Arg::Addr:
27318case Arg::Stack:
27319case Arg::CallArg:
27320#if CPU(X86_64)
27321jit.add64(args[0].asAddress(), args[1].gpr());
27322OPGEN_RETURN(result);
27323#endif
27324break;
27325break;
27326case Arg::Index:
27327#if CPU(X86_64)
27328jit.add64(args[0].asBaseIndex(), args[1].gpr());
27329OPGEN_RETURN(result);
27330#endif
27331break;
27332break;
27333default:
27334break;
27335}
27336break;
27337case 3:
27338switch (this->args[0].kind()) {
27339case Arg::Imm:
27340#if CPU(X86_64) || CPU(ARM64)
27341jit.add64(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
27342OPGEN_RETURN(result);
27343#endif
27344break;
27345break;
27346case Arg::Tmp:
27347#if CPU(X86_64) || CPU(ARM64)
27348jit.add64(args[0].gpr(), args[1].gpr(), args[2].gpr());
27349OPGEN_RETURN(result);
27350#endif
27351break;
27352break;
27353default:
27354break;
27355}
27356break;
27357default:
27358break;
27359}
27360break;
27361case Opcode::AddDouble:
27362switch (this->args.size()) {
27363case 3:
27364switch (this->args[0].kind()) {
27365case Arg::Tmp:
27366switch (this->args[1].kind()) {
27367case Arg::Tmp:
27368jit.addDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
27369OPGEN_RETURN(result);
27370break;
27371break;
27372case Arg::Addr:
27373case Arg::Stack:
27374case Arg::CallArg:
27375#if CPU(X86) || CPU(X86_64)
27376jit.addDouble(args[0].fpr(), args[1].asAddress(), args[2].fpr());
27377OPGEN_RETURN(result);
27378#endif
27379break;
27380break;
27381default:
27382break;
27383}
27384break;
27385case Arg::Addr:
27386case Arg::Stack:
27387case Arg::CallArg:
27388#if CPU(X86) || CPU(X86_64)
27389jit.addDouble(args[0].asAddress(), args[1].fpr(), args[2].fpr());
27390OPGEN_RETURN(result);
27391#endif
27392break;
27393break;
27394case Arg::Index:
27395#if CPU(X86) || CPU(X86_64)
27396jit.addDouble(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
27397OPGEN_RETURN(result);
27398#endif
27399break;
27400break;
27401default:
27402break;
27403}
27404break;
27405case 2:
27406switch (this->args[0].kind()) {
27407case Arg::Tmp:
27408#if CPU(X86) || CPU(X86_64)
27409jit.addDouble(args[0].fpr(), args[1].fpr());
27410OPGEN_RETURN(result);
27411#endif
27412break;
27413break;
27414case Arg::Addr:
27415case Arg::Stack:
27416case Arg::CallArg:
27417#if CPU(X86) || CPU(X86_64)
27418jit.addDouble(args[0].asAddress(), args[1].fpr());
27419OPGEN_RETURN(result);
27420#endif
27421break;
27422break;
27423default:
27424break;
27425}
27426break;
27427default:
27428break;
27429}
27430break;
27431case Opcode::AddFloat:
27432switch (this->args.size()) {
27433case 3:
27434switch (this->args[0].kind()) {
27435case Arg::Tmp:
27436switch (this->args[1].kind()) {
27437case Arg::Tmp:
27438jit.addFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
27439OPGEN_RETURN(result);
27440break;
27441break;
27442case Arg::Addr:
27443case Arg::Stack:
27444case Arg::CallArg:
27445#if CPU(X86) || CPU(X86_64)
27446jit.addFloat(args[0].fpr(), args[1].asAddress(), args[2].fpr());
27447OPGEN_RETURN(result);
27448#endif
27449break;
27450break;
27451default:
27452break;
27453}
27454break;
27455case Arg::Addr:
27456case Arg::Stack:
27457case Arg::CallArg:
27458#if CPU(X86) || CPU(X86_64)
27459jit.addFloat(args[0].asAddress(), args[1].fpr(), args[2].fpr());
27460OPGEN_RETURN(result);
27461#endif
27462break;
27463break;
27464case Arg::Index:
27465#if CPU(X86) || CPU(X86_64)
27466jit.addFloat(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
27467OPGEN_RETURN(result);
27468#endif
27469break;
27470break;
27471default:
27472break;
27473}
27474break;
27475case 2:
27476switch (this->args[0].kind()) {
27477case Arg::Tmp:
27478#if CPU(X86) || CPU(X86_64)
27479jit.addFloat(args[0].fpr(), args[1].fpr());
27480OPGEN_RETURN(result);
27481#endif
27482break;
27483break;
27484case Arg::Addr:
27485case Arg::Stack:
27486case Arg::CallArg:
27487#if CPU(X86) || CPU(X86_64)
27488jit.addFloat(args[0].asAddress(), args[1].fpr());
27489OPGEN_RETURN(result);
27490#endif
27491break;
27492break;
27493default:
27494break;
27495}
27496break;
27497default:
27498break;
27499}
27500break;
27501case Opcode::Sub32:
27502switch (this->args.size()) {
27503case 2:
27504switch (this->args[0].kind()) {
27505case Arg::Tmp:
27506switch (this->args[1].kind()) {
27507case Arg::Tmp:
27508jit.sub32(args[0].gpr(), args[1].gpr());
27509OPGEN_RETURN(result);
27510break;
27511break;
27512case Arg::Addr:
27513case Arg::Stack:
27514case Arg::CallArg:
27515#if CPU(X86) || CPU(X86_64)
27516jit.sub32(args[0].gpr(), args[1].asAddress());
27517OPGEN_RETURN(result);
27518#endif
27519break;
27520break;
27521case Arg::Index:
27522#if CPU(X86) || CPU(X86_64)
27523jit.sub32(args[0].gpr(), args[1].asBaseIndex());
27524OPGEN_RETURN(result);
27525#endif
27526break;
27527break;
27528default:
27529break;
27530}
27531break;
27532case Arg::Imm:
27533switch (this->args[1].kind()) {
27534case Arg::Addr:
27535case Arg::Stack:
27536case Arg::CallArg:
27537#if CPU(X86) || CPU(X86_64)
27538jit.sub32(args[0].asTrustedImm32(), args[1].asAddress());
27539OPGEN_RETURN(result);
27540#endif
27541break;
27542break;
27543case Arg::Index:
27544#if CPU(X86) || CPU(X86_64)
27545jit.sub32(args[0].asTrustedImm32(), args[1].asBaseIndex());
27546OPGEN_RETURN(result);
27547#endif
27548break;
27549break;
27550case Arg::Tmp:
27551jit.sub32(args[0].asTrustedImm32(), args[1].gpr());
27552OPGEN_RETURN(result);
27553break;
27554break;
27555default:
27556break;
27557}
27558break;
27559case Arg::Addr:
27560case Arg::Stack:
27561case Arg::CallArg:
27562#if CPU(X86) || CPU(X86_64)
27563jit.sub32(args[0].asAddress(), args[1].gpr());
27564OPGEN_RETURN(result);
27565#endif
27566break;
27567break;
27568case Arg::Index:
27569#if CPU(X86) || CPU(X86_64)
27570jit.sub32(args[0].asBaseIndex(), args[1].gpr());
27571OPGEN_RETURN(result);
27572#endif
27573break;
27574break;
27575default:
27576break;
27577}
27578break;
27579case 3:
27580#if CPU(ARM64)
27581jit.sub32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27582OPGEN_RETURN(result);
27583#endif
27584break;
27585break;
27586default:
27587break;
27588}
27589break;
27590case Opcode::Sub64:
27591switch (this->args.size()) {
27592case 2:
27593switch (this->args[0].kind()) {
27594case Arg::Tmp:
27595switch (this->args[1].kind()) {
27596case Arg::Tmp:
27597#if CPU(X86_64) || CPU(ARM64)
27598jit.sub64(args[0].gpr(), args[1].gpr());
27599OPGEN_RETURN(result);
27600#endif
27601break;
27602break;
27603case Arg::Addr:
27604case Arg::Stack:
27605case Arg::CallArg:
27606#if CPU(X86_64)
27607jit.sub64(args[0].gpr(), args[1].asAddress());
27608OPGEN_RETURN(result);
27609#endif
27610break;
27611break;
27612case Arg::Index:
27613#if CPU(X86_64)
27614jit.sub64(args[0].gpr(), args[1].asBaseIndex());
27615OPGEN_RETURN(result);
27616#endif
27617break;
27618break;
27619default:
27620break;
27621}
27622break;
27623case Arg::Imm:
27624switch (this->args[1].kind()) {
27625case Arg::Addr:
27626case Arg::Stack:
27627case Arg::CallArg:
27628#if CPU(X86_64)
27629jit.sub64(args[0].asTrustedImm32(), args[1].asAddress());
27630OPGEN_RETURN(result);
27631#endif
27632break;
27633break;
27634case Arg::Index:
27635#if CPU(X86_64)
27636jit.sub64(args[0].asTrustedImm32(), args[1].asBaseIndex());
27637OPGEN_RETURN(result);
27638#endif
27639break;
27640break;
27641case Arg::Tmp:
27642#if CPU(X86_64) || CPU(ARM64)
27643jit.sub64(args[0].asTrustedImm32(), args[1].gpr());
27644OPGEN_RETURN(result);
27645#endif
27646break;
27647break;
27648default:
27649break;
27650}
27651break;
27652case Arg::Addr:
27653case Arg::Stack:
27654case Arg::CallArg:
27655#if CPU(X86_64)
27656jit.sub64(args[0].asAddress(), args[1].gpr());
27657OPGEN_RETURN(result);
27658#endif
27659break;
27660break;
27661case Arg::Index:
27662#if CPU(X86_64)
27663jit.sub64(args[0].asBaseIndex(), args[1].gpr());
27664OPGEN_RETURN(result);
27665#endif
27666break;
27667break;
27668default:
27669break;
27670}
27671break;
27672case 3:
27673#if CPU(ARM64)
27674jit.sub64(args[0].gpr(), args[1].gpr(), args[2].gpr());
27675OPGEN_RETURN(result);
27676#endif
27677break;
27678break;
27679default:
27680break;
27681}
27682break;
27683case Opcode::SubDouble:
27684switch (this->args.size()) {
27685case 3:
27686switch (this->args[1].kind()) {
27687case Arg::Tmp:
27688#if CPU(ARM64)
27689jit.subDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
27690OPGEN_RETURN(result);
27691#endif
27692break;
27693break;
27694case Arg::Addr:
27695case Arg::Stack:
27696case Arg::CallArg:
27697#if CPU(X86) || CPU(X86_64)
27698jit.subDouble(args[0].fpr(), args[1].asAddress(), args[2].fpr());
27699OPGEN_RETURN(result);
27700#endif
27701break;
27702break;
27703case Arg::Index:
27704#if CPU(X86) || CPU(X86_64)
27705jit.subDouble(args[0].fpr(), args[1].asBaseIndex(), args[2].fpr());
27706OPGEN_RETURN(result);
27707#endif
27708break;
27709break;
27710default:
27711break;
27712}
27713break;
27714case 2:
27715switch (this->args[0].kind()) {
27716case Arg::Tmp:
27717#if CPU(X86) || CPU(X86_64)
27718jit.subDouble(args[0].fpr(), args[1].fpr());
27719OPGEN_RETURN(result);
27720#endif
27721break;
27722break;
27723case Arg::Addr:
27724case Arg::Stack:
27725case Arg::CallArg:
27726#if CPU(X86) || CPU(X86_64)
27727jit.subDouble(args[0].asAddress(), args[1].fpr());
27728OPGEN_RETURN(result);
27729#endif
27730break;
27731break;
27732default:
27733break;
27734}
27735break;
27736default:
27737break;
27738}
27739break;
27740case Opcode::SubFloat:
27741switch (this->args.size()) {
27742case 3:
27743switch (this->args[1].kind()) {
27744case Arg::Tmp:
27745#if CPU(ARM64)
27746jit.subFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
27747OPGEN_RETURN(result);
27748#endif
27749break;
27750break;
27751case Arg::Addr:
27752case Arg::Stack:
27753case Arg::CallArg:
27754#if CPU(X86) || CPU(X86_64)
27755jit.subFloat(args[0].fpr(), args[1].asAddress(), args[2].fpr());
27756OPGEN_RETURN(result);
27757#endif
27758break;
27759break;
27760case Arg::Index:
27761#if CPU(X86) || CPU(X86_64)
27762jit.subFloat(args[0].fpr(), args[1].asBaseIndex(), args[2].fpr());
27763OPGEN_RETURN(result);
27764#endif
27765break;
27766break;
27767default:
27768break;
27769}
27770break;
27771case 2:
27772switch (this->args[0].kind()) {
27773case Arg::Tmp:
27774#if CPU(X86) || CPU(X86_64)
27775jit.subFloat(args[0].fpr(), args[1].fpr());
27776OPGEN_RETURN(result);
27777#endif
27778break;
27779break;
27780case Arg::Addr:
27781case Arg::Stack:
27782case Arg::CallArg:
27783#if CPU(X86) || CPU(X86_64)
27784jit.subFloat(args[0].asAddress(), args[1].fpr());
27785OPGEN_RETURN(result);
27786#endif
27787break;
27788break;
27789default:
27790break;
27791}
27792break;
27793default:
27794break;
27795}
27796break;
27797case Opcode::Neg32:
27798switch (this->args[0].kind()) {
27799case Arg::Tmp:
27800jit.neg32(args[0].gpr());
27801OPGEN_RETURN(result);
27802break;
27803break;
27804case Arg::Addr:
27805case Arg::Stack:
27806case Arg::CallArg:
27807#if CPU(X86) || CPU(X86_64)
27808jit.neg32(args[0].asAddress());
27809OPGEN_RETURN(result);
27810#endif
27811break;
27812break;
27813case Arg::Index:
27814#if CPU(X86) || CPU(X86_64)
27815jit.neg32(args[0].asBaseIndex());
27816OPGEN_RETURN(result);
27817#endif
27818break;
27819break;
27820default:
27821break;
27822}
27823break;
27824case Opcode::Neg64:
27825switch (this->args[0].kind()) {
27826case Arg::Tmp:
27827#if CPU(X86_64) || CPU(ARM64)
27828jit.neg64(args[0].gpr());
27829OPGEN_RETURN(result);
27830#endif
27831break;
27832break;
27833case Arg::Addr:
27834case Arg::Stack:
27835case Arg::CallArg:
27836#if CPU(X86_64)
27837jit.neg64(args[0].asAddress());
27838OPGEN_RETURN(result);
27839#endif
27840break;
27841break;
27842case Arg::Index:
27843#if CPU(X86_64)
27844jit.neg64(args[0].asBaseIndex());
27845OPGEN_RETURN(result);
27846#endif
27847break;
27848break;
27849default:
27850break;
27851}
27852break;
27853case Opcode::NegateDouble:
27854#if CPU(ARM64)
27855jit.negateDouble(args[0].fpr(), args[1].fpr());
27856OPGEN_RETURN(result);
27857#endif
27858break;
27859break;
27860case Opcode::NegateFloat:
27861#if CPU(ARM64)
27862jit.negateFloat(args[0].fpr(), args[1].fpr());
27863OPGEN_RETURN(result);
27864#endif
27865break;
27866break;
27867case Opcode::Mul32:
27868switch (this->args.size()) {
27869case 2:
27870switch (this->args[0].kind()) {
27871case Arg::Tmp:
27872jit.mul32(args[0].gpr(), args[1].gpr());
27873OPGEN_RETURN(result);
27874break;
27875break;
27876case Arg::Addr:
27877case Arg::Stack:
27878case Arg::CallArg:
27879#if CPU(X86) || CPU(X86_64)
27880jit.mul32(args[0].asAddress(), args[1].gpr());
27881OPGEN_RETURN(result);
27882#endif
27883break;
27884break;
27885default:
27886break;
27887}
27888break;
27889case 3:
27890switch (this->args[0].kind()) {
27891case Arg::Tmp:
27892switch (this->args[1].kind()) {
27893case Arg::Tmp:
27894jit.mul32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27895OPGEN_RETURN(result);
27896break;
27897break;
27898case Arg::Addr:
27899case Arg::Stack:
27900case Arg::CallArg:
27901#if CPU(X86) || CPU(X86_64)
27902jit.mul32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
27903OPGEN_RETURN(result);
27904#endif
27905break;
27906break;
27907default:
27908break;
27909}
27910break;
27911case Arg::Addr:
27912case Arg::Stack:
27913case Arg::CallArg:
27914#if CPU(X86) || CPU(X86_64)
27915jit.mul32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
27916OPGEN_RETURN(result);
27917#endif
27918break;
27919break;
27920case Arg::Imm:
27921#if CPU(X86) || CPU(X86_64)
27922jit.mul32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
27923OPGEN_RETURN(result);
27924#endif
27925break;
27926break;
27927default:
27928break;
27929}
27930break;
27931default:
27932break;
27933}
27934break;
27935case Opcode::Mul64:
27936switch (this->args.size()) {
27937case 2:
27938#if CPU(X86_64) || CPU(ARM64)
27939jit.mul64(args[0].gpr(), args[1].gpr());
27940OPGEN_RETURN(result);
27941#endif
27942break;
27943break;
27944case 3:
27945jit.mul64(args[0].gpr(), args[1].gpr(), args[2].gpr());
27946OPGEN_RETURN(result);
27947break;
27948break;
27949default:
27950break;
27951}
27952break;
27953case Opcode::MultiplyAdd32:
27954#if CPU(ARM64)
27955jit.multiplyAdd32(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
27956OPGEN_RETURN(result);
27957#endif
27958break;
27959break;
27960case Opcode::MultiplyAdd64:
27961#if CPU(ARM64)
27962jit.multiplyAdd64(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
27963OPGEN_RETURN(result);
27964#endif
27965break;
27966break;
27967case Opcode::MultiplySub32:
27968#if CPU(ARM64)
27969jit.multiplySub32(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
27970OPGEN_RETURN(result);
27971#endif
27972break;
27973break;
27974case Opcode::MultiplySub64:
27975#if CPU(ARM64)
27976jit.multiplySub64(args[0].gpr(), args[1].gpr(), args[2].gpr(), args[3].gpr());
27977OPGEN_RETURN(result);
27978#endif
27979break;
27980break;
27981case Opcode::MultiplyNeg32:
27982#if CPU(ARM64)
27983jit.multiplyNeg32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27984OPGEN_RETURN(result);
27985#endif
27986break;
27987break;
27988case Opcode::MultiplyNeg64:
27989#if CPU(ARM64)
27990jit.multiplyNeg64(args[0].gpr(), args[1].gpr(), args[2].gpr());
27991OPGEN_RETURN(result);
27992#endif
27993break;
27994break;
27995case Opcode::Div32:
27996#if CPU(ARM64)
27997jit.div32(args[0].gpr(), args[1].gpr(), args[2].gpr());
27998OPGEN_RETURN(result);
27999#endif
28000break;
28001break;
28002case Opcode::UDiv32:
28003#if CPU(ARM64)
28004jit.uDiv32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28005OPGEN_RETURN(result);
28006#endif
28007break;
28008break;
28009case Opcode::Div64:
28010#if CPU(ARM64)
28011jit.div64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28012OPGEN_RETURN(result);
28013#endif
28014break;
28015break;
28016case Opcode::UDiv64:
28017#if CPU(ARM64)
28018jit.uDiv64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28019OPGEN_RETURN(result);
28020#endif
28021break;
28022break;
28023case Opcode::MulDouble:
28024switch (this->args.size()) {
28025case 3:
28026switch (this->args[0].kind()) {
28027case Arg::Tmp:
28028switch (this->args[1].kind()) {
28029case Arg::Tmp:
28030jit.mulDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28031OPGEN_RETURN(result);
28032break;
28033break;
28034case Arg::Addr:
28035case Arg::Stack:
28036case Arg::CallArg:
28037#if CPU(X86) || CPU(X86_64)
28038jit.mulDouble(args[0].fpr(), args[1].asAddress(), args[2].fpr());
28039OPGEN_RETURN(result);
28040#endif
28041break;
28042break;
28043default:
28044break;
28045}
28046break;
28047case Arg::Addr:
28048case Arg::Stack:
28049case Arg::CallArg:
28050#if CPU(X86) || CPU(X86_64)
28051jit.mulDouble(args[0].asAddress(), args[1].fpr(), args[2].fpr());
28052OPGEN_RETURN(result);
28053#endif
28054break;
28055break;
28056case Arg::Index:
28057#if CPU(X86) || CPU(X86_64)
28058jit.mulDouble(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
28059OPGEN_RETURN(result);
28060#endif
28061break;
28062break;
28063default:
28064break;
28065}
28066break;
28067case 2:
28068switch (this->args[0].kind()) {
28069case Arg::Tmp:
28070#if CPU(X86) || CPU(X86_64)
28071jit.mulDouble(args[0].fpr(), args[1].fpr());
28072OPGEN_RETURN(result);
28073#endif
28074break;
28075break;
28076case Arg::Addr:
28077case Arg::Stack:
28078case Arg::CallArg:
28079#if CPU(X86) || CPU(X86_64)
28080jit.mulDouble(args[0].asAddress(), args[1].fpr());
28081OPGEN_RETURN(result);
28082#endif
28083break;
28084break;
28085default:
28086break;
28087}
28088break;
28089default:
28090break;
28091}
28092break;
28093case Opcode::MulFloat:
28094switch (this->args.size()) {
28095case 3:
28096switch (this->args[0].kind()) {
28097case Arg::Tmp:
28098switch (this->args[1].kind()) {
28099case Arg::Tmp:
28100jit.mulFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28101OPGEN_RETURN(result);
28102break;
28103break;
28104case Arg::Addr:
28105case Arg::Stack:
28106case Arg::CallArg:
28107#if CPU(X86) || CPU(X86_64)
28108jit.mulFloat(args[0].fpr(), args[1].asAddress(), args[2].fpr());
28109OPGEN_RETURN(result);
28110#endif
28111break;
28112break;
28113default:
28114break;
28115}
28116break;
28117case Arg::Addr:
28118case Arg::Stack:
28119case Arg::CallArg:
28120#if CPU(X86) || CPU(X86_64)
28121jit.mulFloat(args[0].asAddress(), args[1].fpr(), args[2].fpr());
28122OPGEN_RETURN(result);
28123#endif
28124break;
28125break;
28126case Arg::Index:
28127#if CPU(X86) || CPU(X86_64)
28128jit.mulFloat(args[0].asBaseIndex(), args[1].fpr(), args[2].fpr());
28129OPGEN_RETURN(result);
28130#endif
28131break;
28132break;
28133default:
28134break;
28135}
28136break;
28137case 2:
28138switch (this->args[0].kind()) {
28139case Arg::Tmp:
28140#if CPU(X86) || CPU(X86_64)
28141jit.mulFloat(args[0].fpr(), args[1].fpr());
28142OPGEN_RETURN(result);
28143#endif
28144break;
28145break;
28146case Arg::Addr:
28147case Arg::Stack:
28148case Arg::CallArg:
28149#if CPU(X86) || CPU(X86_64)
28150jit.mulFloat(args[0].asAddress(), args[1].fpr());
28151OPGEN_RETURN(result);
28152#endif
28153break;
28154break;
28155default:
28156break;
28157}
28158break;
28159default:
28160break;
28161}
28162break;
28163case Opcode::DivDouble:
28164switch (this->args.size()) {
28165case 3:
28166#if CPU(ARM64)
28167jit.divDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28168OPGEN_RETURN(result);
28169#endif
28170break;
28171break;
28172case 2:
28173switch (this->args[0].kind()) {
28174case Arg::Tmp:
28175#if CPU(X86) || CPU(X86_64)
28176jit.divDouble(args[0].fpr(), args[1].fpr());
28177OPGEN_RETURN(result);
28178#endif
28179break;
28180break;
28181case Arg::Addr:
28182case Arg::Stack:
28183case Arg::CallArg:
28184#if CPU(X86) || CPU(X86_64)
28185jit.divDouble(args[0].asAddress(), args[1].fpr());
28186OPGEN_RETURN(result);
28187#endif
28188break;
28189break;
28190default:
28191break;
28192}
28193break;
28194default:
28195break;
28196}
28197break;
28198case Opcode::DivFloat:
28199switch (this->args.size()) {
28200case 3:
28201#if CPU(ARM64)
28202jit.divFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28203OPGEN_RETURN(result);
28204#endif
28205break;
28206break;
28207case 2:
28208switch (this->args[0].kind()) {
28209case Arg::Tmp:
28210#if CPU(X86) || CPU(X86_64)
28211jit.divFloat(args[0].fpr(), args[1].fpr());
28212OPGEN_RETURN(result);
28213#endif
28214break;
28215break;
28216case Arg::Addr:
28217case Arg::Stack:
28218case Arg::CallArg:
28219#if CPU(X86) || CPU(X86_64)
28220jit.divFloat(args[0].asAddress(), args[1].fpr());
28221OPGEN_RETURN(result);
28222#endif
28223break;
28224break;
28225default:
28226break;
28227}
28228break;
28229default:
28230break;
28231}
28232break;
28233case Opcode::X86ConvertToDoubleWord32:
28234#if CPU(X86) || CPU(X86_64)
28235jit.x86ConvertToDoubleWord32(args[0].gpr(), args[1].gpr());
28236OPGEN_RETURN(result);
28237#endif
28238break;
28239break;
28240case Opcode::X86ConvertToQuadWord64:
28241#if CPU(X86_64)
28242jit.x86ConvertToQuadWord64(args[0].gpr(), args[1].gpr());
28243OPGEN_RETURN(result);
28244#endif
28245break;
28246break;
28247case Opcode::X86Div32:
28248#if CPU(X86) || CPU(X86_64)
28249jit.x86Div32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28250OPGEN_RETURN(result);
28251#endif
28252break;
28253break;
28254case Opcode::X86UDiv32:
28255#if CPU(X86) || CPU(X86_64)
28256jit.x86UDiv32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28257OPGEN_RETURN(result);
28258#endif
28259break;
28260break;
28261case Opcode::X86Div64:
28262#if CPU(X86_64)
28263jit.x86Div64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28264OPGEN_RETURN(result);
28265#endif
28266break;
28267break;
28268case Opcode::X86UDiv64:
28269#if CPU(X86_64)
28270jit.x86UDiv64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28271OPGEN_RETURN(result);
28272#endif
28273break;
28274break;
28275case Opcode::Lea32:
28276switch (this->args[0].kind()) {
28277case Arg::Addr:
28278case Arg::Stack:
28279case Arg::CallArg:
28280jit.lea32(args[0].asAddress(), args[1].gpr());
28281OPGEN_RETURN(result);
28282break;
28283break;
28284case Arg::Index:
28285#if CPU(X86) || CPU(X86_64)
28286jit.x86Lea32(args[0].asBaseIndex(), args[1].gpr());
28287OPGEN_RETURN(result);
28288#endif
28289break;
28290break;
28291default:
28292break;
28293}
28294break;
28295case Opcode::Lea64:
28296switch (this->args[0].kind()) {
28297case Arg::Addr:
28298case Arg::Stack:
28299case Arg::CallArg:
28300jit.lea64(args[0].asAddress(), args[1].gpr());
28301OPGEN_RETURN(result);
28302break;
28303break;
28304case Arg::Index:
28305#if CPU(X86) || CPU(X86_64)
28306jit.x86Lea64(args[0].asBaseIndex(), args[1].gpr());
28307OPGEN_RETURN(result);
28308#endif
28309break;
28310break;
28311default:
28312break;
28313}
28314break;
28315case Opcode::And32:
28316switch (this->args.size()) {
28317case 3:
28318switch (this->args[0].kind()) {
28319case Arg::Tmp:
28320switch (this->args[1].kind()) {
28321case Arg::Tmp:
28322jit.and32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28323OPGEN_RETURN(result);
28324break;
28325break;
28326case Arg::Addr:
28327case Arg::Stack:
28328case Arg::CallArg:
28329#if CPU(X86) || CPU(X86_64)
28330jit.and32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
28331OPGEN_RETURN(result);
28332#endif
28333break;
28334break;
28335default:
28336break;
28337}
28338break;
28339case Arg::BitImm:
28340#if CPU(ARM64)
28341jit.and32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
28342OPGEN_RETURN(result);
28343#endif
28344break;
28345break;
28346case Arg::Addr:
28347case Arg::Stack:
28348case Arg::CallArg:
28349#if CPU(X86) || CPU(X86_64)
28350jit.and32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
28351OPGEN_RETURN(result);
28352#endif
28353break;
28354break;
28355default:
28356break;
28357}
28358break;
28359case 2:
28360switch (this->args[0].kind()) {
28361case Arg::Tmp:
28362switch (this->args[1].kind()) {
28363case Arg::Tmp:
28364jit.and32(args[0].gpr(), args[1].gpr());
28365OPGEN_RETURN(result);
28366break;
28367break;
28368case Arg::Addr:
28369case Arg::Stack:
28370case Arg::CallArg:
28371#if CPU(X86) || CPU(X86_64)
28372jit.and32(args[0].gpr(), args[1].asAddress());
28373OPGEN_RETURN(result);
28374#endif
28375break;
28376break;
28377case Arg::Index:
28378#if CPU(X86) || CPU(X86_64)
28379jit.and32(args[0].gpr(), args[1].asBaseIndex());
28380OPGEN_RETURN(result);
28381#endif
28382break;
28383break;
28384default:
28385break;
28386}
28387break;
28388case Arg::Imm:
28389switch (this->args[1].kind()) {
28390case Arg::Tmp:
28391#if CPU(X86) || CPU(X86_64)
28392jit.and32(args[0].asTrustedImm32(), args[1].gpr());
28393OPGEN_RETURN(result);
28394#endif
28395break;
28396break;
28397case Arg::Addr:
28398case Arg::Stack:
28399case Arg::CallArg:
28400#if CPU(X86) || CPU(X86_64)
28401jit.and32(args[0].asTrustedImm32(), args[1].asAddress());
28402OPGEN_RETURN(result);
28403#endif
28404break;
28405break;
28406case Arg::Index:
28407#if CPU(X86) || CPU(X86_64)
28408jit.and32(args[0].asTrustedImm32(), args[1].asBaseIndex());
28409OPGEN_RETURN(result);
28410#endif
28411break;
28412break;
28413default:
28414break;
28415}
28416break;
28417case Arg::Addr:
28418case Arg::Stack:
28419case Arg::CallArg:
28420#if CPU(X86) || CPU(X86_64)
28421jit.and32(args[0].asAddress(), args[1].gpr());
28422OPGEN_RETURN(result);
28423#endif
28424break;
28425break;
28426case Arg::Index:
28427#if CPU(X86) || CPU(X86_64)
28428jit.and32(args[0].asBaseIndex(), args[1].gpr());
28429OPGEN_RETURN(result);
28430#endif
28431break;
28432break;
28433default:
28434break;
28435}
28436break;
28437default:
28438break;
28439}
28440break;
28441case Opcode::And64:
28442switch (this->args.size()) {
28443case 3:
28444switch (this->args[0].kind()) {
28445case Arg::Tmp:
28446#if CPU(X86_64) || CPU(ARM64)
28447jit.and64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28448OPGEN_RETURN(result);
28449#endif
28450break;
28451break;
28452#if USE(JSVALUE64)
28453case Arg::BitImm64:
28454#if CPU(ARM64)
28455jit.and64(args[0].asTrustedImm64(), args[1].gpr(), args[2].gpr());
28456OPGEN_RETURN(result);
28457#endif
28458break;
28459break;
28460#endif // USE(JSVALUE64)
28461default:
28462break;
28463}
28464break;
28465case 2:
28466switch (this->args[0].kind()) {
28467case Arg::Tmp:
28468switch (this->args[1].kind()) {
28469case Arg::Tmp:
28470#if CPU(X86_64)
28471jit.and64(args[0].gpr(), args[1].gpr());
28472OPGEN_RETURN(result);
28473#endif
28474break;
28475break;
28476case Arg::Addr:
28477case Arg::Stack:
28478case Arg::CallArg:
28479#if CPU(X86_64)
28480jit.and64(args[0].gpr(), args[1].asAddress());
28481OPGEN_RETURN(result);
28482#endif
28483break;
28484break;
28485case Arg::Index:
28486#if CPU(X86_64)
28487jit.and64(args[0].gpr(), args[1].asBaseIndex());
28488OPGEN_RETURN(result);
28489#endif
28490break;
28491break;
28492default:
28493break;
28494}
28495break;
28496case Arg::Imm:
28497switch (this->args[1].kind()) {
28498case Arg::Tmp:
28499#if CPU(X86_64)
28500jit.and64(args[0].asTrustedImm32(), args[1].gpr());
28501OPGEN_RETURN(result);
28502#endif
28503break;
28504break;
28505case Arg::Addr:
28506case Arg::Stack:
28507case Arg::CallArg:
28508#if CPU(X86_64)
28509jit.and64(args[0].asTrustedImm32(), args[1].asAddress());
28510OPGEN_RETURN(result);
28511#endif
28512break;
28513break;
28514case Arg::Index:
28515#if CPU(X86_64)
28516jit.and64(args[0].asTrustedImm32(), args[1].asBaseIndex());
28517OPGEN_RETURN(result);
28518#endif
28519break;
28520break;
28521default:
28522break;
28523}
28524break;
28525case Arg::Addr:
28526case Arg::Stack:
28527case Arg::CallArg:
28528#if CPU(X86_64)
28529jit.and64(args[0].asAddress(), args[1].gpr());
28530OPGEN_RETURN(result);
28531#endif
28532break;
28533break;
28534case Arg::Index:
28535#if CPU(X86_64)
28536jit.and64(args[0].asBaseIndex(), args[1].gpr());
28537OPGEN_RETURN(result);
28538#endif
28539break;
28540break;
28541default:
28542break;
28543}
28544break;
28545default:
28546break;
28547}
28548break;
28549case Opcode::AndDouble:
28550switch (this->args.size()) {
28551case 3:
28552jit.andDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28553OPGEN_RETURN(result);
28554break;
28555break;
28556case 2:
28557#if CPU(X86) || CPU(X86_64)
28558jit.andDouble(args[0].fpr(), args[1].fpr());
28559OPGEN_RETURN(result);
28560#endif
28561break;
28562break;
28563default:
28564break;
28565}
28566break;
28567case Opcode::AndFloat:
28568switch (this->args.size()) {
28569case 3:
28570jit.andFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28571OPGEN_RETURN(result);
28572break;
28573break;
28574case 2:
28575#if CPU(X86) || CPU(X86_64)
28576jit.andFloat(args[0].fpr(), args[1].fpr());
28577OPGEN_RETURN(result);
28578#endif
28579break;
28580break;
28581default:
28582break;
28583}
28584break;
28585case Opcode::OrDouble:
28586switch (this->args.size()) {
28587case 3:
28588jit.orDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28589OPGEN_RETURN(result);
28590break;
28591break;
28592case 2:
28593#if CPU(X86) || CPU(X86_64)
28594jit.orDouble(args[0].fpr(), args[1].fpr());
28595OPGEN_RETURN(result);
28596#endif
28597break;
28598break;
28599default:
28600break;
28601}
28602break;
28603case Opcode::OrFloat:
28604switch (this->args.size()) {
28605case 3:
28606jit.orFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28607OPGEN_RETURN(result);
28608break;
28609break;
28610case 2:
28611#if CPU(X86) || CPU(X86_64)
28612jit.orFloat(args[0].fpr(), args[1].fpr());
28613OPGEN_RETURN(result);
28614#endif
28615break;
28616break;
28617default:
28618break;
28619}
28620break;
28621case Opcode::XorDouble:
28622switch (this->args.size()) {
28623case 3:
28624#if CPU(X86) || CPU(X86_64)
28625jit.xorDouble(args[0].fpr(), args[1].fpr(), args[2].fpr());
28626OPGEN_RETURN(result);
28627#endif
28628break;
28629break;
28630case 2:
28631#if CPU(X86) || CPU(X86_64)
28632jit.xorDouble(args[0].fpr(), args[1].fpr());
28633OPGEN_RETURN(result);
28634#endif
28635break;
28636break;
28637default:
28638break;
28639}
28640break;
28641case Opcode::XorFloat:
28642switch (this->args.size()) {
28643case 3:
28644#if CPU(X86) || CPU(X86_64)
28645jit.xorFloat(args[0].fpr(), args[1].fpr(), args[2].fpr());
28646OPGEN_RETURN(result);
28647#endif
28648break;
28649break;
28650case 2:
28651#if CPU(X86) || CPU(X86_64)
28652jit.xorFloat(args[0].fpr(), args[1].fpr());
28653OPGEN_RETURN(result);
28654#endif
28655break;
28656break;
28657default:
28658break;
28659}
28660break;
28661case Opcode::Lshift32:
28662switch (this->args.size()) {
28663case 3:
28664switch (this->args[1].kind()) {
28665case Arg::Tmp:
28666#if CPU(ARM64)
28667jit.lshift32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28668OPGEN_RETURN(result);
28669#endif
28670break;
28671break;
28672case Arg::Imm:
28673#if CPU(ARM64)
28674jit.lshift32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28675OPGEN_RETURN(result);
28676#endif
28677break;
28678break;
28679default:
28680break;
28681}
28682break;
28683case 2:
28684switch (this->args[0].kind()) {
28685case Arg::Tmp:
28686#if CPU(X86) || CPU(X86_64)
28687jit.lshift32(args[0].gpr(), args[1].gpr());
28688OPGEN_RETURN(result);
28689#endif
28690break;
28691break;
28692case Arg::Imm:
28693#if CPU(X86) || CPU(X86_64)
28694jit.lshift32(args[0].asTrustedImm32(), args[1].gpr());
28695OPGEN_RETURN(result);
28696#endif
28697break;
28698break;
28699default:
28700break;
28701}
28702break;
28703default:
28704break;
28705}
28706break;
28707case Opcode::Lshift64:
28708switch (this->args.size()) {
28709case 3:
28710switch (this->args[1].kind()) {
28711case Arg::Tmp:
28712#if CPU(ARM64)
28713jit.lshift64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28714OPGEN_RETURN(result);
28715#endif
28716break;
28717break;
28718case Arg::Imm:
28719#if CPU(ARM64)
28720jit.lshift64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28721OPGEN_RETURN(result);
28722#endif
28723break;
28724break;
28725default:
28726break;
28727}
28728break;
28729case 2:
28730switch (this->args[0].kind()) {
28731case Arg::Tmp:
28732#if CPU(X86_64)
28733jit.lshift64(args[0].gpr(), args[1].gpr());
28734OPGEN_RETURN(result);
28735#endif
28736break;
28737break;
28738case Arg::Imm:
28739#if CPU(X86_64)
28740jit.lshift64(args[0].asTrustedImm32(), args[1].gpr());
28741OPGEN_RETURN(result);
28742#endif
28743break;
28744break;
28745default:
28746break;
28747}
28748break;
28749default:
28750break;
28751}
28752break;
28753case Opcode::Rshift32:
28754switch (this->args.size()) {
28755case 3:
28756switch (this->args[1].kind()) {
28757case Arg::Tmp:
28758#if CPU(ARM64)
28759jit.rshift32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28760OPGEN_RETURN(result);
28761#endif
28762break;
28763break;
28764case Arg::Imm:
28765#if CPU(ARM64)
28766jit.rshift32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28767OPGEN_RETURN(result);
28768#endif
28769break;
28770break;
28771default:
28772break;
28773}
28774break;
28775case 2:
28776switch (this->args[0].kind()) {
28777case Arg::Tmp:
28778#if CPU(X86) || CPU(X86_64)
28779jit.rshift32(args[0].gpr(), args[1].gpr());
28780OPGEN_RETURN(result);
28781#endif
28782break;
28783break;
28784case Arg::Imm:
28785#if CPU(X86) || CPU(X86_64)
28786jit.rshift32(args[0].asTrustedImm32(), args[1].gpr());
28787OPGEN_RETURN(result);
28788#endif
28789break;
28790break;
28791default:
28792break;
28793}
28794break;
28795default:
28796break;
28797}
28798break;
28799case Opcode::Rshift64:
28800switch (this->args.size()) {
28801case 3:
28802switch (this->args[1].kind()) {
28803case Arg::Tmp:
28804#if CPU(ARM64)
28805jit.rshift64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28806OPGEN_RETURN(result);
28807#endif
28808break;
28809break;
28810case Arg::Imm:
28811#if CPU(ARM64)
28812jit.rshift64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28813OPGEN_RETURN(result);
28814#endif
28815break;
28816break;
28817default:
28818break;
28819}
28820break;
28821case 2:
28822switch (this->args[0].kind()) {
28823case Arg::Tmp:
28824#if CPU(X86_64)
28825jit.rshift64(args[0].gpr(), args[1].gpr());
28826OPGEN_RETURN(result);
28827#endif
28828break;
28829break;
28830case Arg::Imm:
28831#if CPU(X86_64)
28832jit.rshift64(args[0].asTrustedImm32(), args[1].gpr());
28833OPGEN_RETURN(result);
28834#endif
28835break;
28836break;
28837default:
28838break;
28839}
28840break;
28841default:
28842break;
28843}
28844break;
28845case Opcode::Urshift32:
28846switch (this->args.size()) {
28847case 3:
28848switch (this->args[1].kind()) {
28849case Arg::Tmp:
28850#if CPU(ARM64)
28851jit.urshift32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28852OPGEN_RETURN(result);
28853#endif
28854break;
28855break;
28856case Arg::Imm:
28857#if CPU(ARM64)
28858jit.urshift32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28859OPGEN_RETURN(result);
28860#endif
28861break;
28862break;
28863default:
28864break;
28865}
28866break;
28867case 2:
28868switch (this->args[0].kind()) {
28869case Arg::Tmp:
28870#if CPU(X86) || CPU(X86_64)
28871jit.urshift32(args[0].gpr(), args[1].gpr());
28872OPGEN_RETURN(result);
28873#endif
28874break;
28875break;
28876case Arg::Imm:
28877#if CPU(X86) || CPU(X86_64)
28878jit.urshift32(args[0].asTrustedImm32(), args[1].gpr());
28879OPGEN_RETURN(result);
28880#endif
28881break;
28882break;
28883default:
28884break;
28885}
28886break;
28887default:
28888break;
28889}
28890break;
28891case Opcode::Urshift64:
28892switch (this->args.size()) {
28893case 3:
28894switch (this->args[1].kind()) {
28895case Arg::Tmp:
28896#if CPU(ARM64)
28897jit.urshift64(args[0].gpr(), args[1].gpr(), args[2].gpr());
28898OPGEN_RETURN(result);
28899#endif
28900break;
28901break;
28902case Arg::Imm:
28903#if CPU(ARM64)
28904jit.urshift64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28905OPGEN_RETURN(result);
28906#endif
28907break;
28908break;
28909default:
28910break;
28911}
28912break;
28913case 2:
28914switch (this->args[0].kind()) {
28915case Arg::Tmp:
28916#if CPU(X86_64)
28917jit.urshift64(args[0].gpr(), args[1].gpr());
28918OPGEN_RETURN(result);
28919#endif
28920break;
28921break;
28922case Arg::Imm:
28923#if CPU(X86_64)
28924jit.urshift64(args[0].asTrustedImm32(), args[1].gpr());
28925OPGEN_RETURN(result);
28926#endif
28927break;
28928break;
28929default:
28930break;
28931}
28932break;
28933default:
28934break;
28935}
28936break;
28937case Opcode::RotateRight32:
28938switch (this->args.size()) {
28939case 2:
28940switch (this->args[0].kind()) {
28941case Arg::Tmp:
28942#if CPU(X86_64)
28943jit.rotateRight32(args[0].gpr(), args[1].gpr());
28944OPGEN_RETURN(result);
28945#endif
28946break;
28947break;
28948case Arg::Imm:
28949#if CPU(X86_64)
28950jit.rotateRight32(args[0].asTrustedImm32(), args[1].gpr());
28951OPGEN_RETURN(result);
28952#endif
28953break;
28954break;
28955default:
28956break;
28957}
28958break;
28959case 3:
28960switch (this->args[1].kind()) {
28961case Arg::Tmp:
28962#if CPU(ARM64)
28963jit.rotateRight32(args[0].gpr(), args[1].gpr(), args[2].gpr());
28964OPGEN_RETURN(result);
28965#endif
28966break;
28967break;
28968case Arg::Imm:
28969#if CPU(ARM64)
28970jit.rotateRight32(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
28971OPGEN_RETURN(result);
28972#endif
28973break;
28974break;
28975default:
28976break;
28977}
28978break;
28979default:
28980break;
28981}
28982break;
28983case Opcode::RotateRight64:
28984switch (this->args.size()) {
28985case 2:
28986switch (this->args[0].kind()) {
28987case Arg::Tmp:
28988#if CPU(X86_64)
28989jit.rotateRight64(args[0].gpr(), args[1].gpr());
28990OPGEN_RETURN(result);
28991#endif
28992break;
28993break;
28994case Arg::Imm:
28995#if CPU(X86_64)
28996jit.rotateRight64(args[0].asTrustedImm32(), args[1].gpr());
28997OPGEN_RETURN(result);
28998#endif
28999break;
29000break;
29001default:
29002break;
29003}
29004break;
29005case 3:
29006switch (this->args[1].kind()) {
29007case Arg::Tmp:
29008#if CPU(ARM64)
29009jit.rotateRight64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29010OPGEN_RETURN(result);
29011#endif
29012break;
29013break;
29014case Arg::Imm:
29015#if CPU(ARM64)
29016jit.rotateRight64(args[0].gpr(), args[1].asTrustedImm32(), args[2].gpr());
29017OPGEN_RETURN(result);
29018#endif
29019break;
29020break;
29021default:
29022break;
29023}
29024break;
29025default:
29026break;
29027}
29028break;
29029case Opcode::RotateLeft32:
29030switch (this->args[0].kind()) {
29031case Arg::Tmp:
29032#if CPU(X86_64)
29033jit.rotateLeft32(args[0].gpr(), args[1].gpr());
29034OPGEN_RETURN(result);
29035#endif
29036break;
29037break;
29038case Arg::Imm:
29039#if CPU(X86_64)
29040jit.rotateLeft32(args[0].asTrustedImm32(), args[1].gpr());
29041OPGEN_RETURN(result);
29042#endif
29043break;
29044break;
29045default:
29046break;
29047}
29048break;
29049case Opcode::RotateLeft64:
29050switch (this->args[0].kind()) {
29051case Arg::Tmp:
29052#if CPU(X86_64)
29053jit.rotateLeft64(args[0].gpr(), args[1].gpr());
29054OPGEN_RETURN(result);
29055#endif
29056break;
29057break;
29058case Arg::Imm:
29059#if CPU(X86_64)
29060jit.rotateLeft64(args[0].asTrustedImm32(), args[1].gpr());
29061OPGEN_RETURN(result);
29062#endif
29063break;
29064break;
29065default:
29066break;
29067}
29068break;
29069case Opcode::Or32:
29070switch (this->args.size()) {
29071case 3:
29072switch (this->args[0].kind()) {
29073case Arg::Tmp:
29074switch (this->args[1].kind()) {
29075case Arg::Tmp:
29076jit.or32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29077OPGEN_RETURN(result);
29078break;
29079break;
29080case Arg::Addr:
29081case Arg::Stack:
29082case Arg::CallArg:
29083#if CPU(X86) || CPU(X86_64)
29084jit.or32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
29085OPGEN_RETURN(result);
29086#endif
29087break;
29088break;
29089default:
29090break;
29091}
29092break;
29093case Arg::BitImm:
29094#if CPU(ARM64)
29095jit.or32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
29096OPGEN_RETURN(result);
29097#endif
29098break;
29099break;
29100case Arg::Addr:
29101case Arg::Stack:
29102case Arg::CallArg:
29103#if CPU(X86) || CPU(X86_64)
29104jit.or32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
29105OPGEN_RETURN(result);
29106#endif
29107break;
29108break;
29109default:
29110break;
29111}
29112break;
29113case 2:
29114switch (this->args[0].kind()) {
29115case Arg::Tmp:
29116switch (this->args[1].kind()) {
29117case Arg::Tmp:
29118jit.or32(args[0].gpr(), args[1].gpr());
29119OPGEN_RETURN(result);
29120break;
29121break;
29122case Arg::Addr:
29123case Arg::Stack:
29124case Arg::CallArg:
29125#if CPU(X86) || CPU(X86_64)
29126jit.or32(args[0].gpr(), args[1].asAddress());
29127OPGEN_RETURN(result);
29128#endif
29129break;
29130break;
29131case Arg::Index:
29132#if CPU(X86) || CPU(X86_64)
29133jit.or32(args[0].gpr(), args[1].asBaseIndex());
29134OPGEN_RETURN(result);
29135#endif
29136break;
29137break;
29138default:
29139break;
29140}
29141break;
29142case Arg::Imm:
29143switch (this->args[1].kind()) {
29144case Arg::Tmp:
29145#if CPU(X86) || CPU(X86_64)
29146jit.or32(args[0].asTrustedImm32(), args[1].gpr());
29147OPGEN_RETURN(result);
29148#endif
29149break;
29150break;
29151case Arg::Addr:
29152case Arg::Stack:
29153case Arg::CallArg:
29154#if CPU(X86) || CPU(X86_64)
29155jit.or32(args[0].asTrustedImm32(), args[1].asAddress());
29156OPGEN_RETURN(result);
29157#endif
29158break;
29159break;
29160case Arg::Index:
29161#if CPU(X86) || CPU(X86_64)
29162jit.or32(args[0].asTrustedImm32(), args[1].asBaseIndex());
29163OPGEN_RETURN(result);
29164#endif
29165break;
29166break;
29167default:
29168break;
29169}
29170break;
29171case Arg::Addr:
29172case Arg::Stack:
29173case Arg::CallArg:
29174#if CPU(X86) || CPU(X86_64)
29175jit.or32(args[0].asAddress(), args[1].gpr());
29176OPGEN_RETURN(result);
29177#endif
29178break;
29179break;
29180case Arg::Index:
29181#if CPU(X86) || CPU(X86_64)
29182jit.or32(args[0].asBaseIndex(), args[1].gpr());
29183OPGEN_RETURN(result);
29184#endif
29185break;
29186break;
29187default:
29188break;
29189}
29190break;
29191default:
29192break;
29193}
29194break;
29195case Opcode::Or64:
29196switch (this->args.size()) {
29197case 3:
29198switch (this->args[0].kind()) {
29199case Arg::Tmp:
29200#if CPU(X86_64) || CPU(ARM64)
29201jit.or64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29202OPGEN_RETURN(result);
29203#endif
29204break;
29205break;
29206#if USE(JSVALUE64)
29207case Arg::BitImm64:
29208#if CPU(ARM64)
29209jit.or64(args[0].asTrustedImm64(), args[1].gpr(), args[2].gpr());
29210OPGEN_RETURN(result);
29211#endif
29212break;
29213break;
29214#endif // USE(JSVALUE64)
29215default:
29216break;
29217}
29218break;
29219case 2:
29220switch (this->args[0].kind()) {
29221case Arg::Tmp:
29222switch (this->args[1].kind()) {
29223case Arg::Tmp:
29224#if CPU(X86_64) || CPU(ARM64)
29225jit.or64(args[0].gpr(), args[1].gpr());
29226OPGEN_RETURN(result);
29227#endif
29228break;
29229break;
29230case Arg::Addr:
29231case Arg::Stack:
29232case Arg::CallArg:
29233#if CPU(X86_64)
29234jit.or64(args[0].gpr(), args[1].asAddress());
29235OPGEN_RETURN(result);
29236#endif
29237break;
29238break;
29239case Arg::Index:
29240#if CPU(X86_64)
29241jit.or64(args[0].gpr(), args[1].asBaseIndex());
29242OPGEN_RETURN(result);
29243#endif
29244break;
29245break;
29246default:
29247break;
29248}
29249break;
29250case Arg::Imm:
29251switch (this->args[1].kind()) {
29252case Arg::Tmp:
29253#if CPU(X86_64)
29254jit.or64(args[0].asTrustedImm32(), args[1].gpr());
29255OPGEN_RETURN(result);
29256#endif
29257break;
29258break;
29259case Arg::Addr:
29260case Arg::Stack:
29261case Arg::CallArg:
29262#if CPU(X86_64)
29263jit.or64(args[0].asTrustedImm32(), args[1].asAddress());
29264OPGEN_RETURN(result);
29265#endif
29266break;
29267break;
29268case Arg::Index:
29269#if CPU(X86_64)
29270jit.or64(args[0].asTrustedImm32(), args[1].asBaseIndex());
29271OPGEN_RETURN(result);
29272#endif
29273break;
29274break;
29275default:
29276break;
29277}
29278break;
29279case Arg::Addr:
29280case Arg::Stack:
29281case Arg::CallArg:
29282#if CPU(X86_64)
29283jit.or64(args[0].asAddress(), args[1].gpr());
29284OPGEN_RETURN(result);
29285#endif
29286break;
29287break;
29288case Arg::Index:
29289#if CPU(X86_64)
29290jit.or64(args[0].asBaseIndex(), args[1].gpr());
29291OPGEN_RETURN(result);
29292#endif
29293break;
29294break;
29295default:
29296break;
29297}
29298break;
29299default:
29300break;
29301}
29302break;
29303case Opcode::Xor32:
29304switch (this->args.size()) {
29305case 3:
29306switch (this->args[0].kind()) {
29307case Arg::Tmp:
29308switch (this->args[1].kind()) {
29309case Arg::Tmp:
29310jit.xor32(args[0].gpr(), args[1].gpr(), args[2].gpr());
29311OPGEN_RETURN(result);
29312break;
29313break;
29314case Arg::Addr:
29315case Arg::Stack:
29316case Arg::CallArg:
29317#if CPU(X86) || CPU(X86_64)
29318jit.xor32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
29319OPGEN_RETURN(result);
29320#endif
29321break;
29322break;
29323default:
29324break;
29325}
29326break;
29327case Arg::BitImm:
29328#if CPU(ARM64)
29329jit.xor32(args[0].asTrustedImm32(), args[1].gpr(), args[2].gpr());
29330OPGEN_RETURN(result);
29331#endif
29332break;
29333break;
29334case Arg::Addr:
29335case Arg::Stack:
29336case Arg::CallArg:
29337#if CPU(X86) || CPU(X86_64)
29338jit.xor32(args[0].asAddress(), args[1].gpr(), args[2].gpr());
29339OPGEN_RETURN(result);
29340#endif
29341break;
29342break;
29343default:
29344break;
29345}
29346break;
29347case 2:
29348switch (this->args[0].kind()) {
29349case Arg::Tmp:
29350switch (this->args[1].kind()) {
29351case Arg::Tmp:
29352jit.xor32(args[0].gpr(), args[1].gpr());
29353OPGEN_RETURN(result);
29354break;
29355break;
29356case Arg::Addr:
29357case Arg::Stack:
29358case Arg::CallArg:
29359#if CPU(X86) || CPU(X86_64)
29360jit.xor32(args[0].gpr(), args[1].asAddress());
29361OPGEN_RETURN(result);
29362#endif
29363break;
29364break;
29365case Arg::Index:
29366#if CPU(X86) || CPU(X86_64)
29367jit.xor32(args[0].gpr(), args[1].asBaseIndex());
29368OPGEN_RETURN(result);
29369#endif
29370break;
29371break;
29372default:
29373break;
29374}
29375break;
29376case Arg::Imm:
29377switch (this->args[1].kind()) {
29378case Arg::Tmp:
29379#if CPU(X86) || CPU(X86_64)
29380jit.xor32(args[0].asTrustedImm32(), args[1].gpr());
29381OPGEN_RETURN(result);
29382#endif
29383break;
29384break;
29385case Arg::Addr:
29386case Arg::Stack:
29387case Arg::CallArg:
29388#if CPU(X86) || CPU(X86_64)
29389jit.xor32(args[0].asTrustedImm32(), args[1].asAddress());
29390OPGEN_RETURN(result);
29391#endif
29392break;
29393break;
29394case Arg::Index:
29395#if CPU(X86) || CPU(X86_64)
29396jit.xor32(args[0].asTrustedImm32(), args[1].asBaseIndex());
29397OPGEN_RETURN(result);
29398#endif
29399break;
29400break;
29401default:
29402break;
29403}
29404break;
29405case Arg::Addr:
29406case Arg::Stack:
29407case Arg::CallArg:
29408#if CPU(X86) || CPU(X86_64)
29409jit.xor32(args[0].asAddress(), args[1].gpr());
29410OPGEN_RETURN(result);
29411#endif
29412break;
29413break;
29414case Arg::Index:
29415#if CPU(X86) || CPU(X86_64)
29416jit.xor32(args[0].asBaseIndex(), args[1].gpr());
29417OPGEN_RETURN(result);
29418#endif
29419break;
29420break;
29421default:
29422break;
29423}
29424break;
29425default:
29426break;
29427}
29428break;
29429case Opcode::Xor64:
29430switch (this->args.size()) {
29431case 3:
29432switch (this->args[0].kind()) {
29433case Arg::Tmp:
29434#if CPU(X86_64) || CPU(ARM64)
29435jit.xor64(args[0].gpr(), args[1].gpr(), args[2].gpr());
29436OPGEN_RETURN(result);
29437#endif
29438break;
29439break;
29440#if USE(JSVALUE64)
29441case Arg::BitImm64:
29442#if CPU(ARM64)
29443jit.xor64(args[0].asTrustedImm64(), args[1].gpr(), args[2].gpr());
29444OPGEN_RETURN(result);
29445#endif
29446break;
29447break;
29448#endif // USE(JSVALUE64)
29449default:
29450break;
29451}
29452break;
29453case 2:
29454switch (this->args[0].kind()) {
29455case Arg::Tmp:
29456switch (this->args[1].kind()) {
29457case Arg::Tmp:
29458#if CPU(X86_64) || CPU(ARM64)
29459jit.xor64(args[0].gpr(), args[1].gpr());
29460OPGEN_RETURN(result);
29461#endif
29462break;
29463break;
29464case Arg::Addr:
29465case Arg::Stack:
29466case Arg::CallArg:
29467#if CPU(X86_64)
29468jit.xor64(args[0].gpr(), args[1].asAddress());
29469OPGEN_RETURN(result);
29470#endif
29471break;
29472break;
29473case Arg::Index:
29474#if CPU(X86_64)
29475jit.xor64(args[0].gpr(), args[1].asBaseIndex());
29476OPGEN_RETURN(result);
29477#endif
29478break;
29479break;
29480default:
29481break;
29482}
29483break;
29484case Arg::Addr:
29485case Arg::Stack:
29486case Arg::CallArg:
29487#if CPU(X86_64)
29488jit.xor64(args[0].asAddress(), args[1].gpr());
29489OPGEN_RETURN(result);
29490#endif
29491break;
29492break;
29493case Arg::Index:
29494#if CPU(X86_64)
29495jit.xor64(args[0].asBaseIndex(), args[1].gpr());
29496OPGEN_RETURN(result);
29497#endif
29498break;
29499break;
29500case Arg::Imm:
29501switch (this->args[1].kind()) {
29502case Arg::Addr:
29503case Arg::Stack:
29504case Arg::CallArg:
29505#if CPU(X86_64)
29506jit.xor64(args[0].asTrustedImm32(), args[1].asAddress());
29507OPGEN_RETURN(result);
29508#endif
29509break;
29510break;
29511case Arg::Index:
29512#if CPU(X86_64)
29513jit.xor64(args[0].asTrustedImm32(), args[1].asBaseIndex());
29514OPGEN_RETURN(result);
29515#endif
29516break;
29517break;
29518case Arg::Tmp:
29519#if CPU(X86_64)
29520jit.xor64(args[0].asTrustedImm32(), args[1].gpr());
29521OPGEN_RETURN(result);
29522#endif
29523break;
29524break;
29525default:
29526break;
29527}
29528break;
29529default:
29530break;
29531}
29532break;
29533default:
29534break;
29535}
29536break;
29537case Opcode::Not32:
29538switch (this->args.size()) {
29539case 2:
29540#if CPU(ARM64)
29541jit.not32(args[0].gpr(), args[1].gpr());
29542OPGEN_RETURN(result);
29543#endif
29544break;
29545break;
29546case 1:
29547switch (this->args[0].kind()) {
29548case Arg::Tmp:
29549#if CPU(X86) || CPU(X86_64)
29550jit.not32(args[0].gpr());
29551OPGEN_RETURN(result);
29552#endif
29553break;
29554break;
29555case Arg::Addr:
29556case Arg::Stack:
29557case Arg::CallArg:
29558#if CPU(X86) || CPU(X86_64)
29559jit.not32(args[0].asAddress());
29560OPGEN_RETURN(result);
29561#endif
29562break;
29563break;
29564case Arg::Index:
29565#if CPU(X86) || CPU(X86_64)
29566jit.not32(args[0].asBaseIndex());
29567OPGEN_RETURN(result);
29568#endif
29569break;
29570break;
29571default:
29572break;
29573}
29574break;
29575default:
29576break;
29577}
29578break;
29579case Opcode::Not64:
29580switch (this->args.size()) {
29581case 2:
29582#if CPU(ARM64)
29583jit.not64(args[0].gpr(), args[1].gpr());
29584OPGEN_RETURN(result);
29585#endif
29586break;
29587break;
29588case 1:
29589switch (this->args[0].kind()) {
29590case Arg::Tmp:
29591#if CPU(X86_64)
29592jit.not64(args[0].gpr());
29593OPGEN_RETURN(result);
29594#endif
29595break;
29596break;
29597case Arg::Addr:
29598case Arg::Stack:
29599case Arg::CallArg:
29600#if CPU(X86_64)
29601jit.not64(args[0].asAddress());
29602OPGEN_RETURN(result);
29603#endif
29604break;
29605break;
29606case Arg::Index:
29607#if CPU(X86_64)
29608jit.not64(args[0].asBaseIndex());
29609OPGEN_RETURN(result);
29610#endif
29611break;
29612break;
29613default:
29614break;
29615}
29616break;
29617default:
29618break;
29619}
29620break;
29621case Opcode::AbsDouble:
29622#if CPU(ARM64)
29623jit.absDouble(args[0].fpr(), args[1].fpr());
29624OPGEN_RETURN(result);
29625#endif
29626break;
29627break;
29628case Opcode::AbsFloat:
29629#if CPU(ARM64)
29630jit.absFloat(args[0].fpr(), args[1].fpr());
29631OPGEN_RETURN(result);
29632#endif
29633break;
29634break;
29635case Opcode::CeilDouble:
29636switch (this->args[0].kind()) {
29637case Arg::Tmp:
29638jit.ceilDouble(args[0].fpr(), args[1].fpr());
29639OPGEN_RETURN(result);
29640break;
29641break;
29642case Arg::Addr:
29643case Arg::Stack:
29644case Arg::CallArg:
29645#if CPU(X86) || CPU(X86_64)
29646jit.ceilDouble(args[0].asAddress(), args[1].fpr());
29647OPGEN_RETURN(result);
29648#endif
29649break;
29650break;
29651default:
29652break;
29653}
29654break;
29655case Opcode::CeilFloat:
29656switch (this->args[0].kind()) {
29657case Arg::Tmp:
29658jit.ceilFloat(args[0].fpr(), args[1].fpr());
29659OPGEN_RETURN(result);
29660break;
29661break;
29662case Arg::Addr:
29663case Arg::Stack:
29664case Arg::CallArg:
29665#if CPU(X86) || CPU(X86_64)
29666jit.ceilFloat(args[0].asAddress(), args[1].fpr());
29667OPGEN_RETURN(result);
29668#endif
29669break;
29670break;
29671default:
29672break;
29673}
29674break;
29675case Opcode::FloorDouble:
29676switch (this->args[0].kind()) {
29677case Arg::Tmp:
29678jit.floorDouble(args[0].fpr(), args[1].fpr());
29679OPGEN_RETURN(result);
29680break;
29681break;
29682case Arg::Addr:
29683case Arg::Stack:
29684case Arg::CallArg:
29685#if CPU(X86) || CPU(X86_64)
29686jit.floorDouble(args[0].asAddress(), args[1].fpr());
29687OPGEN_RETURN(result);
29688#endif
29689break;
29690break;
29691default:
29692break;
29693}
29694break;
29695case Opcode::FloorFloat:
29696switch (this->args[0].kind()) {
29697case Arg::Tmp:
29698jit.floorFloat(args[0].fpr(), args[1].fpr());
29699OPGEN_RETURN(result);
29700break;
29701break;
29702case Arg::Addr:
29703case Arg::Stack:
29704case Arg::CallArg:
29705#if CPU(X86) || CPU(X86_64)
29706jit.floorFloat(args[0].asAddress(), args[1].fpr());
29707OPGEN_RETURN(result);
29708#endif
29709break;
29710break;
29711default:
29712break;
29713}
29714break;
29715case Opcode::SqrtDouble:
29716switch (this->args[0].kind()) {
29717case Arg::Tmp:
29718jit.sqrtDouble(args[0].fpr(), args[1].fpr());
29719OPGEN_RETURN(result);
29720break;
29721break;
29722case Arg::Addr:
29723case Arg::Stack:
29724case Arg::CallArg:
29725#if CPU(X86) || CPU(X86_64)
29726jit.sqrtDouble(args[0].asAddress(), args[1].fpr());
29727OPGEN_RETURN(result);
29728#endif
29729break;
29730break;
29731default:
29732break;
29733}
29734break;
29735case Opcode::SqrtFloat:
29736switch (this->args[0].kind()) {
29737case Arg::Tmp:
29738jit.sqrtFloat(args[0].fpr(), args[1].fpr());
29739OPGEN_RETURN(result);
29740break;
29741break;
29742case Arg::Addr:
29743case Arg::Stack:
29744case Arg::CallArg:
29745#if CPU(X86) || CPU(X86_64)
29746jit.sqrtFloat(args[0].asAddress(), args[1].fpr());
29747OPGEN_RETURN(result);
29748#endif
29749break;
29750break;
29751default:
29752break;
29753}
29754break;
29755case Opcode::ConvertInt32ToDouble:
29756switch (this->args[0].kind()) {
29757case Arg::Tmp:
29758jit.convertInt32ToDouble(args[0].gpr(), args[1].fpr());
29759OPGEN_RETURN(result);
29760break;
29761break;
29762case Arg::Addr:
29763case Arg::Stack:
29764case Arg::CallArg:
29765#if CPU(X86) || CPU(X86_64)
29766jit.convertInt32ToDouble(args[0].asAddress(), args[1].fpr());
29767OPGEN_RETURN(result);
29768#endif
29769break;
29770break;
29771default:
29772break;
29773}
29774break;
29775case Opcode::ConvertInt64ToDouble:
29776switch (this->args[0].kind()) {
29777case Arg::Tmp:
29778#if CPU(X86_64) || CPU(ARM64)
29779jit.convertInt64ToDouble(args[0].gpr(), args[1].fpr());
29780OPGEN_RETURN(result);
29781#endif
29782break;
29783break;
29784case Arg::Addr:
29785case Arg::Stack:
29786case Arg::CallArg:
29787#if CPU(X86_64)
29788jit.convertInt64ToDouble(args[0].asAddress(), args[1].fpr());
29789OPGEN_RETURN(result);
29790#endif
29791break;
29792break;
29793default:
29794break;
29795}
29796break;
29797case Opcode::ConvertInt32ToFloat:
29798switch (this->args[0].kind()) {
29799case Arg::Tmp:
29800jit.convertInt32ToFloat(args[0].gpr(), args[1].fpr());
29801OPGEN_RETURN(result);
29802break;
29803break;
29804case Arg::Addr:
29805case Arg::Stack:
29806case Arg::CallArg:
29807#if CPU(X86) || CPU(X86_64)
29808jit.convertInt32ToFloat(args[0].asAddress(), args[1].fpr());
29809OPGEN_RETURN(result);
29810#endif
29811break;
29812break;
29813default:
29814break;
29815}
29816break;
29817case Opcode::ConvertInt64ToFloat:
29818switch (this->args[0].kind()) {
29819case Arg::Tmp:
29820#if CPU(X86_64) || CPU(ARM64)
29821jit.convertInt64ToFloat(args[0].gpr(), args[1].fpr());
29822OPGEN_RETURN(result);
29823#endif
29824break;
29825break;
29826case Arg::Addr:
29827case Arg::Stack:
29828case Arg::CallArg:
29829#if CPU(X86_64)
29830jit.convertInt64ToFloat(args[0].asAddress(), args[1].fpr());
29831OPGEN_RETURN(result);
29832#endif
29833break;
29834break;
29835default:
29836break;
29837}
29838break;
29839case Opcode::CountLeadingZeros32:
29840switch (this->args[0].kind()) {
29841case Arg::Tmp:
29842jit.countLeadingZeros32(args[0].gpr(), args[1].gpr());
29843OPGEN_RETURN(result);
29844break;
29845break;
29846case Arg::Addr:
29847case Arg::Stack:
29848case Arg::CallArg:
29849#if CPU(X86) || CPU(X86_64)
29850jit.countLeadingZeros32(args[0].asAddress(), args[1].gpr());
29851OPGEN_RETURN(result);
29852#endif
29853break;
29854break;
29855default:
29856break;
29857}
29858break;
29859case Opcode::CountLeadingZeros64:
29860switch (this->args[0].kind()) {
29861case Arg::Tmp:
29862#if CPU(X86_64) || CPU(ARM64)
29863jit.countLeadingZeros64(args[0].gpr(), args[1].gpr());
29864OPGEN_RETURN(result);
29865#endif
29866break;
29867break;
29868case Arg::Addr:
29869case Arg::Stack:
29870case Arg::CallArg:
29871#if CPU(X86_64)
29872jit.countLeadingZeros64(args[0].asAddress(), args[1].gpr());
29873OPGEN_RETURN(result);
29874#endif
29875break;
29876break;
29877default:
29878break;
29879}
29880break;
29881case Opcode::ConvertDoubleToFloat:
29882switch (this->args[0].kind()) {
29883case Arg::Tmp:
29884jit.convertDoubleToFloat(args[0].fpr(), args[1].fpr());
29885OPGEN_RETURN(result);
29886break;
29887break;
29888case Arg::Addr:
29889case Arg::Stack:
29890case Arg::CallArg:
29891#if CPU(X86) || CPU(X86_64)
29892jit.convertDoubleToFloat(args[0].asAddress(), args[1].fpr());
29893OPGEN_RETURN(result);
29894#endif
29895break;
29896break;
29897default:
29898break;
29899}
29900break;
29901case Opcode::ConvertFloatToDouble:
29902switch (this->args[0].kind()) {
29903case Arg::Tmp:
29904jit.convertFloatToDouble(args[0].fpr(), args[1].fpr());
29905OPGEN_RETURN(result);
29906break;
29907break;
29908case Arg::Addr:
29909case Arg::Stack:
29910case Arg::CallArg:
29911#if CPU(X86) || CPU(X86_64)
29912jit.convertFloatToDouble(args[0].asAddress(), args[1].fpr());
29913OPGEN_RETURN(result);
29914#endif
29915break;
29916break;
29917default:
29918break;
29919}
29920break;
29921case Opcode::Move:
29922switch (this->args.size()) {
29923case 2:
29924switch (this->args[0].kind()) {
29925case Arg::Tmp:
29926switch (this->args[1].kind()) {
29927case Arg::Tmp:
29928jit.move(args[0].gpr(), args[1].gpr());
29929OPGEN_RETURN(result);
29930break;
29931break;
29932case Arg::Addr:
29933case Arg::Stack:
29934case Arg::CallArg:
29935jit.storePtr(args[0].gpr(), args[1].asAddress());
29936OPGEN_RETURN(result);
29937break;
29938break;
29939case Arg::Index:
29940jit.storePtr(args[0].gpr(), args[1].asBaseIndex());
29941OPGEN_RETURN(result);
29942break;
29943break;
29944default:
29945break;
29946}
29947break;
29948case Arg::Imm:
29949switch (this->args[1].kind()) {
29950case Arg::Tmp:
29951jit.signExtend32ToPtr(args[0].asTrustedImm32(), args[1].gpr());
29952OPGEN_RETURN(result);
29953break;
29954break;
29955case Arg::Addr:
29956case Arg::Stack:
29957case Arg::CallArg:
29958#if CPU(X86) || CPU(X86_64)
29959jit.storePtr(args[0].asTrustedImm32(), args[1].asAddress());
29960OPGEN_RETURN(result);
29961#endif
29962break;
29963break;
29964default:
29965break;
29966}
29967break;
29968#if USE(JSVALUE64)
29969case Arg::BigImm:
29970jit.move(args[0].asTrustedImm64(), args[1].gpr());
29971OPGEN_RETURN(result);
29972break;
29973break;
29974#endif // USE(JSVALUE64)
29975case Arg::Addr:
29976case Arg::Stack:
29977case Arg::CallArg:
29978jit.loadPtr(args[0].asAddress(), args[1].gpr());
29979OPGEN_RETURN(result);
29980break;
29981break;
29982case Arg::Index:
29983jit.loadPtr(args[0].asBaseIndex(), args[1].gpr());
29984OPGEN_RETURN(result);
29985break;
29986break;
29987default:
29988break;
29989}
29990break;
29991case 3:
29992jit.move(args[0].asAddress(), args[1].asAddress(), args[2].gpr());
29993OPGEN_RETURN(result);
29994break;
29995break;
29996default:
29997break;
29998}
29999break;
30000case Opcode::Swap32:
30001switch (this->args[1].kind()) {
30002case Arg::Tmp:
30003#if CPU(X86) || CPU(X86_64)
30004jit.swap32(args[0].gpr(), args[1].gpr());
30005OPGEN_RETURN(result);
30006#endif
30007break;
30008break;
30009case Arg::Addr:
30010case Arg::Stack:
30011case Arg::CallArg:
30012#if CPU(X86) || CPU(X86_64)
30013jit.swap32(args[0].gpr(), args[1].asAddress());
30014OPGEN_RETURN(result);
30015#endif
30016break;
30017break;
30018default:
30019break;
30020}
30021break;
30022case Opcode::Swap64:
30023switch (this->args[1].kind()) {
30024case Arg::Tmp:
30025#if CPU(X86_64)
30026jit.swap64(args[0].gpr(), args[1].gpr());
30027OPGEN_RETURN(result);
30028#endif
30029break;
30030break;
30031case Arg::Addr:
30032case Arg::Stack:
30033case Arg::CallArg:
30034#if CPU(X86_64)
30035jit.swap64(args[0].gpr(), args[1].asAddress());
30036OPGEN_RETURN(result);
30037#endif
30038break;
30039break;
30040default:
30041break;
30042}
30043break;
30044case Opcode::Move32:
30045switch (this->args.size()) {
30046case 2:
30047switch (this->args[0].kind()) {
30048case Arg::Tmp:
30049switch (this->args[1].kind()) {
30050case Arg::Tmp:
30051jit.zeroExtend32ToPtr(args[0].gpr(), args[1].gpr());
30052OPGEN_RETURN(result);
30053break;
30054break;
30055case Arg::Addr:
30056case Arg::Stack:
30057case Arg::CallArg:
30058jit.store32(args[0].gpr(), args[1].asAddress());
30059OPGEN_RETURN(result);
30060break;
30061break;
30062case Arg::Index:
30063jit.store32(args[0].gpr(), args[1].asBaseIndex());
30064OPGEN_RETURN(result);
30065break;
30066break;
30067default:
30068break;
30069}
30070break;
30071case Arg::Addr:
30072case Arg::Stack:
30073case Arg::CallArg:
30074jit.load32(args[0].asAddress(), args[1].gpr());
30075OPGEN_RETURN(result);
30076break;
30077break;
30078case Arg::Index:
30079jit.load32(args[0].asBaseIndex(), args[1].gpr());
30080OPGEN_RETURN(result);
30081break;
30082break;
30083case Arg::Imm:
30084switch (this->args[1].kind()) {
30085case Arg::Tmp:
30086#if CPU(X86) || CPU(X86_64)
30087jit.zeroExtend32ToPtr(args[0].asTrustedImm32(), args[1].gpr());
30088OPGEN_RETURN(result);
30089#endif
30090break;
30091break;
30092case Arg::Addr:
30093case Arg::Stack:
30094case Arg::CallArg:
30095#if CPU(X86) || CPU(X86_64)
30096jit.store32(args[0].asTrustedImm32(), args[1].asAddress());
30097OPGEN_RETURN(result);
30098#endif
30099break;
30100break;
30101case Arg::Index:
30102#if CPU(X86) || CPU(X86_64)
30103jit.store32(args[0].asTrustedImm32(), args[1].asBaseIndex());
30104OPGEN_RETURN(result);
30105#endif
30106break;
30107break;
30108default:
30109break;
30110}
30111break;
30112default:
30113break;
30114}
30115break;
30116case 3:
30117jit.move32(args[0].asAddress(), args[1].asAddress(), args[2].gpr());
30118OPGEN_RETURN(result);
30119break;
30120break;
30121default:
30122break;
30123}
30124break;
30125case Opcode::StoreZero32:
30126switch (this->args[0].kind()) {
30127case Arg::Addr:
30128case Arg::Stack:
30129case Arg::CallArg:
30130jit.storeZero32(args[0].asAddress());
30131OPGEN_RETURN(result);
30132break;
30133break;
30134case Arg::Index:
30135jit.storeZero32(args[0].asBaseIndex());
30136OPGEN_RETURN(result);
30137break;
30138break;
30139default:
30140break;
30141}
30142break;
30143case Opcode::StoreZero64:
30144switch (this->args[0].kind()) {
30145case Arg::Addr:
30146case Arg::Stack:
30147case Arg::CallArg:
30148#if CPU(X86_64) || CPU(ARM64)
30149jit.storeZero64(args[0].asAddress());
30150OPGEN_RETURN(result);
30151#endif
30152break;
30153break;
30154case Arg::Index:
30155#if CPU(X86_64) || CPU(ARM64)
30156jit.storeZero64(args[0].asBaseIndex());
30157OPGEN_RETURN(result);
30158#endif
30159break;
30160break;
30161default:
30162break;
30163}
30164break;
30165case Opcode::SignExtend32ToPtr:
30166jit.signExtend32ToPtr(args[0].gpr(), args[1].gpr());
30167OPGEN_RETURN(result);
30168break;
30169break;
30170case Opcode::ZeroExtend8To32:
30171switch (this->args[0].kind()) {
30172case Arg::Tmp:
30173jit.zeroExtend8To32(args[0].gpr(), args[1].gpr());
30174OPGEN_RETURN(result);
30175break;
30176break;
30177case Arg::Addr:
30178case Arg::Stack:
30179case Arg::CallArg:
30180#if CPU(X86) || CPU(X86_64)
30181jit.load8(args[0].asAddress(), args[1].gpr());
30182OPGEN_RETURN(result);
30183#endif
30184break;
30185break;
30186case Arg::Index:
30187#if CPU(X86) || CPU(X86_64)
30188jit.load8(args[0].asBaseIndex(), args[1].gpr());
30189OPGEN_RETURN(result);
30190#endif
30191break;
30192break;
30193default:
30194break;
30195}
30196break;
30197case Opcode::SignExtend8To32:
30198switch (this->args[0].kind()) {
30199case Arg::Tmp:
30200jit.signExtend8To32(args[0].gpr(), args[1].gpr());
30201OPGEN_RETURN(result);
30202break;
30203break;
30204case Arg::Addr:
30205case Arg::Stack:
30206case Arg::CallArg:
30207#if CPU(X86) || CPU(X86_64)
30208jit.load8SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30209OPGEN_RETURN(result);
30210#endif
30211break;
30212break;
30213case Arg::Index:
30214#if CPU(X86) || CPU(X86_64)
30215jit.load8SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30216OPGEN_RETURN(result);
30217#endif
30218break;
30219break;
30220default:
30221break;
30222}
30223break;
30224case Opcode::ZeroExtend16To32:
30225switch (this->args[0].kind()) {
30226case Arg::Tmp:
30227jit.zeroExtend16To32(args[0].gpr(), args[1].gpr());
30228OPGEN_RETURN(result);
30229break;
30230break;
30231case Arg::Addr:
30232case Arg::Stack:
30233case Arg::CallArg:
30234#if CPU(X86) || CPU(X86_64)
30235jit.load16(args[0].asAddress(), args[1].gpr());
30236OPGEN_RETURN(result);
30237#endif
30238break;
30239break;
30240case Arg::Index:
30241#if CPU(X86) || CPU(X86_64)
30242jit.load16(args[0].asBaseIndex(), args[1].gpr());
30243OPGEN_RETURN(result);
30244#endif
30245break;
30246break;
30247default:
30248break;
30249}
30250break;
30251case Opcode::SignExtend16To32:
30252switch (this->args[0].kind()) {
30253case Arg::Tmp:
30254jit.signExtend16To32(args[0].gpr(), args[1].gpr());
30255OPGEN_RETURN(result);
30256break;
30257break;
30258case Arg::Addr:
30259case Arg::Stack:
30260case Arg::CallArg:
30261#if CPU(X86) || CPU(X86_64)
30262jit.load16SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30263OPGEN_RETURN(result);
30264#endif
30265break;
30266break;
30267case Arg::Index:
30268#if CPU(X86) || CPU(X86_64)
30269jit.load16SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30270OPGEN_RETURN(result);
30271#endif
30272break;
30273break;
30274default:
30275break;
30276}
30277break;
30278case Opcode::MoveFloat:
30279switch (this->args.size()) {
30280case 2:
30281switch (this->args[0].kind()) {
30282case Arg::Tmp:
30283switch (this->args[1].kind()) {
30284case Arg::Tmp:
30285jit.moveDouble(args[0].fpr(), args[1].fpr());
30286OPGEN_RETURN(result);
30287break;
30288break;
30289case Arg::Addr:
30290case Arg::Stack:
30291case Arg::CallArg:
30292jit.storeFloat(args[0].fpr(), args[1].asAddress());
30293OPGEN_RETURN(result);
30294break;
30295break;
30296case Arg::Index:
30297jit.storeFloat(args[0].fpr(), args[1].asBaseIndex());
30298OPGEN_RETURN(result);
30299break;
30300break;
30301default:
30302break;
30303}
30304break;
30305case Arg::Addr:
30306case Arg::Stack:
30307case Arg::CallArg:
30308jit.loadFloat(args[0].asAddress(), args[1].fpr());
30309OPGEN_RETURN(result);
30310break;
30311break;
30312case Arg::Index:
30313jit.loadFloat(args[0].asBaseIndex(), args[1].fpr());
30314OPGEN_RETURN(result);
30315break;
30316break;
30317default:
30318break;
30319}
30320break;
30321case 3:
30322jit.moveFloat(args[0].asAddress(), args[1].asAddress(), args[2].fpr());
30323OPGEN_RETURN(result);
30324break;
30325break;
30326default:
30327break;
30328}
30329break;
30330case Opcode::MoveDouble:
30331switch (this->args.size()) {
30332case 2:
30333switch (this->args[0].kind()) {
30334case Arg::Tmp:
30335switch (this->args[1].kind()) {
30336case Arg::Tmp:
30337jit.moveDouble(args[0].fpr(), args[1].fpr());
30338OPGEN_RETURN(result);
30339break;
30340break;
30341case Arg::Addr:
30342case Arg::Stack:
30343case Arg::CallArg:
30344jit.storeDouble(args[0].fpr(), args[1].asAddress());
30345OPGEN_RETURN(result);
30346break;
30347break;
30348case Arg::Index:
30349jit.storeDouble(args[0].fpr(), args[1].asBaseIndex());
30350OPGEN_RETURN(result);
30351break;
30352break;
30353default:
30354break;
30355}
30356break;
30357case Arg::Addr:
30358case Arg::Stack:
30359case Arg::CallArg:
30360jit.loadDouble(args[0].asAddress(), args[1].fpr());
30361OPGEN_RETURN(result);
30362break;
30363break;
30364case Arg::Index:
30365jit.loadDouble(args[0].asBaseIndex(), args[1].fpr());
30366OPGEN_RETURN(result);
30367break;
30368break;
30369default:
30370break;
30371}
30372break;
30373case 3:
30374jit.moveDouble(args[0].asAddress(), args[1].asAddress(), args[2].fpr());
30375OPGEN_RETURN(result);
30376break;
30377break;
30378default:
30379break;
30380}
30381break;
30382case Opcode::MoveZeroToDouble:
30383jit.moveZeroToDouble(args[0].fpr());
30384OPGEN_RETURN(result);
30385break;
30386break;
30387case Opcode::Move64ToDouble:
30388switch (this->args[0].kind()) {
30389case Arg::Tmp:
30390#if CPU(X86_64) || CPU(ARM64)
30391jit.move64ToDouble(args[0].gpr(), args[1].fpr());
30392OPGEN_RETURN(result);
30393#endif
30394break;
30395break;
30396case Arg::Addr:
30397case Arg::Stack:
30398case Arg::CallArg:
30399#if CPU(X86_64)
30400jit.loadDouble(args[0].asAddress(), args[1].fpr());
30401OPGEN_RETURN(result);
30402#endif
30403break;
30404break;
30405case Arg::Index:
30406#if CPU(X86_64) || CPU(ARM64)
30407jit.loadDouble(args[0].asBaseIndex(), args[1].fpr());
30408OPGEN_RETURN(result);
30409#endif
30410break;
30411break;
30412default:
30413break;
30414}
30415break;
30416case Opcode::Move32ToFloat:
30417switch (this->args[0].kind()) {
30418case Arg::Tmp:
30419jit.move32ToFloat(args[0].gpr(), args[1].fpr());
30420OPGEN_RETURN(result);
30421break;
30422break;
30423case Arg::Addr:
30424case Arg::Stack:
30425case Arg::CallArg:
30426#if CPU(X86) || CPU(X86_64)
30427jit.loadFloat(args[0].asAddress(), args[1].fpr());
30428OPGEN_RETURN(result);
30429#endif
30430break;
30431break;
30432case Arg::Index:
30433jit.loadFloat(args[0].asBaseIndex(), args[1].fpr());
30434OPGEN_RETURN(result);
30435break;
30436break;
30437default:
30438break;
30439}
30440break;
30441case Opcode::MoveDoubleTo64:
30442switch (this->args[0].kind()) {
30443case Arg::Tmp:
30444#if CPU(X86_64) || CPU(ARM64)
30445jit.moveDoubleTo64(args[0].fpr(), args[1].gpr());
30446OPGEN_RETURN(result);
30447#endif
30448break;
30449break;
30450case Arg::Addr:
30451case Arg::Stack:
30452case Arg::CallArg:
30453#if CPU(X86_64) || CPU(ARM64)
30454jit.load64(args[0].asAddress(), args[1].gpr());
30455OPGEN_RETURN(result);
30456#endif
30457break;
30458break;
30459case Arg::Index:
30460#if CPU(X86_64) || CPU(ARM64)
30461jit.load64(args[0].asBaseIndex(), args[1].gpr());
30462OPGEN_RETURN(result);
30463#endif
30464break;
30465break;
30466default:
30467break;
30468}
30469break;
30470case Opcode::MoveFloatTo32:
30471switch (this->args[0].kind()) {
30472case Arg::Tmp:
30473jit.moveFloatTo32(args[0].fpr(), args[1].gpr());
30474OPGEN_RETURN(result);
30475break;
30476break;
30477case Arg::Addr:
30478case Arg::Stack:
30479case Arg::CallArg:
30480jit.load32(args[0].asAddress(), args[1].gpr());
30481OPGEN_RETURN(result);
30482break;
30483break;
30484case Arg::Index:
30485jit.load32(args[0].asBaseIndex(), args[1].gpr());
30486OPGEN_RETURN(result);
30487break;
30488break;
30489default:
30490break;
30491}
30492break;
30493case Opcode::Load8:
30494switch (this->args[0].kind()) {
30495case Arg::Addr:
30496case Arg::Stack:
30497case Arg::CallArg:
30498jit.load8(args[0].asAddress(), args[1].gpr());
30499OPGEN_RETURN(result);
30500break;
30501break;
30502case Arg::Index:
30503jit.load8(args[0].asBaseIndex(), args[1].gpr());
30504OPGEN_RETURN(result);
30505break;
30506break;
30507default:
30508break;
30509}
30510break;
30511case Opcode::LoadAcq8:
30512#if CPU(ARMv7) || CPU(ARM64)
30513jit.loadAcq8(args[0].asAddress(), args[1].gpr());
30514OPGEN_RETURN(result);
30515#endif
30516break;
30517break;
30518case Opcode::Store8:
30519switch (this->args[0].kind()) {
30520case Arg::Tmp:
30521switch (this->args[1].kind()) {
30522case Arg::Index:
30523jit.store8(args[0].gpr(), args[1].asBaseIndex());
30524OPGEN_RETURN(result);
30525break;
30526break;
30527case Arg::Addr:
30528case Arg::Stack:
30529case Arg::CallArg:
30530jit.store8(args[0].gpr(), args[1].asAddress());
30531OPGEN_RETURN(result);
30532break;
30533break;
30534default:
30535break;
30536}
30537break;
30538case Arg::Imm:
30539switch (this->args[1].kind()) {
30540case Arg::Index:
30541#if CPU(X86) || CPU(X86_64)
30542jit.store8(args[0].asTrustedImm32(), args[1].asBaseIndex());
30543OPGEN_RETURN(result);
30544#endif
30545break;
30546break;
30547case Arg::Addr:
30548case Arg::Stack:
30549case Arg::CallArg:
30550#if CPU(X86) || CPU(X86_64)
30551jit.store8(args[0].asTrustedImm32(), args[1].asAddress());
30552OPGEN_RETURN(result);
30553#endif
30554break;
30555break;
30556default:
30557break;
30558}
30559break;
30560default:
30561break;
30562}
30563break;
30564case Opcode::StoreRel8:
30565#if CPU(ARMv7) || CPU(ARM64)
30566jit.storeRel8(args[0].gpr(), args[1].asAddress());
30567OPGEN_RETURN(result);
30568#endif
30569break;
30570break;
30571case Opcode::Load8SignedExtendTo32:
30572switch (this->args[0].kind()) {
30573case Arg::Addr:
30574case Arg::Stack:
30575case Arg::CallArg:
30576jit.load8SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30577OPGEN_RETURN(result);
30578break;
30579break;
30580case Arg::Index:
30581jit.load8SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30582OPGEN_RETURN(result);
30583break;
30584break;
30585default:
30586break;
30587}
30588break;
30589case Opcode::LoadAcq8SignedExtendTo32:
30590#if CPU(ARMv7) || CPU(ARM64)
30591jit.loadAcq8SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30592OPGEN_RETURN(result);
30593#endif
30594break;
30595break;
30596case Opcode::Load16:
30597switch (this->args[0].kind()) {
30598case Arg::Addr:
30599case Arg::Stack:
30600case Arg::CallArg:
30601jit.load16(args[0].asAddress(), args[1].gpr());
30602OPGEN_RETURN(result);
30603break;
30604break;
30605case Arg::Index:
30606jit.load16(args[0].asBaseIndex(), args[1].gpr());
30607OPGEN_RETURN(result);
30608break;
30609break;
30610default:
30611break;
30612}
30613break;
30614case Opcode::LoadAcq16:
30615#if CPU(ARMv7) || CPU(ARM64)
30616jit.loadAcq16(args[0].asAddress(), args[1].gpr());
30617OPGEN_RETURN(result);
30618#endif
30619break;
30620break;
30621case Opcode::Load16SignedExtendTo32:
30622switch (this->args[0].kind()) {
30623case Arg::Addr:
30624case Arg::Stack:
30625case Arg::CallArg:
30626jit.load16SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30627OPGEN_RETURN(result);
30628break;
30629break;
30630case Arg::Index:
30631jit.load16SignedExtendTo32(args[0].asBaseIndex(), args[1].gpr());
30632OPGEN_RETURN(result);
30633break;
30634break;
30635default:
30636break;
30637}
30638break;
30639case Opcode::LoadAcq16SignedExtendTo32:
30640#if CPU(ARMv7) || CPU(ARM64)
30641jit.loadAcq16SignedExtendTo32(args[0].asAddress(), args[1].gpr());
30642OPGEN_RETURN(result);
30643#endif
30644break;
30645break;
30646case Opcode::Store16:
30647switch (this->args[0].kind()) {
30648case Arg::Tmp:
30649switch (this->args[1].kind()) {
30650case Arg::Index:
30651jit.store16(args[0].gpr(), args[1].asBaseIndex());
30652OPGEN_RETURN(result);
30653break;
30654break;
30655case Arg::Addr:
30656case Arg::Stack:
30657case Arg::CallArg:
30658jit.store16(args[0].gpr(), args[1].asAddress());
30659OPGEN_RETURN(result);
30660break;
30661break;
30662default:
30663break;
30664}
30665break;
30666case Arg::Imm:
30667switch (this->args[1].kind()) {
30668case Arg::Index:
30669#if CPU(X86) || CPU(X86_64)
30670jit.store16(args[0].asTrustedImm32(), args[1].asBaseIndex());
30671OPGEN_RETURN(result);
30672#endif
30673break;
30674break;
30675case Arg::Addr:
30676case Arg::Stack:
30677case Arg::CallArg:
30678#if CPU(X86) || CPU(X86_64)
30679jit.store16(args[0].asTrustedImm32(), args[1].asAddress());
30680OPGEN_RETURN(result);
30681#endif
30682break;
30683break;
30684default:
30685break;
30686}
30687break;
30688default:
30689break;
30690}
30691break;
30692case Opcode::StoreRel16:
30693#if CPU(ARMv7) || CPU(ARM64)
30694jit.storeRel16(args[0].gpr(), args[1].asAddress());
30695OPGEN_RETURN(result);
30696#endif
30697break;
30698break;
30699case Opcode::LoadAcq32:
30700#if CPU(ARMv7) || CPU(ARM64)
30701jit.loadAcq32(args[0].asAddress(), args[1].gpr());
30702OPGEN_RETURN(result);
30703#endif
30704break;
30705break;
30706case Opcode::StoreRel32:
30707#if CPU(ARMv7) || CPU(ARM64)
30708jit.storeRel32(args[0].gpr(), args[1].asAddress());
30709OPGEN_RETURN(result);
30710#endif
30711break;
30712break;
30713case Opcode::LoadAcq64:
30714#if CPU(ARM64)
30715jit.loadAcq64(args[0].asAddress(), args[1].gpr());
30716OPGEN_RETURN(result);
30717#endif
30718break;
30719break;
30720case Opcode::StoreRel64:
30721#if CPU(ARM64)
30722jit.storeRel64(args[0].gpr(), args[1].asAddress());
30723OPGEN_RETURN(result);
30724#endif
30725break;
30726break;
30727case Opcode::Xchg8:
30728switch (this->args[1].kind()) {
30729case Arg::Addr:
30730case Arg::Stack:
30731case Arg::CallArg:
30732#if CPU(X86) || CPU(X86_64)
30733jit.xchg8(args[0].gpr(), args[1].asAddress());
30734OPGEN_RETURN(result);
30735#endif
30736break;
30737break;
30738case Arg::Index:
30739#if CPU(X86) || CPU(X86_64)
30740jit.xchg8(args[0].gpr(), args[1].asBaseIndex());
30741OPGEN_RETURN(result);
30742#endif
30743break;
30744break;
30745default:
30746break;
30747}
30748break;
30749case Opcode::Xchg16:
30750switch (this->args[1].kind()) {
30751case Arg::Addr:
30752case Arg::Stack:
30753case Arg::CallArg:
30754#if CPU(X86) || CPU(X86_64)
30755jit.xchg16(args[0].gpr(), args[1].asAddress());
30756OPGEN_RETURN(result);
30757#endif
30758break;
30759break;
30760case Arg::Index:
30761#if CPU(X86) || CPU(X86_64)
30762jit.xchg16(args[0].gpr(), args[1].asBaseIndex());
30763OPGEN_RETURN(result);
30764#endif
30765break;
30766break;
30767default:
30768break;
30769}
30770break;
30771case Opcode::Xchg32:
30772switch (this->args[1].kind()) {
30773case Arg::Addr:
30774case Arg::Stack:
30775case Arg::CallArg:
30776#if CPU(X86) || CPU(X86_64)
30777jit.xchg32(args[0].gpr(), args[1].asAddress());
30778OPGEN_RETURN(result);
30779#endif
30780break;
30781break;
30782case Arg::Index:
30783#if CPU(X86) || CPU(X86_64)
30784jit.xchg32(args[0].gpr(), args[1].asBaseIndex());
30785OPGEN_RETURN(result);
30786#endif
30787break;
30788break;
30789default:
30790break;
30791}
30792break;
30793case Opcode::Xchg64:
30794switch (this->args[1].kind()) {
30795case Arg::Addr:
30796case Arg::Stack:
30797case Arg::CallArg:
30798#if CPU(X86_64)
30799jit.xchg64(args[0].gpr(), args[1].asAddress());
30800OPGEN_RETURN(result);
30801#endif
30802break;
30803break;
30804case Arg::Index:
30805#if CPU(X86_64)
30806jit.xchg64(args[0].gpr(), args[1].asBaseIndex());
30807OPGEN_RETURN(result);
30808#endif
30809break;
30810break;
30811default:
30812break;
30813}
30814break;
30815case Opcode::AtomicStrongCAS8:
30816switch (this->args.size()) {
30817case 5:
30818switch (this->args[3].kind()) {
30819case Arg::Addr:
30820case Arg::Stack:
30821case Arg::CallArg:
30822#if CPU(X86) || CPU(X86_64)
30823jit.atomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
30824OPGEN_RETURN(result);
30825#endif
30826break;
30827break;
30828case Arg::Index:
30829#if CPU(X86) || CPU(X86_64)
30830jit.atomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
30831OPGEN_RETURN(result);
30832#endif
30833break;
30834break;
30835default:
30836break;
30837}
30838break;
30839case 3:
30840switch (this->args[2].kind()) {
30841case Arg::Addr:
30842case Arg::Stack:
30843case Arg::CallArg:
30844#if CPU(X86) || CPU(X86_64)
30845jit.atomicStrongCAS8(args[0].gpr(), args[1].gpr(), args[2].asAddress());
30846OPGEN_RETURN(result);
30847#endif
30848break;
30849break;
30850case Arg::Index:
30851#if CPU(X86) || CPU(X86_64)
30852jit.atomicStrongCAS8(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
30853OPGEN_RETURN(result);
30854#endif
30855break;
30856break;
30857default:
30858break;
30859}
30860break;
30861default:
30862break;
30863}
30864break;
30865case Opcode::AtomicStrongCAS16:
30866switch (this->args.size()) {
30867case 5:
30868switch (this->args[3].kind()) {
30869case Arg::Addr:
30870case Arg::Stack:
30871case Arg::CallArg:
30872#if CPU(X86) || CPU(X86_64)
30873jit.atomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
30874OPGEN_RETURN(result);
30875#endif
30876break;
30877break;
30878case Arg::Index:
30879#if CPU(X86) || CPU(X86_64)
30880jit.atomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
30881OPGEN_RETURN(result);
30882#endif
30883break;
30884break;
30885default:
30886break;
30887}
30888break;
30889case 3:
30890switch (this->args[2].kind()) {
30891case Arg::Addr:
30892case Arg::Stack:
30893case Arg::CallArg:
30894#if CPU(X86) || CPU(X86_64)
30895jit.atomicStrongCAS16(args[0].gpr(), args[1].gpr(), args[2].asAddress());
30896OPGEN_RETURN(result);
30897#endif
30898break;
30899break;
30900case Arg::Index:
30901#if CPU(X86) || CPU(X86_64)
30902jit.atomicStrongCAS16(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
30903OPGEN_RETURN(result);
30904#endif
30905break;
30906break;
30907default:
30908break;
30909}
30910break;
30911default:
30912break;
30913}
30914break;
30915case Opcode::AtomicStrongCAS32:
30916switch (this->args.size()) {
30917case 5:
30918switch (this->args[3].kind()) {
30919case Arg::Addr:
30920case Arg::Stack:
30921case Arg::CallArg:
30922#if CPU(X86) || CPU(X86_64)
30923jit.atomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
30924OPGEN_RETURN(result);
30925#endif
30926break;
30927break;
30928case Arg::Index:
30929#if CPU(X86) || CPU(X86_64)
30930jit.atomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
30931OPGEN_RETURN(result);
30932#endif
30933break;
30934break;
30935default:
30936break;
30937}
30938break;
30939case 3:
30940switch (this->args[2].kind()) {
30941case Arg::Addr:
30942case Arg::Stack:
30943case Arg::CallArg:
30944#if CPU(X86) || CPU(X86_64)
30945jit.atomicStrongCAS32(args[0].gpr(), args[1].gpr(), args[2].asAddress());
30946OPGEN_RETURN(result);
30947#endif
30948break;
30949break;
30950case Arg::Index:
30951#if CPU(X86) || CPU(X86_64)
30952jit.atomicStrongCAS32(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
30953OPGEN_RETURN(result);
30954#endif
30955break;
30956break;
30957default:
30958break;
30959}
30960break;
30961default:
30962break;
30963}
30964break;
30965case Opcode::AtomicStrongCAS64:
30966switch (this->args.size()) {
30967case 5:
30968switch (this->args[3].kind()) {
30969case Arg::Addr:
30970case Arg::Stack:
30971case Arg::CallArg:
30972#if CPU(X86_64)
30973jit.atomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress(), args[4].gpr());
30974OPGEN_RETURN(result);
30975#endif
30976break;
30977break;
30978case Arg::Index:
30979#if CPU(X86_64)
30980jit.atomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex(), args[4].gpr());
30981OPGEN_RETURN(result);
30982#endif
30983break;
30984break;
30985default:
30986break;
30987}
30988break;
30989case 3:
30990switch (this->args[2].kind()) {
30991case Arg::Addr:
30992case Arg::Stack:
30993case Arg::CallArg:
30994#if CPU(X86_64)
30995jit.atomicStrongCAS64(args[0].gpr(), args[1].gpr(), args[2].asAddress());
30996OPGEN_RETURN(result);
30997#endif
30998break;
30999break;
31000case Arg::Index:
31001#if CPU(X86_64)
31002jit.atomicStrongCAS64(args[0].gpr(), args[1].gpr(), args[2].asBaseIndex());
31003OPGEN_RETURN(result);
31004#endif
31005break;
31006break;
31007default:
31008break;
31009}
31010break;
31011default:
31012break;
31013}
31014break;
31015case Opcode::BranchAtomicStrongCAS8:
31016switch (this->args[3].kind()) {
31017case Arg::Addr:
31018case Arg::Stack:
31019case Arg::CallArg:
31020#if CPU(X86) || CPU(X86_64)
31021result = jit.branchAtomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31022OPGEN_RETURN(result);
31023#endif
31024break;
31025break;
31026case Arg::Index:
31027#if CPU(X86) || CPU(X86_64)
31028result = jit.branchAtomicStrongCAS8(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31029OPGEN_RETURN(result);
31030#endif
31031break;
31032break;
31033default:
31034break;
31035}
31036break;
31037case Opcode::BranchAtomicStrongCAS16:
31038switch (this->args[3].kind()) {
31039case Arg::Addr:
31040case Arg::Stack:
31041case Arg::CallArg:
31042#if CPU(X86) || CPU(X86_64)
31043result = jit.branchAtomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31044OPGEN_RETURN(result);
31045#endif
31046break;
31047break;
31048case Arg::Index:
31049#if CPU(X86) || CPU(X86_64)
31050result = jit.branchAtomicStrongCAS16(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31051OPGEN_RETURN(result);
31052#endif
31053break;
31054break;
31055default:
31056break;
31057}
31058break;
31059case Opcode::BranchAtomicStrongCAS32:
31060switch (this->args[3].kind()) {
31061case Arg::Addr:
31062case Arg::Stack:
31063case Arg::CallArg:
31064#if CPU(X86) || CPU(X86_64)
31065result = jit.branchAtomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31066OPGEN_RETURN(result);
31067#endif
31068break;
31069break;
31070case Arg::Index:
31071#if CPU(X86) || CPU(X86_64)
31072result = jit.branchAtomicStrongCAS32(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31073OPGEN_RETURN(result);
31074#endif
31075break;
31076break;
31077default:
31078break;
31079}
31080break;
31081case Opcode::BranchAtomicStrongCAS64:
31082switch (this->args[3].kind()) {
31083case Arg::Addr:
31084case Arg::Stack:
31085case Arg::CallArg:
31086#if CPU(X86_64)
31087result = jit.branchAtomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asAddress());
31088OPGEN_RETURN(result);
31089#endif
31090break;
31091break;
31092case Arg::Index:
31093#if CPU(X86_64)
31094result = jit.branchAtomicStrongCAS64(args[0].asStatusCondition(), args[1].gpr(), args[2].gpr(), args[3].asBaseIndex());
31095OPGEN_RETURN(result);
31096#endif
31097break;
31098break;
31099default:
31100break;
31101}
31102break;
31103case Opcode::AtomicAdd8:
31104switch (this->args[0].kind()) {
31105case Arg::Imm:
31106switch (this->args[1].kind()) {
31107case Arg::Addr:
31108case Arg::Stack:
31109case Arg::CallArg:
31110#if CPU(X86) || CPU(X86_64)
31111jit.atomicAdd8(args[0].asTrustedImm32(), args[1].asAddress());
31112OPGEN_RETURN(result);
31113#endif
31114break;
31115break;
31116case Arg::Index:
31117#if CPU(X86) || CPU(X86_64)
31118jit.atomicAdd8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31119OPGEN_RETURN(result);
31120#endif
31121break;
31122break;
31123default:
31124break;
31125}
31126break;
31127case Arg::Tmp:
31128switch (this->args[1].kind()) {
31129case Arg::Addr:
31130case Arg::Stack:
31131case Arg::CallArg:
31132#if CPU(X86) || CPU(X86_64)
31133jit.atomicAdd8(args[0].gpr(), args[1].asAddress());
31134OPGEN_RETURN(result);
31135#endif
31136break;
31137break;
31138case Arg::Index:
31139#if CPU(X86) || CPU(X86_64)
31140jit.atomicAdd8(args[0].gpr(), args[1].asBaseIndex());
31141OPGEN_RETURN(result);
31142#endif
31143break;
31144break;
31145default:
31146break;
31147}
31148break;
31149default:
31150break;
31151}
31152break;
31153case Opcode::AtomicAdd16:
31154switch (this->args[0].kind()) {
31155case Arg::Imm:
31156switch (this->args[1].kind()) {
31157case Arg::Addr:
31158case Arg::Stack:
31159case Arg::CallArg:
31160#if CPU(X86) || CPU(X86_64)
31161jit.atomicAdd16(args[0].asTrustedImm32(), args[1].asAddress());
31162OPGEN_RETURN(result);
31163#endif
31164break;
31165break;
31166case Arg::Index:
31167#if CPU(X86) || CPU(X86_64)
31168jit.atomicAdd16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31169OPGEN_RETURN(result);
31170#endif
31171break;
31172break;
31173default:
31174break;
31175}
31176break;
31177case Arg::Tmp:
31178switch (this->args[1].kind()) {
31179case Arg::Addr:
31180case Arg::Stack:
31181case Arg::CallArg:
31182#if CPU(X86) || CPU(X86_64)
31183jit.atomicAdd16(args[0].gpr(), args[1].asAddress());
31184OPGEN_RETURN(result);
31185#endif
31186break;
31187break;
31188case Arg::Index:
31189#if CPU(X86) || CPU(X86_64)
31190jit.atomicAdd16(args[0].gpr(), args[1].asBaseIndex());
31191OPGEN_RETURN(result);
31192#endif
31193break;
31194break;
31195default:
31196break;
31197}
31198break;
31199default:
31200break;
31201}
31202break;
31203case Opcode::AtomicAdd32:
31204switch (this->args[0].kind()) {
31205case Arg::Imm:
31206switch (this->args[1].kind()) {
31207case Arg::Addr:
31208case Arg::Stack:
31209case Arg::CallArg:
31210#if CPU(X86) || CPU(X86_64)
31211jit.atomicAdd32(args[0].asTrustedImm32(), args[1].asAddress());
31212OPGEN_RETURN(result);
31213#endif
31214break;
31215break;
31216case Arg::Index:
31217#if CPU(X86) || CPU(X86_64)
31218jit.atomicAdd32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31219OPGEN_RETURN(result);
31220#endif
31221break;
31222break;
31223default:
31224break;
31225}
31226break;
31227case Arg::Tmp:
31228switch (this->args[1].kind()) {
31229case Arg::Addr:
31230case Arg::Stack:
31231case Arg::CallArg:
31232#if CPU(X86) || CPU(X86_64)
31233jit.atomicAdd32(args[0].gpr(), args[1].asAddress());
31234OPGEN_RETURN(result);
31235#endif
31236break;
31237break;
31238case Arg::Index:
31239#if CPU(X86) || CPU(X86_64)
31240jit.atomicAdd32(args[0].gpr(), args[1].asBaseIndex());
31241OPGEN_RETURN(result);
31242#endif
31243break;
31244break;
31245default:
31246break;
31247}
31248break;
31249default:
31250break;
31251}
31252break;
31253case Opcode::AtomicAdd64:
31254switch (this->args[0].kind()) {
31255case Arg::Imm:
31256switch (this->args[1].kind()) {
31257case Arg::Addr:
31258case Arg::Stack:
31259case Arg::CallArg:
31260#if CPU(X86_64)
31261jit.atomicAdd64(args[0].asTrustedImm32(), args[1].asAddress());
31262OPGEN_RETURN(result);
31263#endif
31264break;
31265break;
31266case Arg::Index:
31267#if CPU(X86_64)
31268jit.atomicAdd64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31269OPGEN_RETURN(result);
31270#endif
31271break;
31272break;
31273default:
31274break;
31275}
31276break;
31277case Arg::Tmp:
31278switch (this->args[1].kind()) {
31279case Arg::Addr:
31280case Arg::Stack:
31281case Arg::CallArg:
31282#if CPU(X86_64)
31283jit.atomicAdd64(args[0].gpr(), args[1].asAddress());
31284OPGEN_RETURN(result);
31285#endif
31286break;
31287break;
31288case Arg::Index:
31289#if CPU(X86_64)
31290jit.atomicAdd64(args[0].gpr(), args[1].asBaseIndex());
31291OPGEN_RETURN(result);
31292#endif
31293break;
31294break;
31295default:
31296break;
31297}
31298break;
31299default:
31300break;
31301}
31302break;
31303case Opcode::AtomicSub8:
31304switch (this->args[0].kind()) {
31305case Arg::Imm:
31306switch (this->args[1].kind()) {
31307case Arg::Addr:
31308case Arg::Stack:
31309case Arg::CallArg:
31310#if CPU(X86) || CPU(X86_64)
31311jit.atomicSub8(args[0].asTrustedImm32(), args[1].asAddress());
31312OPGEN_RETURN(result);
31313#endif
31314break;
31315break;
31316case Arg::Index:
31317#if CPU(X86) || CPU(X86_64)
31318jit.atomicSub8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31319OPGEN_RETURN(result);
31320#endif
31321break;
31322break;
31323default:
31324break;
31325}
31326break;
31327case Arg::Tmp:
31328switch (this->args[1].kind()) {
31329case Arg::Addr:
31330case Arg::Stack:
31331case Arg::CallArg:
31332#if CPU(X86) || CPU(X86_64)
31333jit.atomicSub8(args[0].gpr(), args[1].asAddress());
31334OPGEN_RETURN(result);
31335#endif
31336break;
31337break;
31338case Arg::Index:
31339#if CPU(X86) || CPU(X86_64)
31340jit.atomicSub8(args[0].gpr(), args[1].asBaseIndex());
31341OPGEN_RETURN(result);
31342#endif
31343break;
31344break;
31345default:
31346break;
31347}
31348break;
31349default:
31350break;
31351}
31352break;
31353case Opcode::AtomicSub16:
31354switch (this->args[0].kind()) {
31355case Arg::Imm:
31356switch (this->args[1].kind()) {
31357case Arg::Addr:
31358case Arg::Stack:
31359case Arg::CallArg:
31360#if CPU(X86) || CPU(X86_64)
31361jit.atomicSub16(args[0].asTrustedImm32(), args[1].asAddress());
31362OPGEN_RETURN(result);
31363#endif
31364break;
31365break;
31366case Arg::Index:
31367#if CPU(X86) || CPU(X86_64)
31368jit.atomicSub16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31369OPGEN_RETURN(result);
31370#endif
31371break;
31372break;
31373default:
31374break;
31375}
31376break;
31377case Arg::Tmp:
31378switch (this->args[1].kind()) {
31379case Arg::Addr:
31380case Arg::Stack:
31381case Arg::CallArg:
31382#if CPU(X86) || CPU(X86_64)
31383jit.atomicSub16(args[0].gpr(), args[1].asAddress());
31384OPGEN_RETURN(result);
31385#endif
31386break;
31387break;
31388case Arg::Index:
31389#if CPU(X86) || CPU(X86_64)
31390jit.atomicSub16(args[0].gpr(), args[1].asBaseIndex());
31391OPGEN_RETURN(result);
31392#endif
31393break;
31394break;
31395default:
31396break;
31397}
31398break;
31399default:
31400break;
31401}
31402break;
31403case Opcode::AtomicSub32:
31404switch (this->args[0].kind()) {
31405case Arg::Imm:
31406switch (this->args[1].kind()) {
31407case Arg::Addr:
31408case Arg::Stack:
31409case Arg::CallArg:
31410#if CPU(X86) || CPU(X86_64)
31411jit.atomicSub32(args[0].asTrustedImm32(), args[1].asAddress());
31412OPGEN_RETURN(result);
31413#endif
31414break;
31415break;
31416case Arg::Index:
31417#if CPU(X86) || CPU(X86_64)
31418jit.atomicSub32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31419OPGEN_RETURN(result);
31420#endif
31421break;
31422break;
31423default:
31424break;
31425}
31426break;
31427case Arg::Tmp:
31428switch (this->args[1].kind()) {
31429case Arg::Addr:
31430case Arg::Stack:
31431case Arg::CallArg:
31432#if CPU(X86) || CPU(X86_64)
31433jit.atomicSub32(args[0].gpr(), args[1].asAddress());
31434OPGEN_RETURN(result);
31435#endif
31436break;
31437break;
31438case Arg::Index:
31439#if CPU(X86) || CPU(X86_64)
31440jit.atomicSub32(args[0].gpr(), args[1].asBaseIndex());
31441OPGEN_RETURN(result);
31442#endif
31443break;
31444break;
31445default:
31446break;
31447}
31448break;
31449default:
31450break;
31451}
31452break;
31453case Opcode::AtomicSub64:
31454switch (this->args[0].kind()) {
31455case Arg::Imm:
31456switch (this->args[1].kind()) {
31457case Arg::Addr:
31458case Arg::Stack:
31459case Arg::CallArg:
31460#if CPU(X86_64)
31461jit.atomicSub64(args[0].asTrustedImm32(), args[1].asAddress());
31462OPGEN_RETURN(result);
31463#endif
31464break;
31465break;
31466case Arg::Index:
31467#if CPU(X86_64)
31468jit.atomicSub64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31469OPGEN_RETURN(result);
31470#endif
31471break;
31472break;
31473default:
31474break;
31475}
31476break;
31477case Arg::Tmp:
31478switch (this->args[1].kind()) {
31479case Arg::Addr:
31480case Arg::Stack:
31481case Arg::CallArg:
31482#if CPU(X86_64)
31483jit.atomicSub64(args[0].gpr(), args[1].asAddress());
31484OPGEN_RETURN(result);
31485#endif
31486break;
31487break;
31488case Arg::Index:
31489#if CPU(X86_64)
31490jit.atomicSub64(args[0].gpr(), args[1].asBaseIndex());
31491OPGEN_RETURN(result);
31492#endif
31493break;
31494break;
31495default:
31496break;
31497}
31498break;
31499default:
31500break;
31501}
31502break;
31503case Opcode::AtomicAnd8:
31504switch (this->args[0].kind()) {
31505case Arg::Imm:
31506switch (this->args[1].kind()) {
31507case Arg::Addr:
31508case Arg::Stack:
31509case Arg::CallArg:
31510#if CPU(X86) || CPU(X86_64)
31511jit.atomicAnd8(args[0].asTrustedImm32(), args[1].asAddress());
31512OPGEN_RETURN(result);
31513#endif
31514break;
31515break;
31516case Arg::Index:
31517#if CPU(X86) || CPU(X86_64)
31518jit.atomicAnd8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31519OPGEN_RETURN(result);
31520#endif
31521break;
31522break;
31523default:
31524break;
31525}
31526break;
31527case Arg::Tmp:
31528switch (this->args[1].kind()) {
31529case Arg::Addr:
31530case Arg::Stack:
31531case Arg::CallArg:
31532#if CPU(X86) || CPU(X86_64)
31533jit.atomicAnd8(args[0].gpr(), args[1].asAddress());
31534OPGEN_RETURN(result);
31535#endif
31536break;
31537break;
31538case Arg::Index:
31539#if CPU(X86) || CPU(X86_64)
31540jit.atomicAnd8(args[0].gpr(), args[1].asBaseIndex());
31541OPGEN_RETURN(result);
31542#endif
31543break;
31544break;
31545default:
31546break;
31547}
31548break;
31549default:
31550break;
31551}
31552break;
31553case Opcode::AtomicAnd16:
31554switch (this->args[0].kind()) {
31555case Arg::Imm:
31556switch (this->args[1].kind()) {
31557case Arg::Addr:
31558case Arg::Stack:
31559case Arg::CallArg:
31560#if CPU(X86) || CPU(X86_64)
31561jit.atomicAnd16(args[0].asTrustedImm32(), args[1].asAddress());
31562OPGEN_RETURN(result);
31563#endif
31564break;
31565break;
31566case Arg::Index:
31567#if CPU(X86) || CPU(X86_64)
31568jit.atomicAnd16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31569OPGEN_RETURN(result);
31570#endif
31571break;
31572break;
31573default:
31574break;
31575}
31576break;
31577case Arg::Tmp:
31578switch (this->args[1].kind()) {
31579case Arg::Addr:
31580case Arg::Stack:
31581case Arg::CallArg:
31582#if CPU(X86) || CPU(X86_64)
31583jit.atomicAnd16(args[0].gpr(), args[1].asAddress());
31584OPGEN_RETURN(result);
31585#endif
31586break;
31587break;
31588case Arg::Index:
31589#if CPU(X86) || CPU(X86_64)
31590jit.atomicAnd16(args[0].gpr(), args[1].asBaseIndex());
31591OPGEN_RETURN(result);
31592#endif
31593break;
31594break;
31595default:
31596break;
31597}
31598break;
31599default:
31600break;
31601}
31602break;
31603case Opcode::AtomicAnd32:
31604switch (this->args[0].kind()) {
31605case Arg::Imm:
31606switch (this->args[1].kind()) {
31607case Arg::Addr:
31608case Arg::Stack:
31609case Arg::CallArg:
31610#if CPU(X86) || CPU(X86_64)
31611jit.atomicAnd32(args[0].asTrustedImm32(), args[1].asAddress());
31612OPGEN_RETURN(result);
31613#endif
31614break;
31615break;
31616case Arg::Index:
31617#if CPU(X86) || CPU(X86_64)
31618jit.atomicAnd32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31619OPGEN_RETURN(result);
31620#endif
31621break;
31622break;
31623default:
31624break;
31625}
31626break;
31627case Arg::Tmp:
31628switch (this->args[1].kind()) {
31629case Arg::Addr:
31630case Arg::Stack:
31631case Arg::CallArg:
31632#if CPU(X86) || CPU(X86_64)
31633jit.atomicAnd32(args[0].gpr(), args[1].asAddress());
31634OPGEN_RETURN(result);
31635#endif
31636break;
31637break;
31638case Arg::Index:
31639#if CPU(X86) || CPU(X86_64)
31640jit.atomicAnd32(args[0].gpr(), args[1].asBaseIndex());
31641OPGEN_RETURN(result);
31642#endif
31643break;
31644break;
31645default:
31646break;
31647}
31648break;
31649default:
31650break;
31651}
31652break;
31653case Opcode::AtomicAnd64:
31654switch (this->args[0].kind()) {
31655case Arg::Imm:
31656switch (this->args[1].kind()) {
31657case Arg::Addr:
31658case Arg::Stack:
31659case Arg::CallArg:
31660#if CPU(X86_64)
31661jit.atomicAnd64(args[0].asTrustedImm32(), args[1].asAddress());
31662OPGEN_RETURN(result);
31663#endif
31664break;
31665break;
31666case Arg::Index:
31667#if CPU(X86_64)
31668jit.atomicAnd64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31669OPGEN_RETURN(result);
31670#endif
31671break;
31672break;
31673default:
31674break;
31675}
31676break;
31677case Arg::Tmp:
31678switch (this->args[1].kind()) {
31679case Arg::Addr:
31680case Arg::Stack:
31681case Arg::CallArg:
31682#if CPU(X86_64)
31683jit.atomicAnd64(args[0].gpr(), args[1].asAddress());
31684OPGEN_RETURN(result);
31685#endif
31686break;
31687break;
31688case Arg::Index:
31689#if CPU(X86_64)
31690jit.atomicAnd64(args[0].gpr(), args[1].asBaseIndex());
31691OPGEN_RETURN(result);
31692#endif
31693break;
31694break;
31695default:
31696break;
31697}
31698break;
31699default:
31700break;
31701}
31702break;
31703case Opcode::AtomicOr8:
31704switch (this->args[0].kind()) {
31705case Arg::Imm:
31706switch (this->args[1].kind()) {
31707case Arg::Addr:
31708case Arg::Stack:
31709case Arg::CallArg:
31710#if CPU(X86) || CPU(X86_64)
31711jit.atomicOr8(args[0].asTrustedImm32(), args[1].asAddress());
31712OPGEN_RETURN(result);
31713#endif
31714break;
31715break;
31716case Arg::Index:
31717#if CPU(X86) || CPU(X86_64)
31718jit.atomicOr8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31719OPGEN_RETURN(result);
31720#endif
31721break;
31722break;
31723default:
31724break;
31725}
31726break;
31727case Arg::Tmp:
31728switch (this->args[1].kind()) {
31729case Arg::Addr:
31730case Arg::Stack:
31731case Arg::CallArg:
31732#if CPU(X86) || CPU(X86_64)
31733jit.atomicOr8(args[0].gpr(), args[1].asAddress());
31734OPGEN_RETURN(result);
31735#endif
31736break;
31737break;
31738case Arg::Index:
31739#if CPU(X86) || CPU(X86_64)
31740jit.atomicOr8(args[0].gpr(), args[1].asBaseIndex());
31741OPGEN_RETURN(result);
31742#endif
31743break;
31744break;
31745default:
31746break;
31747}
31748break;
31749default:
31750break;
31751}
31752break;
31753case Opcode::AtomicOr16:
31754switch (this->args[0].kind()) {
31755case Arg::Imm:
31756switch (this->args[1].kind()) {
31757case Arg::Addr:
31758case Arg::Stack:
31759case Arg::CallArg:
31760#if CPU(X86) || CPU(X86_64)
31761jit.atomicOr16(args[0].asTrustedImm32(), args[1].asAddress());
31762OPGEN_RETURN(result);
31763#endif
31764break;
31765break;
31766case Arg::Index:
31767#if CPU(X86) || CPU(X86_64)
31768jit.atomicOr16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31769OPGEN_RETURN(result);
31770#endif
31771break;
31772break;
31773default:
31774break;
31775}
31776break;
31777case Arg::Tmp:
31778switch (this->args[1].kind()) {
31779case Arg::Addr:
31780case Arg::Stack:
31781case Arg::CallArg:
31782#if CPU(X86) || CPU(X86_64)
31783jit.atomicOr16(args[0].gpr(), args[1].asAddress());
31784OPGEN_RETURN(result);
31785#endif
31786break;
31787break;
31788case Arg::Index:
31789#if CPU(X86) || CPU(X86_64)
31790jit.atomicOr16(args[0].gpr(), args[1].asBaseIndex());
31791OPGEN_RETURN(result);
31792#endif
31793break;
31794break;
31795default:
31796break;
31797}
31798break;
31799default:
31800break;
31801}
31802break;
31803case Opcode::AtomicOr32:
31804switch (this->args[0].kind()) {
31805case Arg::Imm:
31806switch (this->args[1].kind()) {
31807case Arg::Addr:
31808case Arg::Stack:
31809case Arg::CallArg:
31810#if CPU(X86) || CPU(X86_64)
31811jit.atomicOr32(args[0].asTrustedImm32(), args[1].asAddress());
31812OPGEN_RETURN(result);
31813#endif
31814break;
31815break;
31816case Arg::Index:
31817#if CPU(X86) || CPU(X86_64)
31818jit.atomicOr32(args[0].asTrustedImm32(), args[1].asBaseIndex());
31819OPGEN_RETURN(result);
31820#endif
31821break;
31822break;
31823default:
31824break;
31825}
31826break;
31827case Arg::Tmp:
31828switch (this->args[1].kind()) {
31829case Arg::Addr:
31830case Arg::Stack:
31831case Arg::CallArg:
31832#if CPU(X86) || CPU(X86_64)
31833jit.atomicOr32(args[0].gpr(), args[1].asAddress());
31834OPGEN_RETURN(result);
31835#endif
31836break;
31837break;
31838case Arg::Index:
31839#if CPU(X86) || CPU(X86_64)
31840jit.atomicOr32(args[0].gpr(), args[1].asBaseIndex());
31841OPGEN_RETURN(result);
31842#endif
31843break;
31844break;
31845default:
31846break;
31847}
31848break;
31849default:
31850break;
31851}
31852break;
31853case Opcode::AtomicOr64:
31854switch (this->args[0].kind()) {
31855case Arg::Imm:
31856switch (this->args[1].kind()) {
31857case Arg::Addr:
31858case Arg::Stack:
31859case Arg::CallArg:
31860#if CPU(X86_64)
31861jit.atomicOr64(args[0].asTrustedImm32(), args[1].asAddress());
31862OPGEN_RETURN(result);
31863#endif
31864break;
31865break;
31866case Arg::Index:
31867#if CPU(X86_64)
31868jit.atomicOr64(args[0].asTrustedImm32(), args[1].asBaseIndex());
31869OPGEN_RETURN(result);
31870#endif
31871break;
31872break;
31873default:
31874break;
31875}
31876break;
31877case Arg::Tmp:
31878switch (this->args[1].kind()) {
31879case Arg::Addr:
31880case Arg::Stack:
31881case Arg::CallArg:
31882#if CPU(X86_64)
31883jit.atomicOr64(args[0].gpr(), args[1].asAddress());
31884OPGEN_RETURN(result);
31885#endif
31886break;
31887break;
31888case Arg::Index:
31889#if CPU(X86_64)
31890jit.atomicOr64(args[0].gpr(), args[1].asBaseIndex());
31891OPGEN_RETURN(result);
31892#endif
31893break;
31894break;
31895default:
31896break;
31897}
31898break;
31899default:
31900break;
31901}
31902break;
31903case Opcode::AtomicXor8:
31904switch (this->args[0].kind()) {
31905case Arg::Imm:
31906switch (this->args[1].kind()) {
31907case Arg::Addr:
31908case Arg::Stack:
31909case Arg::CallArg:
31910#if CPU(X86) || CPU(X86_64)
31911jit.atomicXor8(args[0].asTrustedImm32(), args[1].asAddress());
31912OPGEN_RETURN(result);
31913#endif
31914break;
31915break;
31916case Arg::Index:
31917#if CPU(X86) || CPU(X86_64)
31918jit.atomicXor8(args[0].asTrustedImm32(), args[1].asBaseIndex());
31919OPGEN_RETURN(result);
31920#endif
31921break;
31922break;
31923default:
31924break;
31925}
31926break;
31927case Arg::Tmp:
31928switch (this->args[1].kind()) {
31929case Arg::Addr:
31930case Arg::Stack:
31931case Arg::CallArg:
31932#if CPU(X86) || CPU(X86_64)
31933jit.atomicXor8(args[0].gpr(), args[1].asAddress());
31934OPGEN_RETURN(result);
31935#endif
31936break;
31937break;
31938case Arg::Index:
31939#if CPU(X86) || CPU(X86_64)
31940jit.atomicXor8(args[0].gpr(), args[1].asBaseIndex());
31941OPGEN_RETURN(result);
31942#endif
31943break;
31944break;
31945default:
31946break;
31947}
31948break;
31949default:
31950break;
31951}
31952break;
31953case Opcode::AtomicXor16:
31954switch (this->args[0].kind()) {
31955case Arg::Imm:
31956switch (this->args[1].kind()) {
31957case Arg::Addr:
31958case Arg::Stack:
31959case Arg::CallArg:
31960#if CPU(X86) || CPU(X86_64)
31961jit.atomicXor16(args[0].asTrustedImm32(), args[1].asAddress());
31962OPGEN_RETURN(result);
31963#endif
31964break;
31965break;
31966case Arg::Index:
31967#if CPU(X86) || CPU(X86_64)
31968jit.atomicXor16(args[0].asTrustedImm32(), args[1].asBaseIndex());
31969OPGEN_RETURN(result);
31970#endif
31971break;
31972break;
31973default:
31974break;
31975}
31976break;
31977case Arg::Tmp:
31978switch (this->args[1].kind()) {
31979case Arg::Addr:
31980case Arg::Stack:
31981case Arg::CallArg:
31982#if CPU(X86) || CPU(X86_64)
31983jit.atomicXor16(args[0].gpr(), args[1].asAddress());
31984OPGEN_RETURN(result);
31985#endif
31986break;
31987break;
31988case Arg::Index:
31989#if CPU(X86) || CPU(X86_64)
31990jit.atomicXor16(args[0].gpr(), args[1].asBaseIndex());
31991OPGEN_RETURN(result);
31992#endif
31993break;
31994break;
31995default:
31996break;
31997}
31998break;
31999default:
32000break;
32001}
32002break;
32003case Opcode::AtomicXor32:
32004switch (this->args[0].kind()) {
32005case Arg::Imm:
32006switch (this->args[1].kind()) {
32007case Arg::Addr:
32008case Arg::Stack:
32009case Arg::CallArg:
32010#if CPU(X86) || CPU(X86_64)
32011jit.atomicXor32(args[0].asTrustedImm32(), args[1].asAddress());
32012OPGEN_RETURN(result);
32013#endif
32014break;
32015break;
32016case Arg::Index:
32017#if CPU(X86) || CPU(X86_64)
32018jit.atomicXor32(args[0].asTrustedImm32(), args[1].asBaseIndex());
32019OPGEN_RETURN(result);
32020#endif
32021break;
32022break;
32023default:
32024break;
32025}
32026break;
32027case Arg::Tmp:
32028switch (this->args[1].kind()) {
32029case Arg::Addr:
32030case Arg::Stack:
32031case Arg::CallArg:
32032#if CPU(X86) || CPU(X86_64)
32033jit.atomicXor32(args[0].gpr(), args[1].asAddress());
32034OPGEN_RETURN(result);
32035#endif
32036break;
32037break;
32038case Arg::Index:
32039#if CPU(X86) || CPU(X86_64)
32040jit.atomicXor32(args[0].gpr(), args[1].asBaseIndex());
32041OPGEN_RETURN(result);
32042#endif
32043break;
32044break;
32045default:
32046break;
32047}
32048break;
32049default:
32050break;
32051}
32052break;
32053case Opcode::AtomicXor64:
32054switch (this->args[0].kind()) {
32055case Arg::Imm:
32056switch (this->args[1].kind()) {
32057case Arg::Addr:
32058case Arg::Stack:
32059case Arg::CallArg:
32060#if CPU(X86_64)
32061jit.atomicXor64(args[0].asTrustedImm32(), args[1].asAddress());
32062OPGEN_RETURN(result);
32063#endif
32064break;
32065break;
32066case Arg::Index:
32067#if CPU(X86_64)
32068jit.atomicXor64(args[0].asTrustedImm32(), args[1].asBaseIndex());
32069OPGEN_RETURN(result);
32070#endif
32071break;
32072break;
32073default:
32074break;
32075}
32076break;
32077case Arg::Tmp:
32078switch (this->args[1].kind()) {
32079case Arg::Addr:
32080case Arg::Stack:
32081case Arg::CallArg:
32082#if CPU(X86_64)
32083jit.atomicXor64(args[0].gpr(), args[1].asAddress());
32084OPGEN_RETURN(result);
32085#endif
32086break;
32087break;
32088case Arg::Index:
32089#if CPU(X86_64)
32090jit.atomicXor64(args[0].gpr(), args[1].asBaseIndex());
32091OPGEN_RETURN(result);
32092#endif
32093break;
32094break;
32095default:
32096break;
32097}
32098break;
32099default:
32100break;
32101}
32102break;
32103case Opcode::AtomicNeg8:
32104switch (this->args[0].kind()) {
32105case Arg::Addr:
32106case Arg::Stack:
32107case Arg::CallArg:
32108#if CPU(X86) || CPU(X86_64)
32109jit.atomicNeg8(args[0].asAddress());
32110OPGEN_RETURN(result);
32111#endif
32112break;
32113break;
32114case Arg::Index:
32115#if CPU(X86) || CPU(X86_64)
32116jit.atomicNeg8(args[0].asBaseIndex());
32117OPGEN_RETURN(result);
32118#endif
32119break;
32120break;
32121default:
32122break;
32123}
32124break;
32125case Opcode::AtomicNeg16:
32126switch (this->args[0].kind()) {
32127case Arg::Addr:
32128case Arg::Stack:
32129case Arg::CallArg:
32130#if CPU(X86) || CPU(X86_64)
32131jit.atomicNeg16(args[0].asAddress());
32132OPGEN_RETURN(result);
32133#endif
32134break;
32135break;
32136case Arg::Index:
32137#if CPU(X86) || CPU(X86_64)
32138jit.atomicNeg16(args[0].asBaseIndex());
32139OPGEN_RETURN(result);
32140#endif
32141break;
32142break;
32143default:
32144break;
32145}
32146break;
32147case Opcode::AtomicNeg32:
32148switch (this->args[0].kind()) {
32149case Arg::Addr:
32150case Arg::Stack:
32151case Arg::CallArg:
32152#if CPU(X86) || CPU(X86_64)
32153jit.atomicNeg32(args[0].asAddress());
32154OPGEN_RETURN(result);
32155#endif
32156break;
32157break;
32158case Arg::Index:
32159#if CPU(X86) || CPU(X86_64)
32160jit.atomicNeg32(args[0].asBaseIndex());
32161OPGEN_RETURN(result);
32162#endif
32163break;
32164break;
32165default:
32166break;
32167}
32168break;
32169case Opcode::AtomicNeg64:
32170switch (this->args[0].kind()) {
32171case Arg::Addr:
32172case Arg::Stack:
32173case Arg::CallArg:
32174#if CPU(X86_64)
32175jit.atomicNeg64(args[0].asAddress());
32176OPGEN_RETURN(result);
32177#endif
32178break;
32179break;
32180case Arg::Index:
32181#if CPU(X86_64)
32182jit.atomicNeg64(args[0].asBaseIndex());
32183OPGEN_RETURN(result);
32184#endif
32185break;
32186break;
32187default:
32188break;
32189}
32190break;
32191case Opcode::AtomicNot8:
32192switch (this->args[0].kind()) {
32193case Arg::Addr:
32194case Arg::Stack:
32195case Arg::CallArg:
32196#if CPU(X86) || CPU(X86_64)
32197jit.atomicNot8(args[0].asAddress());
32198OPGEN_RETURN(result);
32199#endif
32200break;
32201break;
32202case Arg::Index:
32203#if CPU(X86) || CPU(X86_64)
32204jit.atomicNot8(args[0].asBaseIndex());
32205OPGEN_RETURN(result);
32206#endif
32207break;
32208break;
32209default:
32210break;
32211}
32212break;
32213case Opcode::AtomicNot16:
32214switch (this->args[0].kind()) {
32215case Arg::Addr:
32216case Arg::Stack:
32217case Arg::CallArg:
32218#if CPU(X86) || CPU(X86_64)
32219jit.atomicNot16(args[0].asAddress());
32220OPGEN_RETURN(result);
32221#endif
32222break;
32223break;
32224case Arg::Index:
32225#if CPU(X86) || CPU(X86_64)
32226jit.atomicNot16(args[0].asBaseIndex());
32227OPGEN_RETURN(result);
32228#endif
32229break;
32230break;
32231default:
32232break;
32233}
32234break;
32235case Opcode::AtomicNot32:
32236switch (this->args[0].kind()) {
32237case Arg::Addr:
32238case Arg::Stack:
32239case Arg::CallArg:
32240#if CPU(X86) || CPU(X86_64)
32241jit.atomicNot32(args[0].asAddress());
32242OPGEN_RETURN(result);
32243#endif
32244break;
32245break;
32246case Arg::Index:
32247#if CPU(X86) || CPU(X86_64)
32248jit.atomicNot32(args[0].asBaseIndex());
32249OPGEN_RETURN(result);
32250#endif
32251break;
32252break;
32253default:
32254break;
32255}
32256break;
32257case Opcode::AtomicNot64:
32258switch (this->args[0].kind()) {
32259case Arg::Addr:
32260case Arg::Stack:
32261case Arg::CallArg:
32262#if CPU(X86_64)
32263jit.atomicNot64(args[0].asAddress());
32264OPGEN_RETURN(result);
32265#endif
32266break;
32267break;
32268case Arg::Index:
32269#if CPU(X86_64)
32270jit.atomicNot64(args[0].asBaseIndex());
32271OPGEN_RETURN(result);
32272#endif
32273break;
32274break;
32275default:
32276break;
32277}
32278break;
32279case Opcode::AtomicXchgAdd8:
32280switch (this->args[1].kind()) {
32281case Arg::Addr:
32282case Arg::Stack:
32283case Arg::CallArg:
32284#if CPU(X86) || CPU(X86_64)
32285jit.atomicXchgAdd8(args[0].gpr(), args[1].asAddress());
32286OPGEN_RETURN(result);
32287#endif
32288break;
32289break;
32290case Arg::Index:
32291#if CPU(X86) || CPU(X86_64)
32292jit.atomicXchgAdd8(args[0].gpr(), args[1].asBaseIndex());
32293OPGEN_RETURN(result);
32294#endif
32295break;
32296break;
32297default:
32298break;
32299}
32300break;
32301case Opcode::AtomicXchgAdd16:
32302switch (this->args[1].kind()) {
32303case Arg::Addr:
32304case Arg::Stack:
32305case Arg::CallArg:
32306#if CPU(X86) || CPU(X86_64)
32307jit.atomicXchgAdd16(args[0].gpr(), args[1].asAddress());
32308OPGEN_RETURN(result);
32309#endif
32310break;
32311break;
32312case Arg::Index:
32313#if CPU(X86) || CPU(X86_64)
32314jit.atomicXchgAdd16(args[0].gpr(), args[1].asBaseIndex());
32315OPGEN_RETURN(result);
32316#endif
32317break;
32318break;
32319default:
32320break;
32321}
32322break;
32323case Opcode::AtomicXchgAdd32:
32324switch (this->args[1].kind()) {
32325case Arg::Addr:
32326case Arg::Stack:
32327case Arg::CallArg:
32328#if CPU(X86) || CPU(X86_64)
32329jit.atomicXchgAdd32(args[0].gpr(), args[1].asAddress());
32330OPGEN_RETURN(result);
32331#endif
32332break;
32333break;
32334case Arg::Index:
32335#if CPU(X86) || CPU(X86_64)
32336jit.atomicXchgAdd32(args[0].gpr(), args[1].asBaseIndex());
32337OPGEN_RETURN(result);
32338#endif
32339break;
32340break;
32341default:
32342break;
32343}
32344break;
32345case Opcode::AtomicXchgAdd64:
32346switch (this->args[1].kind()) {
32347case Arg::Addr:
32348case Arg::Stack:
32349case Arg::CallArg:
32350#if CPU(X86_64)
32351jit.atomicXchgAdd64(args[0].gpr(), args[1].asAddress());
32352OPGEN_RETURN(result);
32353#endif
32354break;
32355break;
32356case Arg::Index:
32357#if CPU(X86_64)
32358jit.atomicXchgAdd64(args[0].gpr(), args[1].asBaseIndex());
32359OPGEN_RETURN(result);
32360#endif
32361break;
32362break;
32363default:
32364break;
32365}
32366break;
32367case Opcode::AtomicXchg8:
32368switch (this->args[1].kind()) {
32369case Arg::Addr:
32370case Arg::Stack:
32371case Arg::CallArg:
32372#if CPU(X86) || CPU(X86_64)
32373jit.atomicXchg8(args[0].gpr(), args[1].asAddress());
32374OPGEN_RETURN(result);
32375#endif
32376break;
32377break;
32378case Arg::Index:
32379#if CPU(X86) || CPU(X86_64)
32380jit.atomicXchg8(args[0].gpr(), args[1].asBaseIndex());
32381OPGEN_RETURN(result);
32382#endif
32383break;
32384break;
32385default:
32386break;
32387}
32388break;
32389case Opcode::AtomicXchg16:
32390switch (this->args[1].kind()) {
32391case Arg::Addr:
32392case Arg::Stack:
32393case Arg::CallArg:
32394#if CPU(X86) || CPU(X86_64)
32395jit.atomicXchg16(args[0].gpr(), args[1].asAddress());
32396OPGEN_RETURN(result);
32397#endif
32398break;
32399break;
32400case Arg::Index:
32401#if CPU(X86) || CPU(X86_64)
32402jit.atomicXchg16(args[0].gpr(), args[1].asBaseIndex());
32403OPGEN_RETURN(result);
32404#endif
32405break;
32406break;
32407default:
32408break;
32409}
32410break;
32411case Opcode::AtomicXchg32:
32412switch (this->args[1].kind()) {
32413case Arg::Addr:
32414case Arg::Stack:
32415case Arg::CallArg:
32416#if CPU(X86) || CPU(X86_64)
32417jit.atomicXchg32(args[0].gpr(), args[1].asAddress());
32418OPGEN_RETURN(result);
32419#endif
32420break;
32421break;
32422case Arg::Index:
32423#if CPU(X86) || CPU(X86_64)
32424jit.atomicXchg32(args[0].gpr(), args[1].asBaseIndex());
32425OPGEN_RETURN(result);
32426#endif
32427break;
32428break;
32429default:
32430break;
32431}
32432break;
32433case Opcode::AtomicXchg64:
32434switch (this->args[1].kind()) {
32435case Arg::Addr:
32436case Arg::Stack:
32437case Arg::CallArg:
32438#if CPU(X86_64)
32439jit.atomicXchg64(args[0].gpr(), args[1].asAddress());
32440OPGEN_RETURN(result);
32441#endif
32442break;
32443break;
32444case Arg::Index:
32445#if CPU(X86_64)
32446jit.atomicXchg64(args[0].gpr(), args[1].asBaseIndex());
32447OPGEN_RETURN(result);
32448#endif
32449break;
32450break;
32451default:
32452break;
32453}
32454break;
32455case Opcode::LoadLink8:
32456#if CPU(ARM64)
32457jit.loadLink8(args[0].asAddress(), args[1].gpr());
32458OPGEN_RETURN(result);
32459#endif
32460break;
32461break;
32462case Opcode::LoadLinkAcq8:
32463#if CPU(ARM64)
32464jit.loadLinkAcq8(args[0].asAddress(), args[1].gpr());
32465OPGEN_RETURN(result);
32466#endif
32467break;
32468break;
32469case Opcode::StoreCond8:
32470#if CPU(ARM64)
32471jit.storeCond8(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32472OPGEN_RETURN(result);
32473#endif
32474break;
32475break;
32476case Opcode::StoreCondRel8:
32477#if CPU(ARM64)
32478jit.storeCondRel8(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32479OPGEN_RETURN(result);
32480#endif
32481break;
32482break;
32483case Opcode::LoadLink16:
32484#if CPU(ARM64)
32485jit.loadLink16(args[0].asAddress(), args[1].gpr());
32486OPGEN_RETURN(result);
32487#endif
32488break;
32489break;
32490case Opcode::LoadLinkAcq16:
32491#if CPU(ARM64)
32492jit.loadLinkAcq16(args[0].asAddress(), args[1].gpr());
32493OPGEN_RETURN(result);
32494#endif
32495break;
32496break;
32497case Opcode::StoreCond16:
32498#if CPU(ARM64)
32499jit.storeCond16(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32500OPGEN_RETURN(result);
32501#endif
32502break;
32503break;
32504case Opcode::StoreCondRel16:
32505#if CPU(ARM64)
32506jit.storeCondRel16(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32507OPGEN_RETURN(result);
32508#endif
32509break;
32510break;
32511case Opcode::LoadLink32:
32512#if CPU(ARM64)
32513jit.loadLink32(args[0].asAddress(), args[1].gpr());
32514OPGEN_RETURN(result);
32515#endif
32516break;
32517break;
32518case Opcode::LoadLinkAcq32:
32519#if CPU(ARM64)
32520jit.loadLinkAcq32(args[0].asAddress(), args[1].gpr());
32521OPGEN_RETURN(result);
32522#endif
32523break;
32524break;
32525case Opcode::StoreCond32:
32526#if CPU(ARM64)
32527jit.storeCond32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32528OPGEN_RETURN(result);
32529#endif
32530break;
32531break;
32532case Opcode::StoreCondRel32:
32533#if CPU(ARM64)
32534jit.storeCondRel32(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32535OPGEN_RETURN(result);
32536#endif
32537break;
32538break;
32539case Opcode::LoadLink64:
32540#if CPU(ARM64)
32541jit.loadLink64(args[0].asAddress(), args[1].gpr());
32542OPGEN_RETURN(result);
32543#endif
32544break;
32545break;
32546case Opcode::LoadLinkAcq64:
32547#if CPU(ARM64)
32548jit.loadLinkAcq64(args[0].asAddress(), args[1].gpr());
32549OPGEN_RETURN(result);
32550#endif
32551break;
32552break;
32553case Opcode::StoreCond64:
32554#if CPU(ARM64)
32555jit.storeCond64(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32556OPGEN_RETURN(result);
32557#endif
32558break;
32559break;
32560case Opcode::StoreCondRel64:
32561#if CPU(ARM64)
32562jit.storeCondRel64(args[0].gpr(), args[1].asAddress(), args[2].gpr());
32563OPGEN_RETURN(result);
32564#endif
32565break;
32566break;
32567case Opcode::Depend32:
32568#if CPU(ARM64)
32569jit.depend32(args[0].gpr(), args[1].gpr());
32570OPGEN_RETURN(result);
32571#endif
32572break;
32573break;
32574case Opcode::Depend64:
32575#if CPU(ARM64)
32576jit.depend64(args[0].gpr(), args[1].gpr());
32577OPGEN_RETURN(result);
32578#endif
32579break;
32580break;
32581case Opcode::Compare32:
32582switch (this->args[2].kind()) {
32583case Arg::Tmp:
32584jit.compare32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32585OPGEN_RETURN(result);
32586break;
32587break;
32588case Arg::Imm:
32589jit.compare32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32590OPGEN_RETURN(result);
32591break;
32592break;
32593default:
32594break;
32595}
32596break;
32597case Opcode::Compare64:
32598switch (this->args[2].kind()) {
32599case Arg::Tmp:
32600#if CPU(X86_64) || CPU(ARM64)
32601jit.compare64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32602OPGEN_RETURN(result);
32603#endif
32604break;
32605break;
32606case Arg::Imm:
32607#if CPU(X86_64)
32608jit.compare64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32609OPGEN_RETURN(result);
32610#endif
32611break;
32612break;
32613default:
32614break;
32615}
32616break;
32617case Opcode::Test32:
32618switch (this->args[1].kind()) {
32619case Arg::Addr:
32620case Arg::Stack:
32621case Arg::CallArg:
32622#if CPU(X86) || CPU(X86_64)
32623jit.test32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].gpr());
32624OPGEN_RETURN(result);
32625#endif
32626break;
32627break;
32628case Arg::Tmp:
32629switch (this->args[2].kind()) {
32630case Arg::Tmp:
32631jit.test32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32632OPGEN_RETURN(result);
32633break;
32634break;
32635case Arg::BitImm:
32636jit.test32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32637OPGEN_RETURN(result);
32638break;
32639break;
32640default:
32641break;
32642}
32643break;
32644default:
32645break;
32646}
32647break;
32648case Opcode::Test64:
32649switch (this->args[2].kind()) {
32650case Arg::Imm:
32651#if CPU(X86_64)
32652jit.test64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
32653OPGEN_RETURN(result);
32654#endif
32655break;
32656break;
32657case Arg::Tmp:
32658#if CPU(X86_64) || CPU(ARM64)
32659jit.test64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32660OPGEN_RETURN(result);
32661#endif
32662break;
32663break;
32664default:
32665break;
32666}
32667break;
32668case Opcode::CompareDouble:
32669jit.compareDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr());
32670OPGEN_RETURN(result);
32671break;
32672break;
32673case Opcode::CompareFloat:
32674jit.compareFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr());
32675OPGEN_RETURN(result);
32676break;
32677break;
32678case Opcode::Branch8:
32679switch (this->args[1].kind()) {
32680case Arg::Addr:
32681case Arg::Stack:
32682case Arg::CallArg:
32683#if CPU(X86) || CPU(X86_64)
32684result = jit.branch8(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32());
32685OPGEN_RETURN(result);
32686#endif
32687break;
32688break;
32689case Arg::Index:
32690#if CPU(X86) || CPU(X86_64)
32691result = jit.branch8(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
32692OPGEN_RETURN(result);
32693#endif
32694break;
32695break;
32696default:
32697break;
32698}
32699break;
32700case Opcode::Branch32:
32701switch (this->args[1].kind()) {
32702case Arg::Addr:
32703case Arg::Stack:
32704case Arg::CallArg:
32705switch (this->args[2].kind()) {
32706case Arg::Imm:
32707#if CPU(X86) || CPU(X86_64)
32708result = jit.branch32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32());
32709OPGEN_RETURN(result);
32710#endif
32711break;
32712break;
32713case Arg::Tmp:
32714#if CPU(X86) || CPU(X86_64)
32715result = jit.branch32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr());
32716OPGEN_RETURN(result);
32717#endif
32718break;
32719break;
32720default:
32721break;
32722}
32723break;
32724case Arg::Tmp:
32725switch (this->args[2].kind()) {
32726case Arg::Tmp:
32727result = jit.branch32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr());
32728OPGEN_RETURN(result);
32729break;
32730break;
32731case Arg::Imm:
32732result = jit.branch32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32());
32733OPGEN_RETURN(result);
32734break;
32735break;
32736case Arg::Addr:
32737case Arg::Stack:
32738case Arg::CallArg:
32739#if CPU(X86) || CPU(X86_64)
32740result = jit.branch32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress());
32741OPGEN_RETURN(result);
32742#endif
32743break;
32744break;
32745default:
32746break;
32747}
32748break;
32749case Arg::Index:
32750#if CPU(X86) || CPU(X86_64)
32751result = jit.branch32(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
32752OPGEN_RETURN(result);
32753#endif
32754break;
32755break;
32756default:
32757break;
32758}
32759break;
32760case Opcode::Branch64:
32761switch (this->args[1].kind()) {
32762case Arg::Tmp:
32763switch (this->args[2].kind()) {
32764case Arg::Tmp:
32765#if CPU(X86_64) || CPU(ARM64)
32766result = jit.branch64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr());
32767OPGEN_RETURN(result);
32768#endif
32769break;
32770break;
32771case Arg::Imm:
32772#if CPU(X86_64) || CPU(ARM64)
32773result = jit.branch64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32());
32774OPGEN_RETURN(result);
32775#endif
32776break;
32777break;
32778case Arg::Addr:
32779case Arg::Stack:
32780case Arg::CallArg:
32781#if CPU(X86_64)
32782result = jit.branch64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress());
32783OPGEN_RETURN(result);
32784#endif
32785break;
32786break;
32787default:
32788break;
32789}
32790break;
32791case Arg::Addr:
32792case Arg::Stack:
32793case Arg::CallArg:
32794switch (this->args[2].kind()) {
32795case Arg::Tmp:
32796#if CPU(X86_64)
32797result = jit.branch64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr());
32798OPGEN_RETURN(result);
32799#endif
32800break;
32801break;
32802case Arg::Imm:
32803#if CPU(X86_64)
32804result = jit.branch64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32());
32805OPGEN_RETURN(result);
32806#endif
32807break;
32808break;
32809default:
32810break;
32811}
32812break;
32813case Arg::Index:
32814#if CPU(X86_64)
32815result = jit.branch64(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].gpr());
32816OPGEN_RETURN(result);
32817#endif
32818break;
32819break;
32820default:
32821break;
32822}
32823break;
32824case Opcode::BranchTest8:
32825switch (this->args[1].kind()) {
32826case Arg::Addr:
32827case Arg::Stack:
32828case Arg::CallArg:
32829#if CPU(X86) || CPU(X86_64)
32830result = jit.branchTest8(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
32831OPGEN_RETURN(result);
32832#endif
32833break;
32834break;
32835case Arg::Index:
32836#if CPU(X86) || CPU(X86_64)
32837result = jit.branchTest8(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
32838OPGEN_RETURN(result);
32839#endif
32840break;
32841break;
32842default:
32843break;
32844}
32845break;
32846case Opcode::BranchTest32:
32847switch (this->args[1].kind()) {
32848case Arg::Tmp:
32849switch (this->args[2].kind()) {
32850case Arg::Tmp:
32851result = jit.branchTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
32852OPGEN_RETURN(result);
32853break;
32854break;
32855case Arg::BitImm:
32856result = jit.branchTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32());
32857OPGEN_RETURN(result);
32858break;
32859break;
32860default:
32861break;
32862}
32863break;
32864case Arg::Addr:
32865case Arg::Stack:
32866case Arg::CallArg:
32867#if CPU(X86) || CPU(X86_64)
32868result = jit.branchTest32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
32869OPGEN_RETURN(result);
32870#endif
32871break;
32872break;
32873case Arg::Index:
32874#if CPU(X86) || CPU(X86_64)
32875result = jit.branchTest32(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
32876OPGEN_RETURN(result);
32877#endif
32878break;
32879break;
32880default:
32881break;
32882}
32883break;
32884case Opcode::BranchTest64:
32885switch (this->args[1].kind()) {
32886case Arg::Tmp:
32887switch (this->args[2].kind()) {
32888case Arg::Tmp:
32889#if CPU(X86_64) || CPU(ARM64)
32890result = jit.branchTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
32891OPGEN_RETURN(result);
32892#endif
32893break;
32894break;
32895#if USE(JSVALUE64)
32896case Arg::BitImm64:
32897#if CPU(ARM64)
32898result = jit.branchTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm64());
32899OPGEN_RETURN(result);
32900#endif
32901break;
32902break;
32903#endif // USE(JSVALUE64)
32904case Arg::BitImm:
32905#if CPU(X86_64)
32906result = jit.branchTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32());
32907OPGEN_RETURN(result);
32908#endif
32909break;
32910break;
32911default:
32912break;
32913}
32914break;
32915case Arg::Addr:
32916case Arg::Stack:
32917case Arg::CallArg:
32918switch (this->args[2].kind()) {
32919case Arg::BitImm:
32920#if CPU(X86_64)
32921result = jit.branchTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32());
32922OPGEN_RETURN(result);
32923#endif
32924break;
32925break;
32926case Arg::Tmp:
32927#if CPU(X86_64)
32928result = jit.branchTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
32929OPGEN_RETURN(result);
32930#endif
32931break;
32932break;
32933default:
32934break;
32935}
32936break;
32937case Arg::Index:
32938#if CPU(X86_64)
32939result = jit.branchTest64(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32());
32940OPGEN_RETURN(result);
32941#endif
32942break;
32943break;
32944default:
32945break;
32946}
32947break;
32948case Opcode::BranchDouble:
32949result = jit.branchDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr());
32950OPGEN_RETURN(result);
32951break;
32952break;
32953case Opcode::BranchFloat:
32954result = jit.branchFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr());
32955OPGEN_RETURN(result);
32956break;
32957break;
32958case Opcode::BranchAdd32:
32959switch (this->args.size()) {
32960case 4:
32961switch (this->args[1].kind()) {
32962case Arg::Tmp:
32963switch (this->args[2].kind()) {
32964case Arg::Tmp:
32965result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
32966OPGEN_RETURN(result);
32967break;
32968break;
32969case Arg::Addr:
32970case Arg::Stack:
32971case Arg::CallArg:
32972#if CPU(X86) || CPU(X86_64)
32973result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress(), args[3].gpr());
32974OPGEN_RETURN(result);
32975#endif
32976break;
32977break;
32978default:
32979break;
32980}
32981break;
32982case Arg::Addr:
32983case Arg::Stack:
32984case Arg::CallArg:
32985#if CPU(X86) || CPU(X86_64)
32986result = jit.branchAdd32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr(), args[3].gpr());
32987OPGEN_RETURN(result);
32988#endif
32989break;
32990break;
32991default:
32992break;
32993}
32994break;
32995case 3:
32996switch (this->args[1].kind()) {
32997case Arg::Tmp:
32998switch (this->args[2].kind()) {
32999case Arg::Tmp:
33000result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33001OPGEN_RETURN(result);
33002break;
33003break;
33004case Arg::Addr:
33005case Arg::Stack:
33006case Arg::CallArg:
33007#if CPU(X86) || CPU(X86_64)
33008result = jit.branchAdd32(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress());
33009OPGEN_RETURN(result);
33010#endif
33011break;
33012break;
33013default:
33014break;
33015}
33016break;
33017case Arg::Imm:
33018switch (this->args[2].kind()) {
33019case Arg::Tmp:
33020result = jit.branchAdd32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33021OPGEN_RETURN(result);
33022break;
33023break;
33024case Arg::Addr:
33025case Arg::Stack:
33026case Arg::CallArg:
33027#if CPU(X86) || CPU(X86_64)
33028result = jit.branchAdd32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].asAddress());
33029OPGEN_RETURN(result);
33030#endif
33031break;
33032break;
33033default:
33034break;
33035}
33036break;
33037case Arg::Addr:
33038case Arg::Stack:
33039case Arg::CallArg:
33040#if CPU(X86) || CPU(X86_64)
33041result = jit.branchAdd32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33042OPGEN_RETURN(result);
33043#endif
33044break;
33045break;
33046default:
33047break;
33048}
33049break;
33050default:
33051break;
33052}
33053break;
33054case Opcode::BranchAdd64:
33055switch (this->args.size()) {
33056case 4:
33057switch (this->args[1].kind()) {
33058case Arg::Tmp:
33059switch (this->args[2].kind()) {
33060case Arg::Tmp:
33061result = jit.branchAdd64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr());
33062OPGEN_RETURN(result);
33063break;
33064break;
33065case Arg::Addr:
33066case Arg::Stack:
33067case Arg::CallArg:
33068#if CPU(X86) || CPU(X86_64)
33069result = jit.branchAdd64(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress(), args[3].gpr());
33070OPGEN_RETURN(result);
33071#endif
33072break;
33073break;
33074default:
33075break;
33076}
33077break;
33078case Arg::Addr:
33079case Arg::Stack:
33080case Arg::CallArg:
33081#if CPU(X86) || CPU(X86_64)
33082result = jit.branchAdd64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr(), args[3].gpr());
33083OPGEN_RETURN(result);
33084#endif
33085break;
33086break;
33087default:
33088break;
33089}
33090break;
33091case 3:
33092switch (this->args[1].kind()) {
33093case Arg::Imm:
33094#if CPU(X86_64) || CPU(ARM64)
33095result = jit.branchAdd64(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33096OPGEN_RETURN(result);
33097#endif
33098break;
33099break;
33100case Arg::Tmp:
33101#if CPU(X86_64) || CPU(ARM64)
33102result = jit.branchAdd64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33103OPGEN_RETURN(result);
33104#endif
33105break;
33106break;
33107case Arg::Addr:
33108case Arg::Stack:
33109case Arg::CallArg:
33110#if CPU(X86_64)
33111result = jit.branchAdd64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33112OPGEN_RETURN(result);
33113#endif
33114break;
33115break;
33116default:
33117break;
33118}
33119break;
33120default:
33121break;
33122}
33123break;
33124case Opcode::BranchMul32:
33125switch (this->args.size()) {
33126case 3:
33127switch (this->args[1].kind()) {
33128case Arg::Tmp:
33129#if CPU(X86) || CPU(X86_64)
33130result = jit.branchMul32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33131OPGEN_RETURN(result);
33132#endif
33133break;
33134break;
33135case Arg::Addr:
33136case Arg::Stack:
33137case Arg::CallArg:
33138#if CPU(X86) || CPU(X86_64)
33139result = jit.branchMul32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33140OPGEN_RETURN(result);
33141#endif
33142break;
33143break;
33144default:
33145break;
33146}
33147break;
33148case 4:
33149#if CPU(X86) || CPU(X86_64)
33150result = jit.branchMul32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr());
33151OPGEN_RETURN(result);
33152#endif
33153break;
33154break;
33155case 6:
33156#if CPU(ARM64)
33157result = jit.branchMul32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33158OPGEN_RETURN(result);
33159#endif
33160break;
33161break;
33162default:
33163break;
33164}
33165break;
33166case Opcode::BranchMul64:
33167switch (this->args.size()) {
33168case 3:
33169#if CPU(X86_64)
33170result = jit.branchMul64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33171OPGEN_RETURN(result);
33172#endif
33173break;
33174break;
33175case 6:
33176#if CPU(ARM64)
33177result = jit.branchMul64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33178OPGEN_RETURN(result);
33179#endif
33180break;
33181break;
33182default:
33183break;
33184}
33185break;
33186case Opcode::BranchSub32:
33187switch (this->args[1].kind()) {
33188case Arg::Tmp:
33189switch (this->args[2].kind()) {
33190case Arg::Tmp:
33191result = jit.branchSub32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33192OPGEN_RETURN(result);
33193break;
33194break;
33195case Arg::Addr:
33196case Arg::Stack:
33197case Arg::CallArg:
33198#if CPU(X86) || CPU(X86_64)
33199result = jit.branchSub32(args[0].asResultCondition(), args[1].gpr(), args[2].asAddress());
33200OPGEN_RETURN(result);
33201#endif
33202break;
33203break;
33204default:
33205break;
33206}
33207break;
33208case Arg::Imm:
33209switch (this->args[2].kind()) {
33210case Arg::Tmp:
33211result = jit.branchSub32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33212OPGEN_RETURN(result);
33213break;
33214break;
33215case Arg::Addr:
33216case Arg::Stack:
33217case Arg::CallArg:
33218#if CPU(X86) || CPU(X86_64)
33219result = jit.branchSub32(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].asAddress());
33220OPGEN_RETURN(result);
33221#endif
33222break;
33223break;
33224default:
33225break;
33226}
33227break;
33228case Arg::Addr:
33229case Arg::Stack:
33230case Arg::CallArg:
33231#if CPU(X86) || CPU(X86_64)
33232result = jit.branchSub32(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr());
33233OPGEN_RETURN(result);
33234#endif
33235break;
33236break;
33237default:
33238break;
33239}
33240break;
33241case Opcode::BranchSub64:
33242switch (this->args[1].kind()) {
33243case Arg::Imm:
33244#if CPU(X86_64) || CPU(ARM64)
33245result = jit.branchSub64(args[0].asResultCondition(), args[1].asTrustedImm32(), args[2].gpr());
33246OPGEN_RETURN(result);
33247#endif
33248break;
33249break;
33250case Arg::Tmp:
33251#if CPU(X86_64) || CPU(ARM64)
33252result = jit.branchSub64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr());
33253OPGEN_RETURN(result);
33254#endif
33255break;
33256break;
33257default:
33258break;
33259}
33260break;
33261case Opcode::BranchNeg32:
33262result = jit.branchNeg32(args[0].asResultCondition(), args[1].gpr());
33263OPGEN_RETURN(result);
33264break;
33265break;
33266case Opcode::BranchNeg64:
33267#if CPU(X86_64) || CPU(ARM64)
33268result = jit.branchNeg64(args[0].asResultCondition(), args[1].gpr());
33269OPGEN_RETURN(result);
33270#endif
33271break;
33272break;
33273case Opcode::MoveConditionally32:
33274switch (this->args.size()) {
33275case 5:
33276jit.moveConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33277OPGEN_RETURN(result);
33278break;
33279break;
33280case 6:
33281switch (this->args[2].kind()) {
33282case Arg::Tmp:
33283jit.moveConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33284OPGEN_RETURN(result);
33285break;
33286break;
33287case Arg::Imm:
33288jit.moveConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33289OPGEN_RETURN(result);
33290break;
33291break;
33292default:
33293break;
33294}
33295break;
33296default:
33297break;
33298}
33299break;
33300case Opcode::MoveConditionally64:
33301switch (this->args.size()) {
33302case 5:
33303#if CPU(X86_64) || CPU(ARM64)
33304jit.moveConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33305OPGEN_RETURN(result);
33306#endif
33307break;
33308break;
33309case 6:
33310switch (this->args[2].kind()) {
33311case Arg::Tmp:
33312#if CPU(X86_64) || CPU(ARM64)
33313jit.moveConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33314OPGEN_RETURN(result);
33315#endif
33316break;
33317break;
33318case Arg::Imm:
33319#if CPU(X86_64) || CPU(ARM64)
33320jit.moveConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33321OPGEN_RETURN(result);
33322#endif
33323break;
33324break;
33325default:
33326break;
33327}
33328break;
33329default:
33330break;
33331}
33332break;
33333case Opcode::MoveConditionallyTest32:
33334switch (this->args.size()) {
33335case 5:
33336switch (this->args[2].kind()) {
33337case Arg::Tmp:
33338jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33339OPGEN_RETURN(result);
33340break;
33341break;
33342case Arg::Imm:
33343#if CPU(X86) || CPU(X86_64)
33344jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr());
33345OPGEN_RETURN(result);
33346#endif
33347break;
33348break;
33349default:
33350break;
33351}
33352break;
33353case 6:
33354switch (this->args[2].kind()) {
33355case Arg::Tmp:
33356jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33357OPGEN_RETURN(result);
33358break;
33359break;
33360case Arg::BitImm:
33361jit.moveConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33362OPGEN_RETURN(result);
33363break;
33364break;
33365default:
33366break;
33367}
33368break;
33369default:
33370break;
33371}
33372break;
33373case Opcode::MoveConditionallyTest64:
33374switch (this->args.size()) {
33375case 5:
33376switch (this->args[2].kind()) {
33377case Arg::Tmp:
33378#if CPU(X86_64) || CPU(ARM64)
33379jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr());
33380OPGEN_RETURN(result);
33381#endif
33382break;
33383break;
33384case Arg::Imm:
33385#if CPU(X86_64)
33386jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr());
33387OPGEN_RETURN(result);
33388#endif
33389break;
33390break;
33391default:
33392break;
33393}
33394break;
33395case 6:
33396switch (this->args[2].kind()) {
33397case Arg::Tmp:
33398#if CPU(X86_64) || CPU(ARM64)
33399jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33400OPGEN_RETURN(result);
33401#endif
33402break;
33403break;
33404case Arg::Imm:
33405#if CPU(X86_64)
33406jit.moveConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33407OPGEN_RETURN(result);
33408#endif
33409break;
33410break;
33411default:
33412break;
33413}
33414break;
33415default:
33416break;
33417}
33418break;
33419case Opcode::MoveConditionallyDouble:
33420switch (this->args.size()) {
33421case 6:
33422jit.moveConditionallyDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33423OPGEN_RETURN(result);
33424break;
33425break;
33426case 5:
33427jit.moveConditionallyDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr());
33428OPGEN_RETURN(result);
33429break;
33430break;
33431default:
33432break;
33433}
33434break;
33435case Opcode::MoveConditionallyFloat:
33436switch (this->args.size()) {
33437case 6:
33438jit.moveConditionallyFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr(), args[5].gpr());
33439OPGEN_RETURN(result);
33440break;
33441break;
33442case 5:
33443jit.moveConditionallyFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].gpr(), args[4].gpr());
33444OPGEN_RETURN(result);
33445break;
33446break;
33447default:
33448break;
33449}
33450break;
33451case Opcode::MoveDoubleConditionally32:
33452switch (this->args[1].kind()) {
33453case Arg::Tmp:
33454switch (this->args[2].kind()) {
33455case Arg::Tmp:
33456jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33457OPGEN_RETURN(result);
33458break;
33459break;
33460case Arg::Imm:
33461jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33462OPGEN_RETURN(result);
33463break;
33464break;
33465case Arg::Addr:
33466case Arg::Stack:
33467case Arg::CallArg:
33468#if CPU(X86) || CPU(X86_64)
33469jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33470OPGEN_RETURN(result);
33471#endif
33472break;
33473break;
33474default:
33475break;
33476}
33477break;
33478case Arg::Addr:
33479case Arg::Stack:
33480case Arg::CallArg:
33481switch (this->args[2].kind()) {
33482case Arg::Imm:
33483#if CPU(X86) || CPU(X86_64)
33484jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33485OPGEN_RETURN(result);
33486#endif
33487break;
33488break;
33489case Arg::Tmp:
33490#if CPU(X86) || CPU(X86_64)
33491jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33492OPGEN_RETURN(result);
33493#endif
33494break;
33495break;
33496default:
33497break;
33498}
33499break;
33500case Arg::Index:
33501#if CPU(X86) || CPU(X86_64)
33502jit.moveDoubleConditionally32(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33503OPGEN_RETURN(result);
33504#endif
33505break;
33506break;
33507default:
33508break;
33509}
33510break;
33511case Opcode::MoveDoubleConditionally64:
33512switch (this->args[1].kind()) {
33513case Arg::Tmp:
33514switch (this->args[2].kind()) {
33515case Arg::Tmp:
33516#if CPU(X86_64) || CPU(ARM64)
33517jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33518OPGEN_RETURN(result);
33519#endif
33520break;
33521break;
33522case Arg::Imm:
33523#if CPU(X86_64) || CPU(ARM64)
33524jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33525OPGEN_RETURN(result);
33526#endif
33527break;
33528break;
33529case Arg::Addr:
33530case Arg::Stack:
33531case Arg::CallArg:
33532#if CPU(X86_64)
33533jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].gpr(), args[2].asAddress(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33534OPGEN_RETURN(result);
33535#endif
33536break;
33537break;
33538default:
33539break;
33540}
33541break;
33542case Arg::Addr:
33543case Arg::Stack:
33544case Arg::CallArg:
33545switch (this->args[2].kind()) {
33546case Arg::Tmp:
33547#if CPU(X86_64)
33548jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33549OPGEN_RETURN(result);
33550#endif
33551break;
33552break;
33553case Arg::Imm:
33554#if CPU(X86_64)
33555jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33556OPGEN_RETURN(result);
33557#endif
33558break;
33559break;
33560default:
33561break;
33562}
33563break;
33564case Arg::Index:
33565#if CPU(X86_64)
33566jit.moveDoubleConditionally64(args[0].asRelationalCondition(), args[1].asBaseIndex(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33567OPGEN_RETURN(result);
33568#endif
33569break;
33570break;
33571default:
33572break;
33573}
33574break;
33575case Opcode::MoveDoubleConditionallyTest32:
33576switch (this->args[1].kind()) {
33577case Arg::Tmp:
33578switch (this->args[2].kind()) {
33579case Arg::Tmp:
33580jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33581OPGEN_RETURN(result);
33582break;
33583break;
33584case Arg::BitImm:
33585jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33586OPGEN_RETURN(result);
33587break;
33588break;
33589default:
33590break;
33591}
33592break;
33593case Arg::Addr:
33594case Arg::Stack:
33595case Arg::CallArg:
33596#if CPU(X86) || CPU(X86_64)
33597jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33598OPGEN_RETURN(result);
33599#endif
33600break;
33601break;
33602case Arg::Index:
33603#if CPU(X86) || CPU(X86_64)
33604jit.moveDoubleConditionallyTest32(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33605OPGEN_RETURN(result);
33606#endif
33607break;
33608break;
33609default:
33610break;
33611}
33612break;
33613case Opcode::MoveDoubleConditionallyTest64:
33614switch (this->args[1].kind()) {
33615case Arg::Tmp:
33616switch (this->args[2].kind()) {
33617case Arg::Tmp:
33618#if CPU(X86_64) || CPU(ARM64)
33619jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33620OPGEN_RETURN(result);
33621#endif
33622break;
33623break;
33624case Arg::Imm:
33625#if CPU(X86_64)
33626jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].gpr(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33627OPGEN_RETURN(result);
33628#endif
33629break;
33630break;
33631default:
33632break;
33633}
33634break;
33635case Arg::Addr:
33636case Arg::Stack:
33637case Arg::CallArg:
33638switch (this->args[2].kind()) {
33639case Arg::Imm:
33640#if CPU(X86_64)
33641jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33642OPGEN_RETURN(result);
33643#endif
33644break;
33645break;
33646case Arg::Tmp:
33647#if CPU(X86_64)
33648jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].asAddress(), args[2].gpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33649OPGEN_RETURN(result);
33650#endif
33651break;
33652break;
33653default:
33654break;
33655}
33656break;
33657case Arg::Index:
33658#if CPU(X86_64)
33659jit.moveDoubleConditionallyTest64(args[0].asResultCondition(), args[1].asBaseIndex(), args[2].asTrustedImm32(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33660OPGEN_RETURN(result);
33661#endif
33662break;
33663break;
33664default:
33665break;
33666}
33667break;
33668case Opcode::MoveDoubleConditionallyDouble:
33669jit.moveDoubleConditionallyDouble(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33670OPGEN_RETURN(result);
33671break;
33672break;
33673case Opcode::MoveDoubleConditionallyFloat:
33674jit.moveDoubleConditionallyFloat(args[0].asDoubleCondition(), args[1].fpr(), args[2].fpr(), args[3].fpr(), args[4].fpr(), args[5].fpr());
33675OPGEN_RETURN(result);
33676break;
33677break;
33678case Opcode::MemoryFence:
33679jit.memoryFence();
33680OPGEN_RETURN(result);
33681break;
33682break;
33683case Opcode::StoreFence:
33684jit.storeFence();
33685OPGEN_RETURN(result);
33686break;
33687break;
33688case Opcode::LoadFence:
33689jit.loadFence();
33690OPGEN_RETURN(result);
33691break;
33692break;
33693case Opcode::Jump:
33694result = jit.jump();
33695OPGEN_RETURN(result);
33696break;
33697break;
33698case Opcode::RetVoid:
33699jit.retVoid();
33700OPGEN_RETURN(result);
33701break;
33702break;
33703case Opcode::Ret32:
33704jit.ret32(args[0].gpr());
33705OPGEN_RETURN(result);
33706break;
33707break;
33708case Opcode::Ret64:
33709#if CPU(X86_64) || CPU(ARM64)
33710jit.ret64(args[0].gpr());
33711OPGEN_RETURN(result);
33712#endif
33713break;
33714break;
33715case Opcode::RetFloat:
33716jit.retFloat(args[0].fpr());
33717OPGEN_RETURN(result);
33718break;
33719break;
33720case Opcode::RetDouble:
33721jit.retDouble(args[0].fpr());
33722OPGEN_RETURN(result);
33723break;
33724break;
33725case Opcode::Oops:
33726jit.oops();
33727OPGEN_RETURN(result);
33728break;
33729break;
33730case Opcode::EntrySwitch:
33731OPGEN_RETURN(EntrySwitchCustom::generate(*this, jit, context));
33732break;
33733case Opcode::Shuffle:
33734OPGEN_RETURN(ShuffleCustom::generate(*this, jit, context));
33735break;
33736case Opcode::Patch:
33737OPGEN_RETURN(PatchCustom::generate(*this, jit, context));
33738break;
33739case Opcode::CCall:
33740OPGEN_RETURN(CCallCustom::generate(*this, jit, context));
33741break;
33742case Opcode::ColdCCall:
33743OPGEN_RETURN(ColdCCallCustom::generate(*this, jit, context));
33744break;
33745case Opcode::WasmBoundsCheck:
33746OPGEN_RETURN(WasmBoundsCheckCustom::generate(*this, jit, context));
33747break;
33748default:
33749break;
33750}
33751RELEASE_ASSERT_NOT_REACHED();
33752return result;
33753}
33754} } } // namespace JSC::B3::Air
33755#endif // AirOpcodeGenerated_h
33756