1/*
2 * Copyright (C) 2016-2017 Apple Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY APPLE AND ITS CONTRIBUTORS "AS IS" AND ANY
15 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL APPLE OR ITS CONTRIBUTORS BE LIABLE FOR ANY
18 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
21 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26// DO NO EDIT! - This file was generated by /home/ubuntu/webkit/Source/JavaScriptCore/wasm/generateWasmB3IRGeneratorInlinesHeader.py
27
28#pragma once
29
30#if ENABLE(WEBASSEMBLY)
31
32namespace JSC { namespace Wasm {
33
34
35template<> auto B3IRGenerator::addOp<OpType::F32Ceil>(ExpressionType arg0, ExpressionType& result) -> PartialResult
36{
37 result = m_currentBlock->appendNew<Value>(m_proc, B3::Ceil, origin(), arg0);
38 return { };
39}
40
41template<> auto B3IRGenerator::addOp<OpType::I32Mul>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
42{
43 result = m_currentBlock->appendNew<Value>(m_proc, B3::Mul, origin(), arg0, arg1);
44 return { };
45}
46
47template<> auto B3IRGenerator::addOp<OpType::I32Sub>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
48{
49 result = m_currentBlock->appendNew<Value>(m_proc, B3::Sub, origin(), arg0, arg1);
50 return { };
51}
52
53template<> auto B3IRGenerator::addOp<OpType::F64Le>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
54{
55 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessEqual, origin(), arg0, arg1);
56 return { };
57}
58
59template<> auto B3IRGenerator::addOp<OpType::F32DemoteF64>(ExpressionType arg0, ExpressionType& result) -> PartialResult
60{
61 result = m_currentBlock->appendNew<Value>(m_proc, B3::DoubleToFloat, origin(), arg0);
62 return { };
63}
64
65template<> auto B3IRGenerator::addOp<OpType::F32Min>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
66{
67 Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
68Value* temp7 = m_currentBlock->appendNew<Value>(m_proc, B3::BitOr, origin(), arg0, arg1);
69Value* temp14 = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
70Value* temp22 = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
71Value* temp28 = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
72Value* temp20 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp22, arg1, temp28);
73Value* temp12 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp14, arg0, temp20);
74Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp2, temp7, temp12);
75result = temp0;
76 return { };
77}
78
79template<> auto B3IRGenerator::addOp<OpType::F64Ne>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
80{
81 result = m_currentBlock->appendNew<Value>(m_proc, B3::NotEqual, origin(), arg0, arg1);
82 return { };
83}
84
85template<> auto B3IRGenerator::addOp<OpType::F64Lt>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
86{
87 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
88 return { };
89}
90
91template<> auto B3IRGenerator::addOp<OpType::F32Max>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
92{
93 Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
94Value* temp7 = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), arg0, arg1);
95Value* temp14 = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
96Value* temp22 = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
97Value* temp28 = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
98Value* temp20 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp22, arg0, temp28);
99Value* temp12 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp14, arg1, temp20);
100Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp2, temp7, temp12);
101result = temp0;
102 return { };
103}
104
105template<> auto B3IRGenerator::addOp<OpType::F64Mul>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
106{
107 result = m_currentBlock->appendNew<Value>(m_proc, B3::Mul, origin(), arg0, arg1);
108 return { };
109}
110
111template<> auto B3IRGenerator::addOp<OpType::F32Div>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
112{
113 result = m_currentBlock->appendNew<Value>(m_proc, B3::Div, origin(), arg0, arg1);
114 return { };
115}
116
117template<> auto B3IRGenerator::addOp<OpType::I32Clz>(ExpressionType arg0, ExpressionType& result) -> PartialResult
118{
119 result = m_currentBlock->appendNew<Value>(m_proc, B3::Clz, origin(), arg0);
120 return { };
121}
122
123template<> auto B3IRGenerator::addOp<OpType::F32Copysign>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
124{
125 Value* temp6 = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg1);
126Value* temp12 = constant(Int32, 0x80000000);
127Value* temp4 = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), temp6, temp12);
128Value* temp17 = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg0);
129Value* temp23 = constant(Int32, 0x7fffffff);
130Value* temp15 = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), temp17, temp23);
131Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::BitOr, origin(), temp4, temp15);
132Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), temp2);
133result = temp0;
134 return { };
135}
136
137template<> auto B3IRGenerator::addOp<OpType::F64ConvertUI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
138{
139 Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::ZExt32, origin(), arg0);
140Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::IToD, origin(), temp2);
141result = temp0;
142 return { };
143}
144
145template<> auto B3IRGenerator::addOp<OpType::F32ReinterpretI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
146{
147 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg0);
148 return { };
149}
150
151template<> auto B3IRGenerator::addOp<OpType::I64And>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
152{
153 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), arg0, arg1);
154 return { };
155}
156
157template<> auto B3IRGenerator::addOp<OpType::F32Ne>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
158{
159 result = m_currentBlock->appendNew<Value>(m_proc, B3::NotEqual, origin(), arg0, arg1);
160 return { };
161}
162
163template<> auto B3IRGenerator::addOp<OpType::F64Gt>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
164{
165 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
166 return { };
167}
168
169template<> auto B3IRGenerator::addOp<OpType::F32Sqrt>(ExpressionType arg0, ExpressionType& result) -> PartialResult
170{
171 result = m_currentBlock->appendNew<Value>(m_proc, B3::Sqrt, origin(), arg0);
172 return { };
173}
174
175template<> auto B3IRGenerator::addOp<OpType::F64Ge>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
176{
177 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterEqual, origin(), arg0, arg1);
178 return { };
179}
180
181template<> auto B3IRGenerator::addOp<OpType::I64GtS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
182{
183 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
184 return { };
185}
186
187template<> auto B3IRGenerator::addOp<OpType::I64GtU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
188{
189 result = m_currentBlock->appendNew<Value>(m_proc, B3::Above, origin(), arg0, arg1);
190 return { };
191}
192
193template<> auto B3IRGenerator::addOp<OpType::I64Eqz>(ExpressionType arg0, ExpressionType& result) -> PartialResult
194{
195 Value* temp4 = constant(Int64, 0);
196Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), temp4, arg0);
197result = temp0;
198 return { };
199}
200
201template<> auto B3IRGenerator::addOp<OpType::F64Div>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
202{
203 result = m_currentBlock->appendNew<Value>(m_proc, B3::Div, origin(), arg0, arg1);
204 return { };
205}
206
207template<> auto B3IRGenerator::addOp<OpType::F32Add>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
208{
209 result = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
210 return { };
211}
212
213template<> auto B3IRGenerator::addOp<OpType::I64Or>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
214{
215 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitOr, origin(), arg0, arg1);
216 return { };
217}
218
219template<> auto B3IRGenerator::addOp<OpType::I32LeU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
220{
221 result = m_currentBlock->appendNew<Value>(m_proc, B3::BelowEqual, origin(), arg0, arg1);
222 return { };
223}
224
225template<> auto B3IRGenerator::addOp<OpType::I32LeS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
226{
227 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessEqual, origin(), arg0, arg1);
228 return { };
229}
230
231template<> auto B3IRGenerator::addOp<OpType::I64Ne>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
232{
233 result = m_currentBlock->appendNew<Value>(m_proc, B3::NotEqual, origin(), arg0, arg1);
234 return { };
235}
236
237template<> auto B3IRGenerator::addOp<OpType::I64Clz>(ExpressionType arg0, ExpressionType& result) -> PartialResult
238{
239 result = m_currentBlock->appendNew<Value>(m_proc, B3::Clz, origin(), arg0);
240 return { };
241}
242
243template<> auto B3IRGenerator::addOp<OpType::F32Neg>(ExpressionType arg0, ExpressionType& result) -> PartialResult
244{
245 result = m_currentBlock->appendNew<Value>(m_proc, B3::Neg, origin(), arg0);
246 return { };
247}
248
249template<> auto B3IRGenerator::addOp<OpType::I32And>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
250{
251 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), arg0, arg1);
252 return { };
253}
254
255template<> auto B3IRGenerator::addOp<OpType::I32LtU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
256{
257 result = m_currentBlock->appendNew<Value>(m_proc, B3::Below, origin(), arg0, arg1);
258 return { };
259}
260
261template<> auto B3IRGenerator::addOp<OpType::I64Rotr>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
262{
263 Value* temp3 = m_currentBlock->appendNew<Value>(m_proc, B3::Trunc, origin(), arg1);
264Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::RotR, origin(), arg0, temp3);
265result = temp0;
266 return { };
267}
268
269template<> auto B3IRGenerator::addOp<OpType::F64Abs>(ExpressionType arg0, ExpressionType& result) -> PartialResult
270{
271 result = m_currentBlock->appendNew<Value>(m_proc, B3::Abs, origin(), arg0);
272 return { };
273}
274
275template<> auto B3IRGenerator::addOp<OpType::I32LtS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
276{
277 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
278 return { };
279}
280
281template<> auto B3IRGenerator::addOp<OpType::I32Eq>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
282{
283 result = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
284 return { };
285}
286
287template<> auto B3IRGenerator::addOp<OpType::F64Copysign>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
288{
289 Value* temp6 = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg1);
290Value* temp12 = constant(Int64, 0x8000000000000000);
291Value* temp4 = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), temp6, temp12);
292Value* temp17 = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg0);
293Value* temp23 = constant(Int64, 0x7fffffffffffffff);
294Value* temp15 = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), temp17, temp23);
295Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::BitOr, origin(), temp4, temp15);
296Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), temp2);
297result = temp0;
298 return { };
299}
300
301template<> auto B3IRGenerator::addOp<OpType::F32ConvertSI64>(ExpressionType arg0, ExpressionType& result) -> PartialResult
302{
303 result = m_currentBlock->appendNew<Value>(m_proc, B3::IToF, origin(), arg0);
304 return { };
305}
306
307template<> auto B3IRGenerator::addOp<OpType::I64Rotl>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
308{
309 Value* temp3 = m_currentBlock->appendNew<Value>(m_proc, B3::Trunc, origin(), arg1);
310Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::RotL, origin(), arg0, temp3);
311result = temp0;
312 return { };
313}
314
315template<> auto B3IRGenerator::addOp<OpType::F32Lt>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
316{
317 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
318 return { };
319}
320
321template<> auto B3IRGenerator::addOp<OpType::F64ConvertSI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
322{
323 result = m_currentBlock->appendNew<Value>(m_proc, B3::IToD, origin(), arg0);
324 return { };
325}
326
327template<> auto B3IRGenerator::addOp<OpType::F64Eq>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
328{
329 result = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
330 return { };
331}
332
333template<> auto B3IRGenerator::addOp<OpType::F32Le>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
334{
335 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessEqual, origin(), arg0, arg1);
336 return { };
337}
338
339template<> auto B3IRGenerator::addOp<OpType::F32Ge>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
340{
341 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterEqual, origin(), arg0, arg1);
342 return { };
343}
344
345template<> auto B3IRGenerator::addOp<OpType::I32ShrU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
346{
347 result = m_currentBlock->appendNew<Value>(m_proc, B3::ZShr, origin(), arg0, arg1);
348 return { };
349}
350
351template<> auto B3IRGenerator::addOp<OpType::F32ConvertUI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
352{
353 Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::ZExt32, origin(), arg0);
354Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::IToF, origin(), temp2);
355result = temp0;
356 return { };
357}
358
359template<> auto B3IRGenerator::addOp<OpType::I32ShrS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
360{
361 result = m_currentBlock->appendNew<Value>(m_proc, B3::SShr, origin(), arg0, arg1);
362 return { };
363}
364
365template<> auto B3IRGenerator::addOp<OpType::I32GeU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
366{
367 result = m_currentBlock->appendNew<Value>(m_proc, B3::AboveEqual, origin(), arg0, arg1);
368 return { };
369}
370
371template<> auto B3IRGenerator::addOp<OpType::F64Ceil>(ExpressionType arg0, ExpressionType& result) -> PartialResult
372{
373 result = m_currentBlock->appendNew<Value>(m_proc, B3::Ceil, origin(), arg0);
374 return { };
375}
376
377template<> auto B3IRGenerator::addOp<OpType::I32GeS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
378{
379 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterEqual, origin(), arg0, arg1);
380 return { };
381}
382
383template<> auto B3IRGenerator::addOp<OpType::I32Shl>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
384{
385 result = m_currentBlock->appendNew<Value>(m_proc, B3::Shl, origin(), arg0, arg1);
386 return { };
387}
388
389template<> auto B3IRGenerator::addOp<OpType::F64Floor>(ExpressionType arg0, ExpressionType& result) -> PartialResult
390{
391 result = m_currentBlock->appendNew<Value>(m_proc, B3::Floor, origin(), arg0);
392 return { };
393}
394
395template<> auto B3IRGenerator::addOp<OpType::I32Xor>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
396{
397 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitXor, origin(), arg0, arg1);
398 return { };
399}
400
401template<> auto B3IRGenerator::addOp<OpType::F32Abs>(ExpressionType arg0, ExpressionType& result) -> PartialResult
402{
403 result = m_currentBlock->appendNew<Value>(m_proc, B3::Abs, origin(), arg0);
404 return { };
405}
406
407template<> auto B3IRGenerator::addOp<OpType::F64Min>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
408{
409 Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
410Value* temp7 = m_currentBlock->appendNew<Value>(m_proc, B3::BitOr, origin(), arg0, arg1);
411Value* temp14 = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
412Value* temp22 = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
413Value* temp28 = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
414Value* temp20 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp22, arg1, temp28);
415Value* temp12 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp14, arg0, temp20);
416Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp2, temp7, temp12);
417result = temp0;
418 return { };
419}
420
421template<> auto B3IRGenerator::addOp<OpType::F32Mul>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
422{
423 result = m_currentBlock->appendNew<Value>(m_proc, B3::Mul, origin(), arg0, arg1);
424 return { };
425}
426
427template<> auto B3IRGenerator::addOp<OpType::I64Sub>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
428{
429 result = m_currentBlock->appendNew<Value>(m_proc, B3::Sub, origin(), arg0, arg1);
430 return { };
431}
432
433template<> auto B3IRGenerator::addOp<OpType::I32ReinterpretF32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
434{
435 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg0);
436 return { };
437}
438
439template<> auto B3IRGenerator::addOp<OpType::I32Add>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
440{
441 result = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
442 return { };
443}
444
445template<> auto B3IRGenerator::addOp<OpType::F64Sub>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
446{
447 result = m_currentBlock->appendNew<Value>(m_proc, B3::Sub, origin(), arg0, arg1);
448 return { };
449}
450
451template<> auto B3IRGenerator::addOp<OpType::I32Or>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
452{
453 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitOr, origin(), arg0, arg1);
454 return { };
455}
456
457template<> auto B3IRGenerator::addOp<OpType::I64LtU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
458{
459 result = m_currentBlock->appendNew<Value>(m_proc, B3::Below, origin(), arg0, arg1);
460 return { };
461}
462
463template<> auto B3IRGenerator::addOp<OpType::I64LtS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
464{
465 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
466 return { };
467}
468
469template<> auto B3IRGenerator::addOp<OpType::F64ConvertSI64>(ExpressionType arg0, ExpressionType& result) -> PartialResult
470{
471 result = m_currentBlock->appendNew<Value>(m_proc, B3::IToD, origin(), arg0);
472 return { };
473}
474
475template<> auto B3IRGenerator::addOp<OpType::I64Xor>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
476{
477 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitXor, origin(), arg0, arg1);
478 return { };
479}
480
481template<> auto B3IRGenerator::addOp<OpType::I64GeU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
482{
483 result = m_currentBlock->appendNew<Value>(m_proc, B3::AboveEqual, origin(), arg0, arg1);
484 return { };
485}
486
487template<> auto B3IRGenerator::addOp<OpType::I64Mul>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
488{
489 result = m_currentBlock->appendNew<Value>(m_proc, B3::Mul, origin(), arg0, arg1);
490 return { };
491}
492
493template<> auto B3IRGenerator::addOp<OpType::F32Sub>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
494{
495 result = m_currentBlock->appendNew<Value>(m_proc, B3::Sub, origin(), arg0, arg1);
496 return { };
497}
498
499template<> auto B3IRGenerator::addOp<OpType::F64PromoteF32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
500{
501 result = m_currentBlock->appendNew<Value>(m_proc, B3::FloatToDouble, origin(), arg0);
502 return { };
503}
504
505template<> auto B3IRGenerator::addOp<OpType::F64Add>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
506{
507 result = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
508 return { };
509}
510
511template<> auto B3IRGenerator::addOp<OpType::I64GeS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
512{
513 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterEqual, origin(), arg0, arg1);
514 return { };
515}
516
517template<> auto B3IRGenerator::addOp<OpType::I64ExtendUI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
518{
519 result = m_currentBlock->appendNew<Value>(m_proc, B3::ZExt32, origin(), arg0);
520 return { };
521}
522
523template<> auto B3IRGenerator::addOp<OpType::I32Ne>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
524{
525 result = m_currentBlock->appendNew<Value>(m_proc, B3::NotEqual, origin(), arg0, arg1);
526 return { };
527}
528
529template<> auto B3IRGenerator::addOp<OpType::F64ReinterpretI64>(ExpressionType arg0, ExpressionType& result) -> PartialResult
530{
531 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg0);
532 return { };
533}
534
535template<> auto B3IRGenerator::addOp<OpType::F32Eq>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
536{
537 result = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
538 return { };
539}
540
541template<> auto B3IRGenerator::addOp<OpType::I64Eq>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
542{
543 result = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
544 return { };
545}
546
547template<> auto B3IRGenerator::addOp<OpType::F32Floor>(ExpressionType arg0, ExpressionType& result) -> PartialResult
548{
549 result = m_currentBlock->appendNew<Value>(m_proc, B3::Floor, origin(), arg0);
550 return { };
551}
552
553template<> auto B3IRGenerator::addOp<OpType::F32ConvertSI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
554{
555 result = m_currentBlock->appendNew<Value>(m_proc, B3::IToF, origin(), arg0);
556 return { };
557}
558
559template<> auto B3IRGenerator::addOp<OpType::I32Eqz>(ExpressionType arg0, ExpressionType& result) -> PartialResult
560{
561 Value* temp4 = constant(Int32, 0);
562Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), temp4, arg0);
563result = temp0;
564 return { };
565}
566
567template<> auto B3IRGenerator::addOp<OpType::I64ReinterpretF64>(ExpressionType arg0, ExpressionType& result) -> PartialResult
568{
569 result = m_currentBlock->appendNew<Value>(m_proc, B3::BitwiseCast, origin(), arg0);
570 return { };
571}
572
573template<> auto B3IRGenerator::addOp<OpType::I64ShrS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
574{
575 Value* temp3 = m_currentBlock->appendNew<Value>(m_proc, B3::Trunc, origin(), arg1);
576Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::SShr, origin(), arg0, temp3);
577result = temp0;
578 return { };
579}
580
581template<> auto B3IRGenerator::addOp<OpType::I64ShrU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
582{
583 Value* temp3 = m_currentBlock->appendNew<Value>(m_proc, B3::Trunc, origin(), arg1);
584Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::ZShr, origin(), arg0, temp3);
585result = temp0;
586 return { };
587}
588
589template<> auto B3IRGenerator::addOp<OpType::F64Sqrt>(ExpressionType arg0, ExpressionType& result) -> PartialResult
590{
591 result = m_currentBlock->appendNew<Value>(m_proc, B3::Sqrt, origin(), arg0);
592 return { };
593}
594
595template<> auto B3IRGenerator::addOp<OpType::I64Shl>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
596{
597 Value* temp3 = m_currentBlock->appendNew<Value>(m_proc, B3::Trunc, origin(), arg1);
598Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Shl, origin(), arg0, temp3);
599result = temp0;
600 return { };
601}
602
603template<> auto B3IRGenerator::addOp<OpType::F32Gt>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
604{
605 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
606 return { };
607}
608
609template<> auto B3IRGenerator::addOp<OpType::I32WrapI64>(ExpressionType arg0, ExpressionType& result) -> PartialResult
610{
611 result = m_currentBlock->appendNew<Value>(m_proc, B3::Trunc, origin(), arg0);
612 return { };
613}
614
615template<> auto B3IRGenerator::addOp<OpType::I32Rotl>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
616{
617 result = m_currentBlock->appendNew<Value>(m_proc, B3::RotL, origin(), arg0, arg1);
618 return { };
619}
620
621template<> auto B3IRGenerator::addOp<OpType::I32Rotr>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
622{
623 result = m_currentBlock->appendNew<Value>(m_proc, B3::RotR, origin(), arg0, arg1);
624 return { };
625}
626
627template<> auto B3IRGenerator::addOp<OpType::I32GtU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
628{
629 result = m_currentBlock->appendNew<Value>(m_proc, B3::Above, origin(), arg0, arg1);
630 return { };
631}
632
633template<> auto B3IRGenerator::addOp<OpType::I64ExtendSI32>(ExpressionType arg0, ExpressionType& result) -> PartialResult
634{
635 result = m_currentBlock->appendNew<Value>(m_proc, B3::SExt32, origin(), arg0);
636 return { };
637}
638
639template<> auto B3IRGenerator::addOp<OpType::I32GtS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
640{
641 result = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
642 return { };
643}
644
645template<> auto B3IRGenerator::addOp<OpType::F64Neg>(ExpressionType arg0, ExpressionType& result) -> PartialResult
646{
647 result = m_currentBlock->appendNew<Value>(m_proc, B3::Neg, origin(), arg0);
648 return { };
649}
650
651template<> auto B3IRGenerator::addOp<OpType::F64Max>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
652{
653 Value* temp2 = m_currentBlock->appendNew<Value>(m_proc, B3::Equal, origin(), arg0, arg1);
654Value* temp7 = m_currentBlock->appendNew<Value>(m_proc, B3::BitAnd, origin(), arg0, arg1);
655Value* temp14 = m_currentBlock->appendNew<Value>(m_proc, B3::LessThan, origin(), arg0, arg1);
656Value* temp22 = m_currentBlock->appendNew<Value>(m_proc, B3::GreaterThan, origin(), arg0, arg1);
657Value* temp28 = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
658Value* temp20 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp22, arg0, temp28);
659Value* temp12 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp14, arg1, temp20);
660Value* temp0 = m_currentBlock->appendNew<Value>(m_proc, B3::Select, origin(), temp2, temp7, temp12);
661result = temp0;
662 return { };
663}
664
665template<> auto B3IRGenerator::addOp<OpType::I64LeU>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
666{
667 result = m_currentBlock->appendNew<Value>(m_proc, B3::BelowEqual, origin(), arg0, arg1);
668 return { };
669}
670
671template<> auto B3IRGenerator::addOp<OpType::I64LeS>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
672{
673 result = m_currentBlock->appendNew<Value>(m_proc, B3::LessEqual, origin(), arg0, arg1);
674 return { };
675}
676
677template<> auto B3IRGenerator::addOp<OpType::I64Add>(ExpressionType arg0, ExpressionType arg1, ExpressionType& result) -> PartialResult
678{
679 result = m_currentBlock->appendNew<Value>(m_proc, B3::Add, origin(), arg0, arg1);
680 return { };
681}
682
683
684} } // namespace JSC::Wasm
685
686#endif // ENABLE(WEBASSEMBLY)
687
688